JPH1091220A - Programmable controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the programmable controller which can lighten the load on a system MPU and re-execute a user program fast even when the execution of an interruption program is interposed. SOLUTION: The system MPU 2 once informed of interruption by an interruption unit 1 saves internal data regarding a currently executed user program by a ladder instruction execution part 4, but the system MPU 2 controls a control register 7 of the ladder instruction execution part 3 in this case and an internal state saving/reloading mechanism 9 of the ladder instruction execution part 4 saves the internal data in a data memory 5. After the interruption, the system MPU 2 controls the control register 7 of the ladder instruction execution part 4 and the internal state saving/reloading mechanism 9 of the ladder instruction execution part 4 saves the internal data in the ladder instruction execution part 4 from the data memory 5.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a programmable controller, and more particularly to a programmable controller in which a system MPU controls the entire apparatus.

[0002]

2. Description of the Related Art In a programmable controller, during execution of a user program, it may be necessary to temporarily stop the execution of the currently executing user program to execute an interrupt program.

In such a case, conventionally, the system MPU writes out the internal data necessary for re-execution of the program currently being executed one by one to a work area of the system memory to prepare for the re-execution of the program.

[0004]

However, in the conventional programmable controller as described above, when executing the interrupt program, the system MPU is used.
When writing data necessary for re-execution of a program currently being executed to a work area of the system memory, control is performed to write necessary data one by one to a work area of the system memory.

For this reason, there is a problem that the load on the system MPU is large and the user program cannot be re-executed at high speed.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a programmable controller which can reduce the load on the system MPU and can re-execute a user program at high speed even when an interrupt program is executed. .

[0007]

To achieve the above object, the present invention provides a ladder instruction executing means for executing a ladder instruction including a normal program and an interrupt program, and data for executing the ladder instruction. In a programmable controller having a memory, during execution of a normal program, if there is a request to execute an interrupt program, an internal data saving means for saving the internal data of the currently executing ladder instruction execution means to the data memory; Internal data restoring means for restoring the internal data saved in the data memory to the ladder instruction executing means when the execution of the program is completed.

The present invention also provides a ladder instruction executing means for executing a ladder instruction including a normal program and an interrupt program, and a programmable controller having a data memory for executing the ladder instruction. The ladder instruction execution means is controlled to execute the interrupt program instead of the normal program when an interrupt program execution request is issued during execution.

According to the present invention, in a programmable controller having a ladder instruction executing means for executing a ladder instruction including a normal program and an interrupt program, and a data memory for executing the ladder instruction, When an interrupt program execution request is received, the internal data of the currently executing ladder instruction executing means is saved in the data memory by the internal data saving means. The internal data saved in the memory is restored to the ladder instruction execution means.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the programmable controller according to the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a schematic configuration of an embodiment of the present invention. In FIG. 1, a programmable controller 10 includes a system MPU 2 and a ladder instruction execution unit 4 connected to a system bus 8, an interrupt unit 1 connected to the system MPU 2, and an instruction memory 3 connected to the ladder instruction execution unit 4. It comprises a data memory 5.

The system MPU 2 controls the entire programmable controller 10. In this embodiment, when an interrupt is notified from the interrupt unit 1, the system MPU 2 controls the ladder instruction execution unit 4 to execute the user. Stop the program and execute the interrupt program.

When an interrupt occurs during execution of a user program, the interrupt unit 1 notifies the system MPU 2 of the occurrence, and executes the interrupt program. Note that the interrupt unit 1 operates asynchronously with the system MPU 2 and the ladder instruction execution unit 4 and notifies an interrupt.

An instruction memory 3 is a memory in which a user program is stored, and includes a normal program 31 and an interrupt program 3.
2 is stored, and when an interrupt occurs, the interrupt program 32 is executed.

The ladder instruction execution unit 4 executes a user program stored in the instruction memory 3 and normally operates independently of the system MPU 2, and writes an execution result to the data memory 5.

The data memory 5 serves as a work information area for I / O (input / output) contact information and execution of a user program executed by the ladder instruction execution unit 4. In this embodiment, the data memory 5 is particularly executed when an interrupt occurs. The internal data of the ladder instruction execution unit 4 is saved in this memory.

The ladder instruction execution unit 4 saves the internal data of the ladder instruction execution unit 4 to the data memory 5 when the interrupt program 32 is executed. 9 is provided.

Here, the status register 6 notifies the state of the ladder instruction execution unit 4 to the system MPU 2 and has a 16-bit width as shown in FIG.
It has an operating bit, a restoring bit, and a saving bit.

The fact that the operating bit is 1 indicates that the ladder instruction execution unit 4 is executing the user program stored in the instruction memory 3. The user program in this case includes a normal program 31 and an interrupt program 32.

The fact that the saving bit is 1 indicates that the internal data of the ladder instruction execution unit 4 at that time is being saved in the data memory 5 in order to execute the interrupt program 32. .

The fact that the restoring bit is 1 means that the execution of the interrupt program 32 has been completed, so that the ladder instruction execution unit 4 saved in the data memory 5 to execute the normal program again. This indicates that the internal data is being restored to the ladder instruction execution unit 4.

The fact that each of the operating bit, the saving bit, and the restoring bit is 0 indicates that the device is not currently operating, is being saved, or is not being restored.

The control register 7 is provided in the system MPU 2
The ladder instruction execution unit 4 is controlled by a command from the ladder instruction execution unit 4 and has a 16-bit width as shown in FIG.
It has a start bit, a stop bit, a restoration bit, and a save bit.

Here, when 1 is written to the start bit, it indicates that there is a start command from the system MPU 2 to the ladder instruction execution unit 4. This start command is issued when the execution of the user program is once stopped and then restarted.

When 1 is written to the stop bit,
This indicates that a stop command has been issued from the system MPU 2 to the ladder instruction execution unit 4. The stop command is issued when the internal data of the ladder instruction execution unit 4 is saved in the data memory 5 and when the saved data is restored in the ladder instruction execution unit 4.

When 1 is written to the save bit, it indicates that a save instruction has been issued from the system MPU 2 to the ladder instruction execution unit 4. The save command is issued when the internal data of the ladder instruction execution unit 4 is saved in the data memory 5.

When 1 is written to the restoration bit, it indicates that there is a restoration instruction from the system MPU 2 to the ladder instruction execution unit 4. The restoration instruction is issued when the ladder instruction execution unit 4 restores the data saved in the data memory 5.

Note that the fact that 0 is written in the start bit, stop bit, restoration bit, and save bit indicates that the respective commands have not been issued.

The internal state saving / restoring mechanism 9 saves the internal data at the time of occurrence of the interrupt in the data memory 5 under the control of the control register 7 or saves the internal data in the data memory 5 when the interrupt processing is completed. A process of restoring the internal data to the ladder instruction execution unit 4 is performed. Therefore, the system MPU 2 can perform the save processing and the restoration processing of the internal data at the time of the occurrence of the interrupt only by controlling the control register 7, thereby reducing the load on the system MPU 2 and the time from the occurrence of the interrupt to the restart of the user program. Has the effect of reducing

The operation described above will now be described with reference to FIGS. 3 and 4 when the interrupt notification is sent from the interrupt unit 1 to the system MPU 2.

In the idle state in which the system MPU 2 is performing normal processing (step 100), when there is an interrupt notification from the interrupt unit 1 to the system MPU 2 (step 101), the system MPU 2 determines the cause of the interrupt. It is determined whether it is necessary to execute the interrupt program 32 (step 102).

If it is determined that the interrupt program 32 need not be executed (NO in step 102), the process returns to step 101, but it is determined that the interrupt program 32 needs to be executed ( Y in step 102
ES) First, the ladder instruction execution unit 4 is stopped. This is executed by writing 1 to the stop bit of the control register 7 according to a command from the system MPU 2.

After writing 1 to the stop bit of the control register 7, it is checked whether the ladder instruction execution unit 4 has stopped by reading the stop bit of the status register 6 (step 106).

If the stop bit is 0 and the ladder instruction execution unit 4 is not stopped (N in step 106)
O) The process of step 106 is repeated. If the stopped bit is 1 and the ladder instruction execution unit 4 is stopped (YES in step 106), the internal data of the ladder instruction execution unit 4 is saved (step S106). 108). This is executed by writing 1 to the save bit of the control register 7 according to a command from the system MPU 2.

When the process of saving the internal data of the ladder instruction execution unit 4 is started, it is checked whether the saving of the internal data to the data memory 5 is completed (step 110). This is checked by reading the save bit of the status register 6.

If the saving bit is 1 and the saving is not completed (NO in step 110), step 11 is executed.
0 is repeated, but if the saving bit is 0 and the saving is completed (YES in step 110), then the address of the interrupt program 32 is set. (Step 11
2).

When the address of the interrupt program 32 is set, the interrupt program 32 is executed. This is executed by writing 1 to the start bit of the control register 7 in accordance with a command from the system MPU 2 (step). 114).

Subsequently, it is checked whether or not the interrupt program has been completed (step 116). This is checked by reading the operating bit of the status register 6.

If the operating bit is 1 and the interrupt program is not completed (NO in step 116), the process of step 116 is repeated. However, if the operating bit is 0 and the interrupt program is completed. If (step 116
Then, the internal data of the ladder instruction execution unit 4 is restored (step 118). This is the system MPU
In response to a command from 2, the restoration bit of the control register 7 becomes 1
Is executed by writing.

When the process of restoring the internal data of the ladder instruction execution unit 4 is started, it is checked whether or not the restoration of the internal data has been completed (step 120). This is checked by reading the restoring bit of the status register 6.

If the bit being restored is 1 and the restoration is not completed (NO in step 120), step 12 is executed.
The process of 0 is repeated. If the bit being restored is 0 and the restoration is completed (YES in step 120), the ladder instruction execution unit 4 is restarted next (step 122). This is executed by writing 1 to the start bit of the control register 7 according to a command from the system MPU 2.

Then, the system MPU 2 enters the idle state again (step 124), and waits for an interrupt notification from the interrupt unit 1.

As described above, the system MPU 2 causes the ladder instruction execution unit 4 to execute the interruption program when the interruption notification is received from the interruption unit 1. In this case, the control register 7 of the ladder instruction execution unit 4 Just by controlling, it is possible to save and restore internal data when an interrupt occurs.
This has the effect of reducing the load on the system MPU 2 and the time from the occurrence of an interrupt to the resumption of the user program.

[0044]

As described above, according to the present invention, a ladder instruction execution means for executing a ladder instruction including a normal program and an interrupt program, and a programmable memory having a data memory for executing the ladder instruction are provided. In the controller, if there is a request to execute the interrupt program during the execution of the normal program, the internal data saving means saves the internal data of the currently executing ladder instruction executing means to the data memory and terminates the execution of the interrupt program. Then, since the internal data saved in the data memory is restored to the ladder instruction executing means by the internal data restoring means, the load on the system MPU and the like can be reduced, and high-speed operation can be performed even when an interrupt program is executed. A programmable controller that can re-execute the user program An effect such as can be obtained rollers.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an overall configuration of an embodiment of a programmable controller according to the present invention.

FIG. 2 is an explanatory diagram of a status register and a control register used in the programmable controller shown in FIG.

FIG. 3 is a flowchart showing an interrupt processing procedure performed by a system MPU when an interrupt notification is received from an interrupt unit.

FIG. 4 is a flowchart showing a processing procedure of an interrupt performed by a system MPU when an interrupt notification is received from an interrupt unit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Interrupt unit 2 System MPU 3 Instruction memory 4 Ladder instruction execution part 5 Data memory 6 Status register 7 Control register 8 System bus 9 Internal state saving / restoring mechanism 10 Programmable controller 31 Normal program 32 Interrupt program

Claims (4)

[Claims] 1. A programmable controller having a ladder instruction execution means for executing a ladder instruction including a normal program and an interrupt program, and a data memory for executing the ladder instruction. Internal data saving means for saving the internal data of the currently executing ladder instruction execution means to the data memory when there is a request to execute the interrupt program; and internal data saving to the data memory when the execution of the interrupt program is completed. And an internal data restoration unit for restoring the ladder instruction execution unit in the ladder instruction execution unit. 2. A programmable controller comprising: a ladder instruction executing means for executing a ladder instruction including a normal program and an interrupt program; and a programmable controller having a data memory for executing the ladder instruction. A programmable controller having a control means for controlling the ladder instruction execution means so as to execute an interrupt program in place of execution of a normal program when an execution request of the interrupt program is issued. 3. The control means includes: a stop instruction means for instructing the ladder instruction execution means to stop the execution of the currently executed normal program; and a current internal data of the ladder instruction execution means. Evacuation instructing means for instructing evacuation to the data memory, activation instructing means for instructing execution of a ladder instruction including a normal program and an interrupt program, and restoration of the internal data saved in the data memory to the ladder instruction executing means 3. The programmable controller according to claim 2, further comprising: a restoration instructing unit that instructs to perform the operation. 4. The ladder instruction executing means includes: an operating determining means for determining whether a ladder instruction is currently being executed; a saving determining means for determining whether or not internal data is currently being saved to the data memory; Restoring determination means for determining whether or not the internal data currently saved in the data memory is being restored to the ladder instruction execution means. The control means stops execution of the ladder instruction by the operation determination means. Is instructed to save the current internal data to the data memory only when it is determined that the internal data has been saved to the data memory only by the evacuation determination means. Instructs the activation instructing means to activate the interrupt program, and transmits the data to the restoration instructing means only when the in-operation discriminating means determines that the execution of the ladder instruction is stopped. When the internal data saved in the data memory is instructed to be restored to the ladder instruction executing means, and it is determined that the internal data saved in the data memory is restored to the ladder instruction executing means by the in-restoration determining means. 4. The programmable controller according to claim 3, wherein only the activation instruction means is instructed to activate a normal program.