JPH05232512A - Liquid crystal display device - Google Patents

Abstract

PURPOSE:To make electric charging characteristics uniform between an input side and a far end by making the channel size W/L of a switching element larger at the far end than on the gate signal input side. CONSTITUTION:Switching elements 1 are formed of TFTs, which have their drains connected to drain lines DL4, their gates connected to gate lines GL2, and their sources connected to picture element electrodes 20. The W/L of the switching elements 1 is small on the gate signal input side of the gate lines GL2 and large at the far ends. The switching elements 1 are therefore large in drain current at the far ends and reduced in ON resistance, so that the time constant that the switching elements 1 have becomes small. A delay time due to the line resistance of the gate lines GL2 is corrected with the time constant to make the electric charging characteristics uniform. Further, even when only the W or L is varied, the same operation is obtained eventually by varying the W/L.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly to a liquid crystal display device in which flicker due to charge characteristics of gate signals is suppressed.

[0002]

2. Description of the Related Art An active matrix type liquid crystal display device using a thin film transistor (TFT) is used as a display for a portable television, a video monitor and a liquid crystal projector. As a detailed explanation of this technical trend, there is "Flat Panel Display 1991" issued by Nikkei BP. Although liquid crystal display devices having various structures are described therein, an active matrix liquid crystal display device using a TFT will be described here.

This active matrix liquid crystal display device has a structure as shown in FIG. 4, for example. First there is a transparent insulating substrate, for example a glass substrate (11). On the glass substrate (11), a gate (12) and an auxiliary capacitance electrode (13), which are constituent elements of the TFT, are formed on, for example, Mo-.
It is made of Ta alloy or the like. Furthermore, SiNx is formed on the entire surface.
A film (14) made of is laminated. Then, on the SiNx film (14) corresponding to the gate (12), a non-doped amorphous silicon film (15) and N ^+.
Type amorphous silicon films (16) are laminated, and a semiconductor protective film (17) is provided between the two layers of amorphous silicon films (15) and (16). Then, on the N ⁺ type amorphous silicon film (16),
Source electrode (18) and drain electrode (1
9) is provided as a laminated body of Mo and Al, for example.
Furthermore, the SiN corresponding to the auxiliary capacitance electrode (13)
On the x film (14), the pixel electrode (2
0) is provided and is electrically connected to the source electrode (18). Further, for protection of the entire surface, a SiN _x film (21) is passivated and an alignment film (2
2) is attached.

Another glass substrate (23) is provided so as to face the glass substrate (11).
3) A counter electrode (25) is provided on it. A light-shielding film (24) is provided in a portion facing the TFT, a common counter electrode (25) is formed on the entire surface, and an alignment film (26) is attached thereon. And this pair of glass substrates (11) (23)
Liquid crystal (27) is injected between them to form a liquid crystal display device.

As shown in FIG. 5, each pixel of the liquid crystal display device is arranged in a matrix by connecting the drain and gate of the TFT to the drain line DL and the gate line GL arranged in a matrix. The shaded liquid crystal capacitance C _LC is formed between the pixel electrode (20) and the counter electrode (25), and the non-hatched auxiliary capacitance C _SC is formed between the pixel electrode (20) and the auxiliary capacitance electrode (13). The parasitic capacitance C _GS is formed between the gate (12) and the source electrode (18).

[0006]

In such a liquid crystal display device, since a large number of pixels are connected to one gate line GL for display, the gate signal supplied from the gate line GL is at the input side and the far end. However, there is a problem that a brightness gradient and a partial flicker occur depending on the charging characteristics. Specifically, as the liquid crystal panel becomes larger, the gate line GL becomes longer and the line resistance becomes larger at the far end. Therefore, as shown in FIG. 6, the pulse-shaped gate shown by the solid line is used.
The input signal has a sharp shape on its input side, but its waveform is attenuated by its resistance and capacitance components at the far end of the gate line GL. That is, as shown by the dotted line, the far end pixel electrode cannot be sufficiently charged. As a result, for example, in the case of normally white, the gate line GL
Although the pixel is black on the input side of, the same black signal is grayed at the end.

The coupling down potential ΔV is

[0008]

[Equation 1]

Is given by As described above, since the attenuation of the gate signal becomes larger at the far end, the voltage amplitude value ΔV _{G of the} gate signal becomes smaller at the far end than the input side of the gate line GL, therefore ΔV is given by Obviously, the value changes at the input side and the far end. As a result, the optimum counter electrode potentials shown in FIG. 5 do not match on the input side and the far end, resulting in partial flicker.

[0010]

SUMMARY OF THE INVENTION The present invention has been made in view of these problems, and changes the size of W / L, W or L of a switching element between the gate signal input side and the far end. Thus, a liquid crystal display device having significantly improved charging characteristics is realized.

[0011]

According to the present invention, the size of W / L of the switching element is reduced on the input side of the gate line GL and increased at the far end. As a result, the drain current of the switching element increases at the far end, the on-resistance decreases, and the time constant of the switching element decreases. By correcting the delay time due to the line resistance of the gate line GL with this time constant, the charging characteristics can be made uniform.

Even if only W or L is changed, the result is W
/ L is changed, and the same operation is performed.

[0013]

Embodiments of the present invention will be described below with reference to FIGS. FIG. 1 is an equivalent circuit diagram of the liquid crystal display device of the present invention. A large number of gate lines GL are arranged in the horizontal axis direction, and a large number of drain lines DL are arranged so as to be orthogonal to the gate lines GL. Therefore, the gate line G
The L and the drain line DL are insulated and arranged in a matrix or a lattice, and one pixel is formed in a square space formed therebetween. A switching element (1) and a pixel electrode (20) are formed in one pixel.

The switching element (1) is formed of a TFT, the drain is connected to the drain line DL, the gate is connected to the gate line GL, and the source is connected to the pixel electrode (2).
0). The shaded liquid crystal capacitor C _LC is formed between the pixel electrode (20) and the counter electrode (25), and the non-hatched auxiliary capacitor C _SC is formed between the pixel electrode (20) and the auxiliary capacitor electrode (13). There is. The parasitic capacitance C _GS is formed between the gate and the source of the switching element (1).

The feature of the present invention lies in the channel dimension W / L of the switching element (1). That is,
The W / L of the switching element (1) on the gate signal input side of the gate line GL is made small, and the W / L of the far end switching element (1) is made large. In FIG. 1, this relationship is represented by the size of the switching element (1). The parasitic capacitance C _{GS is} also a switching element (1)
The parasitic capacitance C _GS also increases with an increase in W / L, which increases with increasing distance from the distant end to C _GSA <C _GSB <C _GSC .

Next, the structure of the liquid crystal display device will be specifically described with reference to FIG. Since the cross-sectional structure is the same as the conventional one shown in FIG. 4, the planar structure will be described here using the reference numerals of FIG. A large number of hatched gate lines GL (2) are provided on the glass substrate in parallel with the horizontal axis direction, and the auxiliary capacitance line (3) and the auxiliary capacitance electrode connected thereto are provided along the gate line GL (2). (13) are provided in parallel. The gate line GL (3) and the auxiliary capacitance electrode (13) are formed by vapor deposition of Mo-Ta alloy or the like,
The surface is covered with an anodic oxide film (28).

The entire surface is covered with an insulating film (14) made of SiN _x . An amorphous silicon film (15) and an N ⁺ type amorphous silicon film (16) are laminated on the insulating film (14). Then, both amorphous silicon films (15) and (16) are etched to form the amorphous silicon film (1
5) is left, a semiconductor protective film (17) is provided on the channel region, and the N ⁺ -type amorphous silicon film (16) is separated on the semiconductor protective film (17) to form the source region (5) and A drain region (6) is formed. On the source region (5) and the drain region (6), a source electrode (18) and a drain electrode (19) having a laminated structure of M _O and Al are formed. A pixel electrode (20) made of ITO is provided on the remaining portion of the insulating film (14) and is connected to the source region (5) by a source electrode (18). The drain line DL (4) is connected to the drain electrode (1
9) is formed at the same time when the gate line G is formed.
It is arranged so as to be orthogonal to L (2). Further, the gate line GL (2) projects so as to form the gate of the switching element (1) and extends under each channel region.

Further, the auxiliary capacitance electrode (13) extends from the auxiliary capacitance line (3) to below the pixel electrode (20), and its size is the same on the gate signal input side and the far end. Is forming. As shown in the upper part of FIG. 2, the switching element (1) has the channel width W gradually increasing and the channel length L gradually decreasing from the gate signal input side. As a result, W /
L gradually increases toward the far end. Specifically, the delay of the gate line GL is 1 μsec at the input side and 5 at the far end.
If it is μsec, W / L is designed to be 4.2 on the input side and 7.2 at the far end.

There is also a method of gradually increasing the channel width W while keeping the channel length L constant, as shown in the lower part of FIG. Although not shown, there is also a method in which the channel width W is kept constant and the channel length L is gradually reduced toward the far end. Both methods result in W / L increasing toward the far end.

Next, the operating principle of the present invention will be described with reference to FIG. If the liquid crystal capacitance C _LC and the auxiliary capacitance C _SC are the same for each pixel and the sum of both capacitances is 1.2 PF, the delay time of the gate line GL is 1 μsec on the input side of the gate line GL, and the far end Then it will be 5 μsec. On the other hand, a TFT type M that is a switching element (1)
In the OSFET, the drain current _ID is represented by the following formula.

[0021]

[Equation 2]

From this, the drain current I _D changes depending on W / L, and the ON resistance of the switching element (1) can be controlled by selecting W / L. Therefore, C _LC + C _SC / β corresponding to the time constant determined by the sum of the ON resistance, the liquid crystal capacitance C _LC and the auxiliary capacitance C _SC can be selected by W / L, and the gate delay time corresponding to W / L can be selected. You can choose. FIG. 3 is a characteristic diagram showing the relationship in the case where the same charging characteristics are shown on the input side and the far end under the above-mentioned conditions.
If / L is designed to be 4.2 and W / L is designed to be 7.2 at the far end, the delay time of the gate line GL can be corrected.

More specifically, the W / L is 4.
In the case of No. 2, it can be seen from FIG. 3 that the gate delay time is 1 μsec and the switching element (1) is turned off 1 μsec after the gate signal falls. On the other hand, if the W / L is designed to be 7.2, the gate delay time is 5 μsec as shown in FIG. 3, and even if the gate signal falls, the switching element (1) is turned off for 5 μsec.
The N state can be maintained and sufficient charging can be performed. Thereby, the delay time of the gate line GL can be corrected.

The coupling down potential ΔV can also be improved by the present invention. By reducing the W / L of the switching element (1) on the input side, ΔV _G becomes
It is attenuated by the delay time. As a result, the difference from ΔV _G at the far end, which is attenuated by the line resistance of the gate line GL, becomes small. Further, the parasitic capacitance C _{GS is} also reduced by reducing W / L, and the coupling down potential Δ
V works so as to become small. On the other hand, on the far end side, ΔV _G becomes smaller due to the line resistance of the gate line GL, but
By making / L large, the parasitic capacitance C _GS becomes large and the coupling down potential ΔV becomes large. As a result, the coupling-down potential ΔV can be equalized between the gate signal input side and the far end.

[0025]

According to the present invention, the gate line is formed by utilizing the gate delay time by forming the W / L of the switching element (1) at the far end larger than the gate signal input side. Since the GL delay can be compensated, the charging characteristics on the input side and the far end can be made uniform.

Further, according to the present invention, by increasing the W / L of the switching element (1) at the far end, the parasitic capacitance C _GS at the far end can be increased and the coupling down potential ΔV can be made uniform. As a result, even a large-sized liquid crystal display device can suppress the brightness inclination and partial flicker, and can obtain a uniform display.

[Brief description of drawings]

FIG. 1 is a circuit diagram illustrating an equivalent circuit diagram of a liquid crystal display device according to the present invention.

FIG. 2 is a plan view illustrating a pixel structure of a liquid crystal display device according to the present invention.

FIG. 3 is a characteristic diagram illustrating an operation principle of the liquid crystal display device according to the present invention.

FIG. 4 is a cross-sectional view illustrating a conventional liquid crystal display device.

FIG. 5 is a circuit diagram illustrating an equivalent circuit diagram of a conventional liquid crystal display device.

FIG. 6 is a waveform diagram illustrating the operation principle of a conventional liquid crystal display device.

[Explanation of symbols]

1 Switching Element 2 Gate Line GL 3 Auxiliary Capacitance Line 4 Drain Line DL 5 Source Region 6 Drain Region 11 Glass Substrate 12 Gate 13 Auxiliary Capacitance Electrode 14 Insulating Film 15 Amorphous Silicon Film 16 N ⁺ Type Amorphous Silicon Film 17 Semiconductor Protection Films 18 and 19 Source electrode, drain electrode 20 Pixel electrode 27 Liquid crystal

Claims (3)

[Claims] 1. A drain line and a gate line arranged in a matrix, a pixel electrode arranged in a matrix between both lines, an auxiliary capacitance electrode extending under the pixel electrode, and the drain line. In a liquid crystal display device comprising a switching element in which a drain is connected to the gate line and a gate is connected to the pixel electrode in the source, and a liquid crystal material provided between the pixel electrode and a counter electrode, W / L of the switching element is A liquid crystal display device, characterized in that the size at the far end is formed larger than that at the gate signal input side. 2. A drain line and a gate line arranged in a matrix, a pixel electrode arranged in a matrix between both lines, an auxiliary capacitance electrode extending under the pixel electrode, and the drain line. In a liquid crystal display device comprising a switching element in which a drain is connected to the gate line and a gate is connected to the pixel electrode in the source, and a liquid crystal material provided between the pixel electrode and a counter electrode, W of the switching element is gated. A liquid crystal display device, characterized in that the size at the far end is formed to be larger than that at the input side of the signal. 3. A drain line and a gate line arranged in a matrix, a pixel electrode arranged in a matrix between both lines, an auxiliary capacitance electrode extending under the pixel electrode, and the drain line. In a liquid crystal display device comprising a switching element in which a drain is connected to the gate line and a gate is connected to the pixel electrode in the source, and a liquid crystal material provided between the pixel electrode and a counter electrode, L of the switching element is gated. A liquid crystal display device characterized in that the size of the far end is smaller than that of the input side of the signal.