JP2008026513A - Display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display device capable of preventing the occurrence of the shading and stripe unevenness due to the wiring resistance of a gate pulse. <P>SOLUTION: A resistance 300 is inserted between a gate of a TFT 114 of a pixel circuit 101 and wiring 200 of a scanning line WSL. At this time, the resistance having a resistance value as great as that of the TFT is arranged (inserted) near the output end of a buffer 1,041 of a write scanner 104. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a display device such as an organic EL (Electroluminescence) display in which pixel circuits each having an electro-optic element whose luminance is controlled by a current value are arranged in a matrix, and in particular, an insulation provided inside each pixel circuit. The present invention relates to a so-called active matrix display device in which a current value flowing through an electro-optic element is controlled by a gate type field effect transistor.

In an image display device, such as a liquid crystal display, an image is displayed by arranging a large number of pixels in a matrix and controlling the light intensity for each pixel in accordance with image information to be displayed.
This is the same for an organic EL display or the like, but the organic EL display is a so-called self-luminous display having a light emitting element in each pixel circuit, and has a higher image visibility than a liquid crystal display. There are advantages such as unnecessary and high response speed.
The luminance of each light emitting element is greatly different from a liquid crystal display or the like in that a color gradation is obtained by controlling the luminance of the light emitting element according to the current value flowing therethrough, that is, the light emitting element is a current control type.

  In the organic EL display, as with the liquid crystal display, a simple matrix method and an active matrix method can be used. However, although the former has a simple structure, it is difficult to realize a large and high-definition display. Due to the problems, active matrix systems have been actively developed to control the current flowing through the light-emitting elements inside each pixel circuit by means of active elements provided inside the pixel circuit, generally TFTs (Thin Film Transistors). ing.

FIG. 1 is a block diagram showing a configuration of a general organic EL display device.
As shown in FIG. 1, the display device 1 includes a pixel array unit 2 in which pixel circuits (PXLC) 2 a are arranged in an m × n matrix, a horizontal selector (HSEL) 3, a light scanner (WSCN) 4, a horizontal Data lines DTL1 to DTLn selected by the selector 3 and supplied with data signals corresponding to luminance information, and scanning lines WSL1 to WSLm selectively driven by the write scanner 4 are provided.
The horizontal selector 3 and the light scanner 4 may be formed on the polycrystalline silicon or may be formed around the pixel by MOSIC or the like.

FIG. 2 is a circuit diagram showing a configuration example of the pixel circuit 2a of FIG. 1 (see, for example, Patent Documents 1 and 2).
The pixel circuit in FIG. 2 has the simplest circuit configuration among many proposed circuits, and is a so-called two-transistor driving circuit.

2 includes a p-channel thin film field effect transistor (hereinafter referred to as TFT) 11 and TFT 12, a capacitor C11, and an organic EL element (OLED) 13 which is a light emitting element. In FIG. 2, DTL indicates a data line, and WSL indicates a scanning line.
Since organic EL elements often have rectifying properties, they are sometimes referred to as OLEDs (Organic Light Emitting Diodes). In FIG. 2 and others, the symbol of a diode is used as a light-emitting element. It does not require rectification.
In FIG. 2, the source of the TFT 11 is connected to the power supply potential VCC, and the cathode (cathode) of the light emitting element 13 is connected to the ground potential GND. The operation of the pixel circuit 2a in FIG. 2 is as follows.

Step ST1 :
When the scanning line WSL is in a selected state (here, at a low level) and the write potential Vdata is applied to the data line DTL, the TFT 12 becomes conductive and the capacitor C11 is charged or discharged, and the gate potential of the TFT 11 becomes Vdata.

Step ST2 :
When the scanning line WSL is in a non-selected state (here, high level), the data line DTL and the TFT 11 are electrically disconnected, but the gate potential of the TFT 11 is stably held by the capacitor C11.

Step ST3 :
The current flowing through the TFT 11 and the light emitting element 13 has a value corresponding to the gate-source voltage Vgs of the TFT 11, and the light emitting element 13 continues to emit light with a luminance corresponding to the current value.
The operation of selecting the scanning line WSL and transmitting the luminance information given to the data line to the inside of the pixel as in step ST1 is hereinafter referred to as “writing”.
As described above, in the pixel circuit 2a of FIG. 2, once Vdata is written, the light emitting element 13 continues to emit light with a constant luminance until it is rewritten next time.

As described above, in the pixel circuit 2a, the value of the current flowing through the EL light emitting element 13 is controlled by changing the gate application voltage of the TFT 11 serving as the drive transistor.
At this time, the source of the p-channel drive transistor is connected to the power supply potential VCC, and the TFT 11 always operates in the saturation region. Therefore, the constant current source has a value represented by the following formula 1.

(Equation 1)
Ids = 1/2 · μ (W / L) Cox (Vgs− | Vth |) ² (1)

  Here, μ is the carrier mobility, Cox is the gate capacity per unit area, W is the gate width, L is the gate length, and Vgs is the gate source of the TFT 11. The inter-voltage and Vth indicate the threshold value of the TFT 11, respectively.

  In the simple matrix type image display device, each light emitting element emits light only at the selected moment, whereas in the active matrix, as described above, the light emitting element continues to emit light even after the writing is completed. In comparison, the peak luminance and peak current of the light emitting element can be lowered, and this is particularly advantageous in a large-sized and high-definition display.

  FIG. 3 is a diagram showing a change with time of current-voltage (IV) characteristics of the organic EL element. In FIG. 33, the curve indicated by the solid line indicates the characteristic in the initial state, and the curve indicated by the broken line indicates the characteristic after change with time.

In general, the IV characteristics of an organic EL element deteriorate as time passes, as shown in FIG.
However, since the two-transistor drive in FIG. 2 is driven at a constant current, a constant current continues to flow through the organic EL element as described above, and even if the IV characteristic of the organic EL element deteriorates, the emission luminance deteriorates with time. There is nothing.

  The pixel circuit 2a shown in FIG. 2 is composed of a p-channel TFT. However, if it can be composed of an n-channel TFT, a conventional amorphous silicon (a-Si) process can be used in TFT fabrication. It becomes like this. Thereby, the cost of the TFT substrate can be reduced.

  Next, a basic pixel circuit in which transistors are replaced with n-channel TFTs will be described.

  FIG. 4 is a circuit diagram showing a pixel circuit in which the p-channel TFT in the circuit of FIG. 2 is replaced with an n-channel TFT.

  The pixel circuit 2b in FIG. 4 includes n-channel TFTs 21 and 22, a capacitor C21, and an organic EL element (OLED) 23 that is a light emitting element. In FIG. 4, DTL indicates a data line, and WSL indicates a scanning line.

  In the pixel circuit 2b, the drain side of the TFT 21 as a drive transistor is connected to the power supply potential VCC, and the source is connected to the anode of the EL element 23, thereby forming a source follower circuit.

  FIG. 5 is a diagram showing operating points of the TFT 21 and the EL element 23 as drive transistors in the initial state. In FIG. 5, the horizontal axis represents the drain-source voltage Vds of the TFT 21, and the vertical axis represents the drain-source current Ids.

As shown in FIG. 5, the source voltage is determined by the operating point of the TFT 21 as the drive transistor and the EL element 23, and the voltage has a different value depending on the gate voltage.
Since the TFT 21 is driven in a saturation region, a current Ids having a current value of the equation shown in the above equation 1 is supplied with respect to Vgs with respect to the source voltage at the operating point.

USP 5,684,365 JP-A-8-234683

The pixel circuit described above is the simplest circuit, but actually, a drive transistor connected in series with the OLED, a TFT for mobility and threshold cancellation, and the like are provided.
These TFTs generate a gate pulse by a vertical scanner arranged on both sides or one side of an active matrix organic EL display panel, and this pulse signal is applied to a desired TFT gate of a pixel circuit arranged in a matrix through a wiring. Is done.
When there are two or more TFTs to which this pulse signal is applied, the timing for applying each pulse signal is important.

However, as shown in FIG. 6, the pulse resistance is affected by the wiring resistance r of the wiring 41 that applies the pulse signal to the gate of the transistor (TFT) in the pixel circuit 4 through the buffer 40 at the final stage of the write scanner. Delay and transient change occur. For this reason, a timing shift occurs, and shading and unevenness occur.
The wiring resistance to the gate of the transistor in each pixel circuit 2a increases as the distance from the scanner increases.
Therefore, when the both ends of the panel are compared, for example, a difference occurs in the mobility correction period, resulting in a difference in luminance.
In addition, since there is a deviation from the optimal mobility correction period, there is a disadvantage that pixels that cannot completely correct the variation in mobility appear and are visually recognized as streaks.

  An object of the present invention is to provide a display device capable of suppressing the occurrence of shading and uneven stripes due to the wiring resistance of a gate pulse.

  A display device according to a first aspect of the present invention includes a plurality of pixel circuits arranged in a matrix and including at least one transistor whose conduction state is controlled by receiving a drive signal to a control terminal, and the pixel circuit is formed. At least one scanner for outputting a drive signal to a control terminal of the transistor, and at least one drive wiring for connecting the control terminals of the transistors of a plurality of pixel circuits in common and transmitting a drive signal from the scanner; The drive wiring is formed to include a configuration that averages signal delays due to wiring resistance differences according to the distance from the output terminal of the drive signal of the scanner.

  A display device according to a second aspect of the present invention includes a plurality of pixel circuits arranged in a matrix and including transistors whose conduction state is controlled by receiving a drive signal to a gate, and a matrix arrangement of the pixel circuits. A first, second, third, and fourth data line that is wired for each column and that supplies a data signal to which a data signal corresponding to luminance information is supplied, and a drive signal to a gate of a transistor that forms the pixel circuit. First, second, third, and fourth drives in which the gates of the transistors of a plurality of pixel circuits in the same row are connected in common and drive signals from the first to fourth scanners are propagated, respectively. The pixel circuit includes a wiring and first, second, third, and fourth reference potentials, and the pixel circuit includes an electro-optical element whose luminance is changed by a flowing current, the first and second nodes, , The first A current supply line is formed by the pixel capacitor connected between the node and the second node, the drain end and the source terminal, and the current is supplied according to the potential of the gate connected to the second node. A driving transistor for controlling a current flowing through the supply line; a first reference potential; a first switch transistor connected to a drain terminal of the driving transistor; the first node; and the third third reference potential. A second switch transistor connected in between, a third switch transistor connected between the second node and a fourth reference potential, and connected between the data line and the second node. A fourth switch transistor, and between the first reference potential and the second reference potential, the first switch, the current supply line of the driving transistor, the first node And the electro-optic element are connected in series, the first drive wiring is connected to the gate of the first switch transistor, the second drive wiring is connected to the gate of the fourth switch transistor, The third drive wiring is connected to the gate of the second switch transistor, the fourth drive wiring is connected to the gate of the third switch transistor, and at least one of the first to fourth drive wirings. One drive wiring is formed so as to include a configuration that averages the signal delay due to the wiring resistance difference according to the distance from the output terminal of the drive signal of the scanner.

  Preferably, resistors are respectively disposed between the drive wiring and the gates of the corresponding transistors.

  Preferably, the resistance value is set higher as the resistance is closer to the output end of the drive signal of the scanner.

  Preferably, the resistor is formed as a multilayer wiring.

  Preferably, the drive wiring is formed so that the line width increases as the distance from the drive signal output end of the scanner increases.

  Preferably, the drive wiring is divided into a plurality of sections, and the line width in each section is formed so that the line width increases as the distance from the output end of the drive signal of the scanner increases.

  Preferably, the drive wiring is formed in two layers, and the line width of one layer is formed to be equal as a whole, and the line width of the other layer is formed so as to be farther from the output end of the drive signal of the scanner. Yes.

  According to the present invention, it is possible to suppress the occurrence of shading and unevenness due to the wiring resistance of the gate pulse.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 7 is a block diagram showing a configuration of an organic EL display device employing the pixel circuit according to the embodiment of the present invention.
FIG. 8 is a circuit diagram showing a specific configuration of the pixel circuit according to the present embodiment.

  7 and 8, the display device 100 includes a pixel array unit 102 in which pixel circuits 101 are arranged in an m × n matrix, a horizontal selector (HSEL) 103, a write scanner (WSCN) 104, a drive A scanner (DSCN) 105, a first auto-zero circuit (AZRD1) 106, a second auto-zero circuit (AZRD2) 107, a data line DTL selected by the horizontal selector 103 and supplied with a data signal corresponding to luminance information, a write scanner 104 The scanning line WSL as the second drive wiring selectively driven by the drive, the drive line DSL as the first drive wiring selectively driven by the drive scanner 105, and the fourth drive selectively driven by the first auto-zero circuit 106 First auto-zero line AZL1 as wiring and second auto-zero circuit 07 by a second auto-zero line AZL2 as the third driving wiring to be selectively driven.

As shown in FIGS. 7 and 8, the pixel circuit 101 according to the present embodiment includes a p-channel TFT 111, n-channel TFTs 112 to 115, a capacitor C111, a light emitting element 116 including an organic EL element (OLED: electro-optical element), It has one node ND111 and a second ND112.
A first switch transistor is formed by the TFT 111, a second switch transistor is formed by the TFT 113, a third switch transistor is formed by the TFT 115, and a fourth switch transistor is formed by the TFT 114.
The supply line (power supply potential) of the power supply voltage VCC corresponds to the first reference potential, and the ground potential GND corresponds to the second reference potential. VSS1 corresponds to the fourth reference potential, and VSS2 corresponds to the third reference potential.

In the pixel circuit 101, between the first reference potential (power supply potential VCC in this embodiment) and the second reference potential (ground potential GND in this embodiment), the TFT 111, the TFT 112 as a drive transistor, the first A node ND111 and a light emitting element (OLED) 116 are connected in series. Specifically, the cathode of the light emitting element 116 is connected to the ground potential GND, the anode is connected to the first node ND111, the source of the TFT 112 is connected to the first node ND111, and the drain of the TFT 111 is connected to the drain of the TFT 111. The source of the TFT 111 is connected to the power supply potential VCC.
The gate of the TFT 112 is connected to the second node ND112, and the gate of the TFT 111 is connected to the drive line DSL.
The drain of the TFT 113 is connected to the first node 111 and the first electrode of the capacitor C111, the source is connected to the fixed potential VSS2, and the gate of the TFT 113 is connected to the second auto zero line AZL2. The second electrode of the capacitor C111 is connected to the second node ND112.
The source / drain of the TFT 114 is connected between the data line DTL and the second node ND112. The gate of the TFT 114 is connected to the scanning line WSL.
Further, the source and drain of the TFT 115 are connected between the second node ND112 and the predetermined potential Vss1, respectively. The gate of the TFT 115 is connected to the first auto zero line AZL1.

  As described above, in the pixel circuit 101 according to the present embodiment, the capacitor C111 as the pixel capacitance is connected between the gate and the source of the TFT 112 as the drive transistor, and the source potential of the TFT 112 is connected to the TFT 113 as the switch transistor during the non-light emission period. The threshold voltage Vth is corrected by connecting to a fixed potential through the TFT 112 and connecting between the gate and drain of the TFT 112.

In the display device 100 of this embodiment, in order to improve shading and unevenness due to pulse delay due to the wiring resistance of the wiring to which the driving pulse applied to the gate of the TFT (transistor) in the pixel circuit 101 is applied. The resistance value of the wiring leading to the gate of the TFT of the pixel is adjusted so that the resistance value increases as it is closer to the final stage (output stage) of the vertical scanner, and the resistance value decreases as it is farther away.
Measures against this shading and stripe unevenness are performed on at least the scanning line WSL or the driving line DSL among the scanning line WSL, the driving line DSL, and the auto zero lines AZL1 and AZL2.
Hereinafter, some countermeasure examples will be described. However, in the following description, an example in which measures are taken for the scanning line WSL is shown.

FIG. 9 is a diagram for explaining a first countermeasure example for improving shading and uneven stripes.
In FIG. 9, reference numeral 1041 denotes a buffer at the final stage (output stage) of the write scanner 104, which is formed as a CMOS buffer of a PMOS transistor PT1 and an NMOS transistor NT1.

In the example of FIG. 9, a resistor 300 is inserted between the gate of the TFT 114 of the pixel circuit 101 and the wiring 200 of the scanning line WSL.
At this time, a resistor having a larger resistance value is disposed (inserted) in the TFT closer to the output terminal of the buffer 1041 of the write scanner 104.
The resistance value of the resistor 300 to be inserted is desirably set so that the sum of the wiring resistance r × n from the scanner output end to the gate of the TFT and the insertion resistor 300 is as equal as possible.
The resistor itself may be a wiring having a high resistance value such as Mo (molybdenum).

FIG. 10 is a diagram for explaining a second countermeasure example for improving shading and uneven stripes.
In order to improve shading and stripe unevenness, a multilayer wiring may be used as the wiring between the gate wiring and the gate.
When multilayer wiring is used, the resistance wiring length can be increased as shown in FIG.

FIG. 11 is a diagram illustrating an example of a multi-layered configuration.
In this configuration, the wiring part 200 is pulled up to a new layer 301 by TiAl or the like, and then connected to the gate part 114a of the TFT 114 through a contact. At this time, the resistance value is changed by changing the wiring length and width of the new layer 301.
Al or the like can be used for the new layer 301. At this time, a normal TFT process can be used as the process.
Alternatively, Ag or the like may be used for the new layer 301. At this time, a normal anode process can be adopted as the process.

  By the first and second countermeasure examples, the difference in resistance value from the output terminal of the scanner to each transistor (TFT) can be reduced. As a result, it is possible to improve shading and unevenness caused by the wiring resistance of the gate pulse.

FIG. 12 is a diagram for explaining a third countermeasure example for improving shading and uneven stripes.
In this example, as the distance from the output end of the scanner buffer 1041 increases, the width of the wiring 200A increases.
At this time, the wiring from the gate pulse input end to the output end to the TFT (transistor) in the pixel circuit 101 is divided into a plurality of sections, and the width of each wiring is formed thicker as the distance from the scanner output end increases. To do.

FIG. 13 shows an example of normal wiring, and FIG. 14 shows an example of wiring according to the third countermeasure example.
13 and 14, the wiring from the input end to the output end is divided into four sections, and the boundaries from the gate pulse input end to the output end are denoted as A, B, C, D, and E.

  In the normal example of FIG. 13, when the wiring is 1 and the length of the section is 2 and the sheet resistance coefficient is 1, the resistance value is 2 at the B point, the resistance value is 4 at the C point, and the resistance value is at the D point. The resistance value is 6 and the resistance value is 8 at point E, and the resistance value at the output end is four times the resistance value of the first pixel.

On the other hand, in the wiring example of FIG. 14 according to the present embodiment, the width of the gate pulse wiring 300A is doubled as the distance from the gate pulse input end for each section increases.
At this time, the resistance value at point B is 2, the resistance value at point C is 3, the resistance value at point D is 3.6, the resistance value at point E is 4.1, and the resistance value at the output end is the first pixel It is twice the resistance value, and the influence of the wiring resistance value can be reduced compared to the normal example.
The number of sections to be divided may be any value.

FIG. 15 is a diagram for explaining a fourth countermeasure example for improving shading and uneven stripes.
The wiring 200B for transferring the gate pulse may be divided into two layers, one layer having the same line width 210, and the other layer 220 having a larger wiring width as the distance from the output end of the vertical scanner increases.
Thereby, the difference in resistance value from the output terminal of the scanner to the gate of each transistor (TFT) can be reduced by adding only one layer.

FIG. 16 is a diagram illustrating a second configuration example having multiple layers.
In this configuration, the wiring part 200 is pulled up to the new layer 320 by TiAl or the like.
At this time, the resistance value is changed by changing the wiring width of the new layer 320.
Al or the like can be used for the new layer 320. At this time, a normal TFT process can be used as the process.
Alternatively, Ag or the like may be used for the new layer 320. At this time, a normal anode process can be adopted as the process.

Next, the operation of the above configuration will be described with reference to FIGS. 17A to 17F, focusing on the operation of the pixel circuit.
17A shows a drive signal applied to the drive DSL, FIG. 17B applied a drive signal WS applied to the scanning line WSL, and FIG. 17C applied to the first auto-zero line AZL1. 17D shows the driving signal AZ1, FIG. 17D shows the driving signal auto-zero signal AZ2 applied to the second auto-zero line AZL2, FIG. 17E shows the potential of the second node ND112, and FIG. The potential of the first node ND111 is shown.

The drive signal DS of the drive line DSL by the drive scanner 105 is held at a high level, the drive signal WS to the scanning line WSL by the write scanner 104 is held at a low level, and the drive signal AZ1 to the auto zero line AZL1 by the auto zero circuit 106 is held at a low level. The driving signal AZ2 to the auto zero line AZL2 by the auto zero circuit 107 is held at a high level.
As a result, the TFT 113 is turned on. At this time, a current flows through the TFT 113, and the source potential Vs of the TFT 112 (the potential of the node ND111) drops to VSS2. Therefore, the voltage applied to the EL light emitting element 116 is also 0 V, and the EL light emitting element 116 does not emit light.
In this case, even if the TFT 114 is turned on, the voltage held in the capacitor C111, that is, the gate voltage of the TFT 112 does not change.

Next, in the non-emission period of the EL light emitting element 117, as shown in FIGS. 17C and 17D, the driving signal AZ2 to the auto zero line AZL2 is held at a high level, and the auto cell line AZL1 is applied. The drive signal AZ1 is set to a high level. As a result, the potential of the second node ND112 becomes VSS1.
Then, after the drive signal AZ2 to the auto zero line AZL2 is switched to the low level, the drive signal DS of the drive line DSL by the drive scanner 105 is switched to the low level only for a predetermined period.
Accordingly, the TFT 113 is turned off and the TFT 115 and the TFT 112 are turned on, whereby a current flows through the path of the TFT 112 and the TFT 111, and the potential of the first node rises.
Then, the drive signal DS of the drive line DSL by the drive scanner 105 is switched to the high level, and the drive signal AZ1 is switched to the low level.
As a result, the threshold Vth correction of the drive transistor TFT112 is performed, and the potential difference between the second node ND112 and the first node ND111 becomes Vth.
In this state, after the elapse of a predetermined period, the drive signal WS to the scanning line WSL by the write scanner 104 is held at a high level for a predetermined period, data is written from the data line to the node ND112, and the drive scanner 105 is in the period where the drive signal WS is at a high level. The drive signal DS of the drive line DSL is switched to the high level, and the drive signal WS is eventually switched to the low level.
At this time, the TFT 112 is turned on, the TFT 114 is turned off, and the mobility is corrected.
In this case, since the TFT 114 is off and the gate-source voltage of the TFT 112 is constant, the TFT 112 passes a constant current Ids to the EL light emitting element 116. Accordingly, the potential of the first node ND111 rises to a voltage Vx through which a current Ids flows through the EL light emitting element 116, and the EL light emitting element 116 emits light.
Here, in this circuit as well, the EL element changes its current-voltage (IV) characteristic when the light emission time becomes long. Therefore, the potential of the first node ND111 also changes. However, since the gate-source voltage Vgs of the TFT 112 is maintained at a constant value, the current flowing through the EL light emitting element 117 does not change. Therefore, even if the IV characteristics of the EL light emitting element 116 deteriorate, the constant current Ids always flows and the luminance of the EL light emitting element 116 does not change.

  In the pixel circuit driven in this way, since shading and streak countermeasures due to the delay due to the wiring resistance of the drive signal (pulse) are performed on the entire panel, the image quality of the shading and streak is suppressed. A good image can be obtained.

It is a block diagram which shows the structure of a common organic electroluminescent display apparatus. FIG. 2 is a circuit diagram illustrating a configuration example of a pixel circuit in FIG. 1. It is a figure which shows the time-dependent change of the electric current-voltage (IV) characteristic of an organic EL element. FIG. 3 is a circuit diagram illustrating a pixel circuit in which a p-channel TFT in the circuit of FIG. 2 is replaced with an n-channel TFT. It is a figure which shows the operating point of TFT and EL element as a drive transistor in an initial state. It is a figure for demonstrating the disadvantage by wiring resistance. 1 is a block diagram illustrating a configuration of an organic EL display device that employs a pixel circuit according to an embodiment of the present invention. FIG. 6 is a circuit diagram illustrating a specific configuration of a pixel circuit according to the present embodiment. It is a figure for demonstrating the 1st example of a countermeasure for improving a shading and a stripe unevenness. It is a figure for demonstrating the 2nd example of a countermeasure for improving a shading and a stripe unevenness. It is a figure which shows the example of a structure multilayered. It is a figure for demonstrating the 3rd example of a countermeasure for improving a shading and a stripe unevenness. It is a figure which shows the example of normal wiring. It is a figure which shows the example of wiring according to the 3rd example of a countermeasure. It is a figure for demonstrating the 4th example of a countermeasure for improving a shading and a stripe unevenness. It is a figure which shows the 2nd structural example made multilayer. It is a timing chart for demonstrating operation | movement of this embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 ... Display apparatus, 101 ... Pixel circuit, 102 ... Pixel array part, 103 ... Horizontal selector (HSEL), 104 ... Write scanner (WSCN), 105 ... Drive scanner (DSCN), 106 ... 1st auto drive circuit (AZRD1) 107, second auto-zero circuit (AZRD2), DTL, data line, WSL, scanning line, DSL, drive line, AZL1, AZL2, auto-zero line, 111, p-channel TFT as a switch, 112, drive (drive) N-channel TFTs as transistors, 113 to 1152... N-channel TFTs N as switches, D111... First node, ND112... Second node, 200, 200A, 200B. Layer wiring, 300 ... resistance.

Claims (14)

A plurality of pixel circuits including at least one transistor arranged in a matrix and having a conduction state controlled by receiving a drive signal to a control terminal;
At least one scanner for outputting a drive signal to a control terminal of a transistor forming the pixel circuit;
The control terminals of the transistors of a plurality of pixel circuits are connected in common and have at least one drive wiring through which a drive signal from the scanner is propagated;
The drive wiring is
A display device configured to include a configuration that averages a signal delay due to a wiring resistance difference corresponding to a distance from an output end of a drive signal of the scanner. The display device according to claim 1, wherein resistors are respectively disposed between the drive wirings and the control terminals of the corresponding transistors. The display device according to claim 2, wherein the resistance value is set higher as the resistance is closer to an output end of a drive signal of the scanner. The display device according to claim 3, wherein the resistor is formed by multilayer wiring. The display device according to claim 1, wherein the drive wiring is formed so that the line width increases as the distance from the output end of the drive signal of the scanner increases. The display device according to claim 5, wherein the drive wiring is divided into a plurality of sections, and the line width in each section is formed so that the line width increases as the distance from the output end of the drive signal of the scanner increases. 6. The drive wiring is formed in two layers, and the line width of one layer is formed to be equal as a whole, and the line width of the other layer is formed so as to be farther from the output end of the drive signal of the scanner. The display device described. A plurality of pixel circuits including transistors arranged in a matrix and having a conduction state controlled by receiving a drive signal to the gate;
A data line that is wired for each column with respect to the matrix arrangement of the pixel circuit and is supplied with a data signal according to luminance information;
First, second, third, and fourth scanners that output drive signals to the gates of the transistors forming the pixel circuit;
First, second, third, and fourth drive wirings to which the gates of the transistors of a plurality of pixel circuits in the same row are connected in common and the drive signals from the first to fourth scanners are respectively propagated;
First, second, third and fourth reference potentials,
The pixel circuit is
An electro-optic element whose luminance varies depending on the flowing current;
The first and second nodes;
A pixel capacitor connected between the first node and the second node;
A drive transistor that forms a current supply line with a drain end and a source terminal, and controls a current flowing through the current supply line according to a potential of a gate connected to the second node;
A first reference transistor and a first switch transistor connected to the drain terminal of the driving transistor;
A second switch transistor connected between the first node and the third third reference potential;
A third switch transistor connected between the second node and a fourth reference potential;
A fourth switch transistor connected between the data line and the second node;
The first switch, the current supply line of the driving transistor, the first node, and the electro-optic element are connected in series between the first reference potential and the second reference potential,
The first drive wiring is connected to the gate of the first switch transistor, the second drive wiring is connected to the gate of the fourth switch transistor, and the third drive wiring is connected to the second switch transistor. And the fourth drive wiring is connected to the gate of the third switch transistor,
At least one of the first to fourth drive wirings is
A display device configured to include a configuration that averages a signal delay due to a wiring resistance difference corresponding to a distance from an output end of a drive signal of the scanner. The display device according to claim 8, wherein resistors are respectively disposed between the drive wirings and the gates of the corresponding transistors. The display device according to claim 9, wherein the resistance value is set higher as the resistance is closer to an output end of a drive signal of the scanner. The display device according to claim 10, wherein the resistor is formed by multilayer wiring. The display device according to claim 8, wherein the drive wiring is formed so that the line width increases as the distance from the output end of the drive signal of the scanner increases. The display device according to claim 12, wherein the drive wiring is divided into a plurality of sections, and the line width in each section is formed so that the line width increases as the distance from the output end of the drive signal of the scanner increases. 15. The drive wiring is formed into two layers, and the line width of one layer is formed to be equal as a whole, and the line width of the other layer is formed so as to be farther from the output end of the drive signal of the scanner. The display device described.

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