JPH05219133A - Coded data reception circuit - Google Patents

Abstract

PURPOSE:To make the split transmission of data unnecessary. CONSTITUTION:A communication control circuit 1 receives the data from a communication line 7, and outputs the received data 8 and a received clock 9. A data buffer 4 samples the received data 8 by the received clock 9, and accumulates it. A synchronization detection circuit 2 monitors synchronization detection data included in the received data 8, and if it detects the synchronization detection data, it outputs a synchronization detection signal 11. A counter 3 counts the number of the data between two synchronization detection signals 11 inputted continuously on the basis of the received clock 9, and outputs a count value as count data 12. A memory 5 stores the count data 12 in order as it is inputted. A control circuit 6 reads the count value, i.e., the number of the data of a coding unit from the memory 5 as data length information 13, and reads the data of the number expressed by this information from the data buffer 4 by outputting a read-out clock 15.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for receiving data encoded in units of a predetermined number of data.

[0002]

2. Description of the Related Art Conventionally, when transmission data is coded in units of a predetermined number of data and the receiving side needs to handle the data in coding units, the transmitting side divides the data into unit data and transmits the data. Was.

[0003]

However, when the number of unit data for transmission is made equal to the number of unit data for coding,
When the number of encoded unit data is variable, the number of transmitted unit data also changes, which is disadvantageous in terms of communication efficiency.
On the other hand, when the number of unit data for transmission is a fixed number of data with good communication efficiency, when decoding the encoded data on the receiving side, the data may be interrupted during the decoding, and the data of the encoding unit is continuous. Then, the device that receives and decrypts the data cannot decrypt the data.

An object of the present invention is to provide a coded data receiving circuit which eliminates the need for dividing and transmitting data in order to solve such a problem.

[0005]

According to the present invention, in a data receiving circuit for receiving coded data to which sync detection data indicating the beginning of each coded unit is added, the sync detection is performed from the received data. A synchronization detection circuit for detecting data; a counter for counting the number of data between two consecutive synchronization detection data detected by the synchronization detection circuit; a memory for storing the number of data counted by the counter; A data buffer for accumulating received data, and a read control circuit for taking the number of data stored in the memory as a unit data number and continuously reading the data of each unit data number from the data buffer for each data of each unit data number. It is characterized by having and.

[0006]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 shows an example of a coded data receiving circuit according to the present invention. The coded data to which the sync detection data indicating the head of the coded data is added is input to the receiving circuit for each coding unit of the coded data. The communication control circuit 1 receives such data from the communication line 7, receives the received data 8, the received clock 9, and the data end signal 1
Outputs 0. The data buffer 4 samples the reception data 8 by the reception clock 9 and stores it in the internal memory. The synchronization detection circuit 2 monitors the synchronization detection data included in the received data 8 and outputs the synchronization detection signal 11 when the synchronization detection data is detected. Data number counter 3
Starts counting the number of data based on the reception clock 9 when the synchronization detection signal 11 is input, and outputs the count value up to that time as the count data 12 when the synchronization detection signal 11 is input next. .. At the same time, the count value is cleared and the counting of the number of data is restarted. The data number memory 5 has a FIFO (First In First Out) configuration and stores the count data 12 in the order of input. The read control circuit 6 monitors the sync detection signal 11,
When the synchronization detection signal 11 is input twice or more, it is determined that the data of one coding unit or more is accumulated in the data buffer 4, and the first count value from the data number memory 5, that is, the coding unit The number of data is read as the data length information 13 and set in the internal read counter. Then, the read clock 15 for continuously reading data of one coding unit is output to the data buffer 4, and the data is read from the data buffer 4.

Next, the operation will be described. The communication control circuit 1 is
The data is received from the communication line 7, and the received data 8 and the received clock 9 are output. The data buffer 4 samples the reception data 8 from the communication control circuit 1 by the reception clock 9 and stores it in the internal memory.

On the other hand, the synchronization detection circuit 2 is the communication control circuit 1
The synchronization detection data included in the reception data 8 from is monitored, and when the synchronization detection data is detected, the synchronization detection signal 1
1 is output. Then, when the synchronization detection signal 11 is input, the data number counter 3 starts counting the number of data based on the reception clock 9, and when the synchronization detection signal 11 is input next, the count value up to that point is calculated. Count data 1
Output as 2. At the same time, the count value is cleared and the counting of the number of data is restarted. The data number memory 5 is
The count data 12 from the data number counter 3 is stored in the order of input.

The read control circuit 6 monitors the synchronization detection signal 11, and when the synchronization detection signal 11 is input twice or more,
It is determined that the data of one coding unit or more has been accumulated in the data buffer 4, and the data number of the first coding unit is read from the data number memory 5 as the data length information 13 and set in the internal read counter. .. And 1
The read clock 15 for continuously reading the data for one coding unit is output to the data buffer 4, and the data for one coding unit is read from the data buffer 4. The control circuit 6 decrements the value of the internal counter by 1 each time one clock 15 is output, and when the value of the counter becomes 0, the reading of the data for one encoding unit is completed. Each time the read clock 15 is input from the control circuit 6, the data buffer 4 reads data from its internal memory and outputs it as read data 14. After that, the read control circuit 6 determines the number of sync detection signals 11 from the sync detection circuit 2 and the data buffer 4
Compared with the number of data units of the coding unit read from,
While the former is larger than the latter, the data length information 13 is sequentially read from the memory 5 as described above, and one coding unit of data represented by the information is sequentially read from the data buffer 4.

The communication control circuit 1 outputs a data end signal 10 to the synchronization detection circuit 2 and the control circuit 6 when confirming that the data reception from the communication line 7 has been completed by the communication procedure. As a result, the synchronization detection circuit 2 outputs the synchronization detection signal 11 for ending the counting of the data number of the last coding unit to the data number counter 3, while the control circuit 6 empties the data number memory 5. The data is read from the data buffer 4, and the data read control ends.

[0011]

As described above, according to the present invention, in the data receiving circuit for receiving the coded data to which the sync detection data indicating the head is added for each coded unit of the coded data, A synchronization detection circuit for detecting synchronization detection data from data, a counter for counting the number of data between two consecutive synchronization detection data detected by the synchronization detection circuit, and a memory for storing the number of data counted by this counter. , A data buffer for accumulating received data, and a read control circuit for reading the data of each unit data number from the data buffer continuously for each data of each unit number of data as the unit data number. It is characterized by having. Therefore, in the coded data receiving circuit of the present invention, the sync detection data is detected from the received data, the number of data between the two consecutive sync detection data detected is counted, and the coding unit is based on the count value. It is possible to continuously output the encoded data for each. Therefore, the transmission side does not need to divide and transmit the data, and high communication efficiency can be realized, and further the data of the coding unit can be continuously supplied to the decoding unit.

[Brief description of drawings]

FIG. 1 is a block diagram showing an example of a coded data receiving circuit according to the present invention.

[Explanation of symbols]

 1 Communication Control Circuit 2 Synchronization Detection Circuit 3 Data Number Counter 4 Data Buffer 5 Data Number Memory 6 Read Control Circuit

Claims (2)

[Claims] 1. A data reception circuit for receiving coded data to which sync detection data indicating the beginning of each coded unit is added, and a sync detection circuit for detecting the sync detection data from the received data. A counter for counting the number of data between two consecutive synchronization detection data detected by the synchronization detection circuit, a memory for storing the number of data counted by the counter, and a data buffer for accumulating the received data A read control circuit for reading the data of each unit data number continuously from the data buffer for each data of each unit data number, wherein the number of data stored in the memory is a unit data number. A coded data receiving circuit. 2. The encoded data receiving circuit according to claim 1, wherein the memory is a memory having a FIFO structure.