JPS6228906B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a data compression/reproduction method that improves processing efficiency by compressing and reproducing data to be processed, such as transmission or storage.

(Prior Art) Conventionally, in data processing, compression/reproduction methods have been proposed for the purpose of gradually reducing line costs for data transmission and for reducing storage costs for data storage. In particular, in data transmission, it is customary to collect several codes to form a block, and to transmit this block as a unit. When this block has unique properties, it often includes a group of codes that appear repeatedly in each block or a group of codes that occur and fluctuate slowly. For example, 3 to 4 days worth of data processed by a POS terminal at a store and recorded on a cassette tape typically has a capacity of about 2000 blocks per item. The data includes fixed codes, as exemplified by store codes, date codes that change every 400 to 500, and other loosely fluctuating codes. Also unit price, quantity,
Data such as monetary amounts are usually transmitted using fixed digits, so there are many consecutive zero codes. Conventionally, even such a code group is always transmitted as part of a data block, or, as exemplified in Japanese Patent Publication No. 53-50626, the transmitting side encloses the repeated part in a special code and transmits it, and then the receiving side On the other hand, a method has been adopted in which when a special code is detected, the received data is reproduced using previously received data.

[Problem that the invention seeks to solve]

However, in the conventional example described above, the process of enclosing the repeated part during transmission requires a sufficient understanding of what kind of data is being repeated, and this is done by taking into account changes over time in the repeated part. In order to achieve this, the disadvantage was that an extremely large capacity memory was required to absorb the fluctuations. Such drawbacks are common not only in data transmission but also in data storage. Data processing as used herein is a broad concept that includes various types of processing such as transmission, transfer, and storage.

The present invention has been made in view of the above-mentioned conventional drawbacks, and its purpose is to provide a simple data compression/reproduction method that is effective in processing data that has a high frequency of repeated appearance.

(Means for Solving the Problems) According to the present invention, during compression, the preceding first data block that has already been processed (transmission, storage, etc.; the same applies hereinafter) and the subsequent second data block that is processed immediately thereafter. The number of consecutive matching codes is detected by comparing each intra-block code corresponding to the intra-block code position for both. At the time of compression, the code of the consecutively matched portion of the subsequent second data block is replaced with the number of consecutively matched portions. On the other hand, during reproduction, based on the number of consecutive matches in the subsequent second data block after the above processing and the reproduction code of the preceding first data block that was previously reproduced, the consecutive matching portions of the subsequent second data block are determined. Play the code. Since the present invention has such a configuration, it does not require any large-capacity memory to understand the nature of the repeated data while taking into account the temporal fluctuations of the repeated portion, and is therefore extremely simple, inexpensive, and highly efficient. Reliable data compression and playback can be achieved.

〔Example〕

Hereinafter, the present invention will be explained in more detail by way of embodiments, taking data transmission as an example.

FIG. 1 is an example of a functional block diagram of a transmitting device used in an embodiment of the present invention, in which 1 is a data input terminal, 2, 3, and 4 are shift registers, and 5 is a functional block diagram of a transmitting device used in an embodiment of the present invention.
is the transmission buffer. Shift register 2, 3
is a section 2-1, 2-2, 2-3, .
...and 3-1, 3-2, 3-3..., and shifts by one character each time a shift pulse is input from the signal line 7 at time t ₀ , t ₁ t ₂ ... . Each character is composed of an appropriate number of multiple bits (for example, 9 bits), and the signal lines between shift registers are composed of multiple parallel signal lines corresponding to the above number of bits, but for simplicity, only one signal line is used. It is represented by a line.

FIGS. 2a and 2b are conceptual diagrams illustrating the contents of the shift register at time _t0 . The shift register 3 stores data for one block consisting of information characters A ₀ , A ₁ , _{A 2 .} α, C ₀ , C ₁ . . . G ₃ are stored in the shift register 2. consecutive 2
In order to compare the contents of corresponding positions within the blocks (sections 2-1 and 3-1 in the example of FIG. 1), sections 2-1 and 3-1 are
connected via. Comparator 8 outputs a match signal to counting/control circuit 9 when both characters match. The counting/control circuit 9 counts the character matching signals described above, but has a function of always clearing the previous counted value when the counted value does not increase continuously, and has a function to always clear the counted value until the counted value reaches a predetermined number ( In this embodiment, no control is performed until step 3) is reached. Therefore, at time _t0 , the leading character α of both blocks is compared, and the counting/control circuit 9
counts 1 but does not perform any control.

At time _t1 , the character α in section 2-1 is connected to the signal line 6 and the conducting gate 16.
section 4-2 of shift register 4 through
The character C ₀ shifted from section 2-2 is stored in section 2-1 instead. At the same time, the character α stored in section 3-1 disappears, and in its place, character A ₀ shifted from section 3-2 is stored in section 3-1. At time t ₁ , comparator 8 does not output a coincidence signal, and therefore, as described above, counting/control circuit 9 clears the count value which was 1 at time t ₀ at time t ₁ . Similarly, at times t ₂ , t ₃ , and t ₄ , A ₁ and C ₁ ,
A ₂ and C ₂ and A ₃ and C ₃ are compared, but in either case, the comparator 8 does not output a match signal and the count value of the counting/control circuit 9 is kept at zero.

At time t ₅ , t ₆ , t ₇ , B ₀ , B ₀ , B ₁ in the same order
and B ₁ , B ₂ and B ₂ are compared, and the counting/control circuit 9
The count value of will be 3. At this time, shift register 4
The character B ₀ is stored in the section 4-1, and the character B ₁ is stored in the section 4-2. When the counting/control circuit 9 counts 3, it activates the write circuit 11 via the signal line 10 . The activated write circuit 11 writes a character DLE (character match signal) and a space to each of sections 4-1 and 4-2 via signal lines 12 and 13. As a result, character B ₀ in section 4-1 is rewritten to character DLE, and character B ₁ in section 4-2 is rewritten to character DLE.
is deleted and becomes a space. In parallel with this, the counting/control circuit 9 connects the gate 1 via the signal line 14.
6 and 17 are made non-conductive. The above series of operations is
This is performed between times _t7 and _t8 .

At time _t8 , character _B2 in section 2-1 is output to signal line 6, but
Since gate 16 is non-conductive, transfer to shift register 16 is blocked. Further, since the gate 17 is non-conductive, the shift pulse on the signal line 7 is blocked, and shifting of the character in the register 4 is prohibited. In parallel with this, the comparator 8 compares character B ₃ , which is the new content of section 2-1, with character B ₃ , which is the new content of section 3-1. The circuit 9 counts "4", but since the count value is increasing continuously, it does not perform any other control such as clearing the count value. Similarly, at time _t9 , the counting/control circuit 9 only counts "5" and does not perform any control.

At time t ₁₀ , character E ₀ in section 3-1 and character E 0 in section 2-1
A comparison of _B5 is performed, and the comparison match pulses input to the counting/control circuit 9 are interrupted only after five consecutive pulses. The counting/control circuit 9 has a count value of 3.
In the above case, when an interruption of the coincidence pulse is detected, the section 4
After writing the self-held count value "5" to -2, the own count value is cleared. In addition,
When the count value is less than 3 and an interruption of the comparison match pulse is detected, the count value is not written but only cleared. Subsequently, the counting/control circuit 9 makes the gates 16 and 17 conductive via the signal line 14, and further connects the write circuit 1 via the signal line 10.
Reset 1.

At time _t11 , a shift pulse is supplied to the register 4 via the gate 17 which has regained conduction. As a result, the character DLE in the section 4-1 is transferred to the transmission buffer 5, and the contents of the section 4-1 are replaced with "5" indicating the number of matching characters. On the other hand, the character _B5 in the section 2-1 is transferred to the section 4-2 through the gate 16, which has regained conduction.
be transferred.

The above-described operations are repeated to send characters to the transmission buffer 5. As illustrated in FIG. 2C, compressed transmission data in which three characters are compressed is set in the transmission buffer, and after parallel-to-serial conversion as necessary, it is sent to the transmission terminal 30. . For convenience of explanation, the shift register 2 is assumed to have a capacity for storing one block, but it may be configured to store one character, or it may be configured without the shift register 2 at all.

FIG. 3 is an example of a functional block diagram of a receiving device used in an embodiment of the present invention, in which 31 is a data receiving terminal, 20 is a receiving buffer, 21 and 22 are shift registers, 23 is a DLE detection circuit, and 24 is a receiving buffer. is the decoding/control circuit. The reception buffer 20 receives a compressed data signal as illustrated in FIG. Transfer the character to the shift register 21. The shift register section 21-1 is connected to the DLE detection circuit 23 and the decoding/control circuit 24 via a signal line 25. DLE detection circuit 2
When detecting that the character DLE has been transferred into the section 21-1, it activates the decoding/control circuit 24 via the signal line 32. The activated decoding/control circuit 24 decodes the subsequently transferred character indicating the number of duplicate characters (character "5" in FIG. 2C; the example in FIG. 2 will be followed hereinafter). A starting signal for five cycles of shift pulses is output to the signal line 26. The activation signal causes gate 28 to conduct and inhibit character transfer from receive buffer 20 for five periods of shift pulses. Section 21-
2 and section 22-2 are corresponding character positions within two consecutive blocks.
Therefore, the character DLE in section 21-2
is replaced by character B ₀ in section 22-2. Character “5” shifted into section 21-2 by subsequent shift pulses
is replaced by character B ₁ in section 22-2. Furthermore, section 21-2
The character (space) shifted in is replaced by character B ₂ in section 22-2. Thereafter, similar operations are repeated, and the compressed data signal shown in FIG. 2C is reproduced into the original data signal shown in FIG. 2B.

〔Effect of the invention〕

As explained in detail above, according to the present invention,
Since there is no need for a large-capacity memory to grasp the nature of repeated data in order to constantly compare it with the immediately preceding data, it is possible to achieve extremely simple, inexpensive, and highly reliable data compression and transmission.

The present invention can also be applied as a storage method for a storage device that sequentially stores and reads data. For example, if it is used in magnetic cassette tapes, floppy disks, etc., it is possible to increase the data density relative to the storage capacity.

[Brief explanation of the drawing]

FIG. 1 and FIG. 3 are examples of functional block diagrams of a transmitting device and a receiving device used in an embodiment of the present invention.
FIG. 2 is a conceptual diagram for explaining the operations of FIGS. 1 and 3. FIG. 2, 3, 4, 21, 22...All shift registers, 5...Transmission buffer, 8...Comparator, 9
...Counting/control circuit, 11...Writing circuit, 20
...Reception buffer, 23...DLE detection circuit, 2
4...Decoding/control circuit.

Claims (1)

[Scope of Claims] 1. During compression, the codes within the data block of the preceding first data block that has been processed and the subsequent second data block that is to be processed subsequently are compared in correspondence with the code positions within the data block. Then, the number of consecutively matched codes is counted, and the code of the part of the subsequent second data block that continuously matches the code of the preceding first data block is calculated as the consecutively matched code. At the time of reproduction, based on the number of consecutively matched codes in the subsequent second data block after the processing and the reproduced code of the preceding first data block that was reproduced prior to this, , a data compression/reproduction method characterized in that the code of the consecutively matched part replaced by the number of consecutively matched codes of the subsequent second data block is reproduced into the original code.