JPH05219012A - Demodulation device for synchronous type spread spectrum modulated wave - Google Patents

Abstract

PURPOSE:To provide the demodulation device for the synchronous type SS modulated wave which eliminates the interference disturbance of conventional technology in principle. CONSTITUTION:This device is equipped with an inverse spreading means 3 which inversely spreads a spread spectrum modulated wave by multiplying it by a spread code outputted from a spread code generator 27, a synchronism detecting means 4 which detects the synchronism of the obtained inverse spread modulation output, and a carrier regenerating means 50 which regenerates a carrier according to the obtained inverse spread demodulation output. Further, the device is equipped with frequency dividing means 26 and 27 which divide the frequency of the regenerated carrier to generate clock signals for a spread code generator, suppressing means 49 and 41 which suppress and remove spread noise components in the synchronism detection output, a synchronism detecting means 34 which performs synchronism detection as sliding correlation synchronism acquisition for the output signals of the suppressing means, and control means 35 and Sw which control the number of frequency divisions of the regenerated carrier of the frequency dividing means by using the obtained synchronism detection signal as a control signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a demodulator for demodulating a carrier-modulated synchronous spread spectrum (abbreviated as "SS" hereinafter) modulated wave, and more particularly to a synchronous demodulator that does not require a sync holding function. Type SS modulated wave demodulator (hereinafter also simply referred to as "demodulator"). In the following description, the demodulation device of the present invention is applied to the receiving section of communication equipment, and the transmitting section (modulation circuit) will be described as necessary.

[0002]

TECHNICAL BACKGROUND In recent years, in SS communication, mobile communication using the multiple access method by SS technology has reached a practical range. The main reason for this is that it is necessary to effectively use the frequency because the radio wave resource is finite, whereas it is being proved that the SS signal can contribute to the improvement of the frequency utilization efficiency due to the progress of the technology. In particular, the SS signal is spread over a wide frequency band and the power spectrum density of the modulated wave is very small, so there is little effect on other conventional communication radio waves, etc. Therefore, it can be mixed in existing communication frequency bands. Therefore, the advantage in that respect is also great.
For these reasons, wireless communication by SS is becoming more and more familiar, and in the future, its future potential and developability such as application of communication between mobile bodies mounted on a vehicle are expected.

[0003]

2. Description of the Related Art In SS communication, synchronization acquisition and synchronization holding in reception are basically necessary, and various synchronization acquisition and holding methods have been proposed and put to practical use. Among them, PSK (Pha (Pha
se Shift Keying) Carrier for modulation and S that is secondary modulation
The synchronous SS modulation and demodulation method, in which the SS modulation is performed in a synchronous relationship with the spread code clock signal used for the S modulation, is also known as a method in which the circuit configuration can be somewhat simplified in the reception demodulation. Regarding such a conventional technique, FIG.
The description will be made with reference to FIGS.

FIG. 1 shows a circuit configuration of a modulator on the side of a transmission section for generating a transmission signal for the present demodulator, FIG. 2 shows a circuit configuration of a conventional demodulator for a synchronous SS modulated wave, and FIG. FIG. 4 shows a specific circuit configuration of a signal processing circuit which is a main part of a delay lock loop) type synchronization holding circuit, FIG. 4 shows a synchronization holding characteristic in the DLL type synchronization holding circuit, and FIG. 5 shows a correlation characteristic showing a sliding correlation type synchronization acquisition operation. Are shown respectively.

First, the SS modulator shown in FIG. 1 will be described. Information signal d such as data from the input terminal In1
(t) is the carrier cos for PSK modulation from the oscillator 19.
ωt is supplied to the multiplier 9 for PSK modulation, and the PSK modulation of the information d (t) is performed here, and the PSK modulated wave d (t) cosωt is obtained. Furthermore, the oscillator output is divided by the frequency divider 2
5, a clock signal is generated, and a spread code generator (PNG) 48 generates a spread code p (t) based on the clock signal. Therefore, the spread code p (t) that is output is kept in synchronization with the carrier cosωt. Spread code p
(t) is supplied to the multiplier 10 for spread modulation, where SS
(Spread spectrum) modulation is performed and SS modulated wave p (t) *
d (t) cosωt is generated, is output from the output terminal Out1 via the BPF (bandpass filter) 11, and is transmitted from an antenna (not shown).

Next, the demodulation operation will be described with reference to FIG. The SS modulated wave is received by an antenna (not shown) on the receiver side, and a multiplier 3 for both sliding correlation and despreading demodulation via an input terminal In2 and a BPF 12 and a DLL-type synchronization holding signal processing circuit. (Hereafter, simply "D
LL signal processing circuit "). A spreading code generated by a PNG (spreading code generator) 47 is also supplied to the multiplier 3, and the clock signal for this spreading code is slightly higher than that at the time of holding the synchronization until the synchronization is acquired. It is set by a VCO (voltage controlled oscillator) 21. Therefore, the sliding correlation and the despread demodulation are performed in time series.

The operation leading to synchronization acquisition (establishment) will now be described. The input SS modulated wave p (t) * d (t) cosωt from which unnecessary frequency band components have been attenuated or removed by the BPF 12 is used by the spread code p from the spread code generator 47 in the multiplier 3.
Correlation is performed by multiplication with (t). This spreading code p
(t) is the spread code p (t) generated by the PNG 48 on the receiving side.
Is actually p (t−τ) having a delay of time τ, and is represented by adding Λ (hat) on the letter p of p (t), but here it is used in electronic applications. Due to the restriction of possible characters, it is represented by "ρ (t)". Therefore,
The multiplication output from the multiplier 3 is p (t) * ρ (t) * d (t) cosωt.

The multiplication output is supplied to the multipliers 7 and 8, and the reproduction carrier cos from the VCO 22 is supplied to the multiplier 7.
Synchronous detection is performed by multiplication with (ωt-φ). Therefore, from the multiplier 7, (1/2) p (t) * ρ (t) * d (t) * {cosφ + c
os (2ωt-φ)} is output, and the LPF (low-pass filter) 15 at the next stage removes p (t) * ρ (t) * d (t) cos (2ωt-φ) / 2 components. As a result, p (t) * ρ (t) * d (t) cosφ is obtained. If the value of φ is close to 0, the LPF15 output p (t) * ρ (t) *
The level of d (t) cosφ is about 1/2. On the other hand, the multiplier 5
Is supplied with a carrier of regenerated carrier cos (ωt-φ) from the voltage controlled oscillator (VCO) 22 and sin (ωt-φ) whose phase is shifted by π / 2 in the π / 2 phase shift circuit 23. ing.

Therefore, the output of the multiplier 5 is (-1/2) p (t) *.
ρ (t) d (t) * {sinφ + sin (2ωt-φ)}, and LPF16
Outputs -p (t) * ρ (t) sin φ, but the actual level is close to zero. The outputs of the LPF 15 and LPF 16 are both supplied to the multiplier 6, where multiplication is performed and the output is p ² (t) ρ ² (t) * d ² (t) * (-1/2) sin2φ
Is obtained as an error signal. Such an error signal is further reduced by the loop filter 24 which determines the response time constant of the loop.
After being converted into an error signal of Ksin2φ, it is supplied to the VCO 22 as a control signal. In the carrier reproducing circuit 50 composed of such a round of phase locked loop, PSK demodulation can be simultaneously performed in synchronization with the input carrier.

It is this carrier regeneration circuit 50 that first starts to work after the power of the receiving section in the communication device is turned on. Therefore, after carrier regeneration, the correlation output p (t) * ρ (t) obtained from the LPF 15, That is, 3 centered at the point t ₀ in FIG.
The output based on the angular output characteristic is supplied to the threshold level detection circuit 34 for synchronous acquisition of sliding correlation, and after the synchronous acquisition point SHL is detected here, the output is further supplied to the output (waveform) shaping circuit 35 for synchronization. A constant DC output is obtained from the time of capture. This DC output is supplied to the adder circuit 42, where it is added to the correlation output from the DLL signal processing circuit 36 and then supplied to the VCO 21. The VCO 21 is controlled by the obtained addition output, and the controlled voltage-controlled oscillation output becomes a clock signal for generating the spread code at the time of normal synchronization holding.

Next, the synchronization holding operation will be described. The input SS modulated wave is supplied to the DLL signal processing circuit 36 via the BPF 12. Here, a specific circuit example of the DLL signal processing circuit 36 is shown in FIG. The SS modulated wave is input from the input terminal In3 to the multipliers 7 and 8
Is supplied to. On the other hand, the multiplier 3 is connected to the input terminal In4.
The spread code (a) whose phase is Δt earlier than that of the regular spread code p (t) supplied to (a) and the spread code (b) which is delayed by Δt p (t + Δt) are input terminal In5. , PNG47
More supplied respectively. In the SS method, Δt is the time for one bit of the spread code, that is, one chip time, so
The output of the multiplier 7 is PSK which is the despreading output during normal operation.
It is a modulated wave, and it has a narrow band characteristic that can be transmitted.
Absolute value circuit (or envelope detection circuit) 3
8 are supplied.

Similarly, the output of the multiplier 8 is also supplied to the absolute value circuit 39 via the BPF 44. Therefore, the output of the absolute value circuit 38 becomes a signal which is obtained by multiplying the component of twice the carrier frequency by p (t) * p (t-Δt), and the output of the absolute value circuit 39 similarly shows the carrier frequency. P for double component
It is obtained as a signal multiplied by (t) * p (t + Δt). The respective output signals are supplied to the subtraction circuit 40 to be subtracted, and the characteristics thereof are inverse S-shaped correlation characteristics shown in FIG.
Point (C) is a synchronization holding point. The correlation output thus obtained is output from the output terminal Out3 via the loop filter 28 for processing this into a control signal, and is added to the output of the waveform shaping circuit 35 by the adder circuit 42 of FIG. After that, it is supplied to the VCO 21 and the synchronization is maintained.

[0013]

In such a conventional demodulator, the VCO 22 for carrier reproduction and the VCO for clock generation are used.
There is a problem that it is difficult to operate the circuit stably due to the complexity of the circuit and the increase of the circuit scale because an oscillator is required for both of the CO 21 and a synchronization holding circuit must be used together. It was happening.

[0014]

A demodulation device of the present invention comprises despreading means for despreading by multiplying a spread spectrum modulated wave by a spread code output from a spread code generator,
Synchronous detection means for performing synchronous detection of the obtained despread demodulation output, carrier reproduction means for reproducing a carrier based on the obtained despread demodulation output, and for the spreading code generator by dividing the obtained reproduced carrier. A frequency dividing means for generating a clock signal, a suppressing means for suppressing or eliminating a diffusion noise component in the synchronous detection output, a synchronous detecting means for performing synchronous detection as a sliding correlation synchronous acquisition of the output signal of the suppressing means, The above-mentioned problem is solved by comprising the control means for controlling the reproduction carrier frequency division number of the frequency division means by using the obtained synchronization detection signal as a control signal.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration and operation of one embodiment of the demodulation device of the present invention will be described along with the configuration example shown in FIG. 6 together with the spectrum diagram for explaining the spreading noise suppressing operation of FIG. Figure 6
In, 19 is a correction filter (usually using LPF),
Reference numeral 20 is an inverse circuit, Sw is a changeover switch, 26 and 27 are frequency dividers for dividing the input signal into 1 / N ₁ and 1 / N ₂ , respectively.
Reference numeral 9 is a diffused noise reproducing unit, and the same components as those of the conventional apparatus shown in FIG.

Interference waves that are not removed even by the BPF 12 may sometimes be mixed into the SS signal coming into the input terminal In2 of the demodulator 1 shown in FIG. 6 during transmission {see FIG. 8 (A)}. If such an interference wave is I (t) = cosεt, the input S
The S signal is p (t) * d (t) cosωt + cosεt, and the BPF
At 12, the high frequency components of the spread modulated wave are removed and {p (t)-
p ′ (t)} * d (t) cosωt + cosεt, which is supplied to the multiplier 3 which also serves as despreading and sliding correlation.

When synchronization is established in the demodulator 1, the spreading code generated by the PNG 47 is p (t), and the correction filter 19 produces {p (t) -p '(t)}.
Further, in the reciprocal conversion circuit 20, it is set to {p (t) -p '(t)} ^-1 ,
It is supplied to the multiplier 3. Therefore, the output of the multiplier 3 is d
(t) cosωt + coseqt / {p (t) -p '(t)} (see FIG. 8B) is supplied to the multiplier 4 for synchronous detection and the BPF 13 having a narrow band pass characteristic.

The multiplier 4 multiplies the carrier for coherence detection cos (ωt-φ) output from the VCO 22 and d (t) cosωφ + cos (ωt-εt + φ) / {p (t)-
p ′ (t)}, and is output to the diffusion noise reproducing unit 49 and the subtraction circuit 41 via the LPF 17. In addition, LPF17
The cutoff frequency of is selected as a frequency that can sufficiently transmit the spread frequency band. Further, the change in the amplitude in the above signal expression is omitted for convenience.

Here, the specific structure and function of the diffused noise reproducing section 49 will be described with reference to FIG. FIG. 7 is a block diagram showing an example of the configuration of the diffusion noise reproducing section 49, and the input signals (a) to (c) in FIG. 7 correspond to those shown in FIG. In FIG. 7, reference numeral 30 is a high-pass filter (HPF) for demodulation information removal, and 31 is a frequency characteristic correction circuit including an equalizer and the like.

The output from the LPF 17 is the input terminal In
It is supplied to the HPF 30 via 6. In HPF30,
All signal components existing in the frequency band of the demodulation information are removed {see FIG. 8 (C)} and output to the multiplier 29. The multiplier 29 multiplies the output of the correction filter 19 {p (t) -p '(t)} (see FIG. 8D) and outputs the result to one input terminal of the multiplier 28. At the other input terminal of the multiplier 28, the reciprocal spread code {p (t) -p ′ that has passed through the LPF 14 is sent.
(t)} ^-1 is supplied. The LPF 14 is used to remove the high band part and the side lobe of the main lobe of the frequency spectrum of the reciprocal spread code. Therefore, the low- and middle-frequency components of the main lobe of the reciprocal spreading code {see FIG. 8 (E)}
Only the multiplier 28 will be fed to it, thus
The frequency band component of the demodulation information lost by the HPF 30 is partially restored from the multiplier 28 (FIG. 8).
(F) Reference} is output.

The partial restoration output is supplied to the frequency characteristic correction circuit 31, where the partial restoration in the required frequency band is corrected to complete restoration and is output as a restored composite component {see FIG. 8 (G)}. This restored composite component is supplied to the subtraction circuit 41 of FIG. 6 through the output terminal Out4, where it is subtracted from the sliding correlation output from the multiplier 4 (LPF17) to cancel the composite component. And is greatly attenuated (see FIG. 8 (H)). That is, from the complex output (diffuse noise) generated in the correlation output and the correlation operation time at the time of correlation,
A good correlation output with a CN ratio (signal-to-noise ratio) in which the spread noise is suppressed is obtained, and the spread noise is almost completely removed by the LPF 18, and is output from the terminal Out2 of {see FIG. 8 (I)}. , To a synchronization determination circuit (synchronization acquisition threshold level detection circuit) 34.

In the synchronization determination circuit 34, the synchronization acquisition point SHL (see FIG.
(See reference), and then supplies this to the shaping circuit 35,
A constant DC output is obtained from the time of synchronization acquisition. This DC output is used for the switching operation control signal of the changeover switch Sw. When the DC output is generated, the switch Sw is connected to the frequency divider 26 side, and the regular clock signal from the frequency divider 26 is spread coded. It is supplied to the generator (PNG) 47. As a result, the spreading code output from the PNG 47 becomes p (t), and the normal despreading is performed in the multiplier 3.

That is, the output signal of the shaping circuit 35 is generated when SS synchronization is established, and is not generated when it is asynchronous. With such a function, if some kind of strong disturbance occurs in the SS modulated wave and the process gain of the SS system is exceeded, the SS synchronization is not maintained and the level of the disturbance wave is reduced. SS sync level (sync capture point SHL)
When it goes down, it operates to switch to the sliding correlation operation.

Finally, the carrier reproducing operation will be described. The d (t) cosωt or cosωt component is extracted from the output signal of the multiplier 3 in FIG. 6 by the narrow band characteristic BPF 13 and is supplied to the multipliers 2 and 5 for carrier regeneration. Since the oscillation signal is directly supplied from the VCO 22 to the multiplier 2 and the signal whose phase is further shifted by π / 2 by the π / 2 phase shift circuit 23 is supplied to the multiplier 5, multiplication with the output of the BPF 13 is performed. Performed, cos (ωt-φ) and sin (ωt-φ)
After it becomes a signal including components, it is output to the multiplier 6 via the LPFs 15 and 16, respectively. Therefore, the output of the multiplier 6 becomes p ² (t) * ρ ² (t) * d ² (t) sin2φ, which is converted into an error signal voltage of Ksin2φ by the loop filter 24 and VC
It is supplied to O22 and the oscillation frequency is controlled.

Carrier cos (ω output from VCO 22
t-φ) is supplied to the frequency dividers 26 and 27 of 1 / N ₁ . As described above, the frequency divider 26 converts the VCO output into a regular clock signal when the spread code synchronization is established. The frequency divider 27 performs a frequency division of 1 / N ₂ .
Since the number of frequency divisions is smaller than that of the frequency divider 26, the frequency of the clock signal output from the frequency divider 27 is higher than that during SS synchronization. The outputs of the frequency dividers 26 and 27 are supplied to the changeover switch Sw, but before the SS synchronization is established, the output of the frequency divider 27 is selected as a clock signal and supplied to the PNG 47.

[0026]

As described above, since the demodulator of the present invention is configured to carry out carrier regeneration and synchronous detection independently, the BPF 13 at the input stage of the carrier regeneration circuit 50 can realize a narrow band, which allows The noise level in the information-modulated wave is reduced, and carrier reproduction can be achieved which is hardly affected by jitter due to noise in the input signal. Also,
Since the reproduction carrier is selected from the two types of frequency division outputs to obtain the sliding correlation spreading code and the regular despreading spreading code, the synchronization holding circuit typified by the conventional DLL circuit becomes unnecessary, and It can contribute to further stabilization.

Furthermore, if the jitter in the output of the reproduced carrier is small, the jitter of the clock signal supplied to the spread code generator is also small, so that a good spread code with little jitter can be generated by PNG. Furthermore, the despreading circuit section is provided with the spreading noise suppressing circuit including the spreading noise reproducing section 49 and the subtraction circuit 41, so that even if the level of the interference wave mixed in the SS signal is large, there is a problem of interference. In principle, it contributes to the stability of the operation, the overall circuit configuration is simplified, and it is also advantageous in terms of cost.

[Brief description of drawings]

FIG. 1 is a block diagram of a synchronous SS modulator that generates a transmission signal.

FIG. 2 is a block configuration diagram of a conventional demodulator for a synchronous SS modulated wave.

FIG. 3 is a specific configuration diagram of a DLL-type synchronization holding signal processing circuit which is a main part of a conventional device.

FIG. 4 is a characteristic diagram showing a sync holding characteristic in a DLL-type sync holding signal processing circuit.

FIG. 5 is a correlation characteristic diagram for explaining a sliding correlation type synchronous capturing operation.

FIG. 6 is a block diagram showing an embodiment of a demodulation device of the present invention.

FIG. 7 is a specific circuit configuration diagram of a diffused noise reproducing unit in the device of the present invention.

FIG. 8 is a spectrum diagram for explaining a diffusion noise suppressing (removing) operation in the device of the present invention.

[Explanation of symbols]

1 Demodulator 2-10, 28, 29 Multiplier 11-11, 43, 44 BPF (bandpass filter) 14-18 LPF (low-pass filter) 19 Correction filter (LPF) 20 Inverse circuit 21,22 VCO ( Voltage controlled oscillator) 23 π / 2 phase shift circuit 24 Loop filter 25-27 frequency divider 30 HPF (high-pass filter) 31 Frequency characteristic correction circuit 34 Synchronization determination circuit (threshold level detection circuit) 35 Output shaping circuit 36 DLL Type synchronization holding signal processing circuit 38, 39 Absolute value circuit (envelope detection circuit) 40, 41 Subtraction circuit 42 Addition circuit 47, 48 PNG (spreading code generator) 49 Spreading noise reproducing unit 50 Carrier reproducing circuit Sw changeover switch

Claims (2)

[Claims] 1. A demodulator for receiving and demodulating a spread spectrum modulated wave in which a carrier for PSK modulation and a clock signal for a spread code generator have a synchronous relationship, and the spread code modulated wave is used for the spread spectrum modulated wave. Despreading means for despreading by multiplying by the output spreading code, synchronous detection means for performing synchronous detection of the obtained despread demodulation output, and carrier regeneration based on the obtained despread demodulation output. Carrier reproducing means, frequency dividing means for dividing the reproduced carrier to generate a clock signal for a spread code generator, suppressing means for suppressing or removing the spread noise component in the synchronous detection output, and the suppressing means. A synchronization detecting means for performing synchronization detection as a sliding correlation synchronization acquisition of the output signal, and a reproduction carrier frequency division number of the frequency dividing means using the obtained synchronization detection signal as a control signal. And a control means for controlling the above. 2. The carrier reproducing means and the coherent detection means supply the information modulated wave in the despread demodulation output to the first and second multipliers via a bandpass filter having a narrow band characteristic, and the first and second multipliers. The multiplier multiplies the regenerated carrier from the voltage controlled oscillator and supplies it to the first low pass filter, and the second multiplier shifts the phase of the regenerated carrier by π / 2 before multiplication. To a second low-pass filter, the outputs of these two low-pass filters are multiplied by a third multiplier, and then supplied to a loop filter which gives a response time constant of the loop.
A carrier signal is regenerated by the voltage controlled oscillator based on the output of the loop filter and supplied to a fourth multiplier, and the fourth multiplier multiplies the carrier signal by the despread demodulation output to perform synchronous detection. The demodulator of the synchronous spread spectrum modulated wave according to claim 1, which is configured as described above.