JPH05218053A - Method of processing semiconductor substrate - Google Patents
Method of processing semiconductor substrateInfo
- Publication number
- JPH05218053A JPH05218053A JP4016524A JP1652492A JPH05218053A JP H05218053 A JPH05218053 A JP H05218053A JP 4016524 A JP4016524 A JP 4016524A JP 1652492 A JP1652492 A JP 1652492A JP H05218053 A JPH05218053 A JP H05218053A
- Authority
- JP
- Japan
- Prior art keywords
- single crystal
- heat treatment
- polishing
- semiconductor substrate
- processing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体基材の加工方法
に関し、更に詳しくは、半導体素子、集積回路、およ
び、微細機械機構等に於て、応用されうる単結晶の表面
加工方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for processing a semiconductor substrate, and more particularly to a method for processing a surface of a single crystal which can be applied to a semiconductor device, an integrated circuit, a fine mechanical mechanism and the like. Is.
【０００２】[0002]
【従来の技術】近年、集積回路はその集積度を著しく増
し、それに伴い表面の加工精度もより厳しい条件が課さ
れるようになり、工程途上で表面荒れが生じた場合にこ
れを除去して、平坦、平滑な表面を得ることが要請され
ている。2. Description of the Related Art In recent years, the degree of integration of integrated circuits has remarkably increased, and as a result, severer conditions have been imposed on the surface processing accuracy. If surface roughness occurs during the process, it must be removed. It is required to obtain a flat and smooth surface.
【０００３】単結晶表面を平坦化する加工方法として
は、研磨が一般的である。Polishing is generally used as a processing method for flattening the surface of a single crystal.
【０００４】研磨法は、被研磨面に研磨砥粒を中性、あ
るいはアルカリ性の溶液（ＫＯＨなど）に縣濁した液を
研磨液として、これを滴下しながら、被研磨面をウレタ
ンなどでできた研磨布に押しつけながら擦り合わせるこ
とにより被研磨面を削り取って、被研磨面を平坦化する
ものである。例えばシリコン単結晶表面を研磨により平
坦化する場合、酸化シリコンからなるコロイダルシリカ
を研磨砥粒として、これをアルカリ性の溶液（ＫＯＨな
ど）などに縣濁したものを滴下しながら、研磨を行な
う。In the polishing method, a liquid in which abrasive grains are suspended in a neutral or alkaline solution (KOH or the like) on the surface to be polished is used as a polishing liquid, and the surface to be polished is made of urethane or the like while being dropped. The surface to be polished is flattened by scraping off the surface to be polished by pressing it against a polishing cloth and rubbing it together. For example, when the surface of a silicon single crystal is flattened by polishing, polishing is performed while colloidal silica made of silicon oxide is used as polishing abrasive grains and suspended in an alkaline solution (KOH or the like).
【０００５】その他の平坦化法としては、熱処理による
平坦化が挙げられる。As another flattening method, there is a flattening by heat treatment.
【０００６】Ｓ． Ｎａｋａｓｈｉｍａ， Ｋ． Ｉｚ
ｕｍｉ（Ｊ． Ｍａｔｅｒ． Ｒｅｓ．（１９９０）
Ｖｏｌ．５， Ｎｏ．９， ｐ．１９１８）によれば、
数十ｎｍ径の窪みが無数に存在する荒れた表面を、１２
６０度（窒素中）２時間、ないしは、１３００度（アル
ゴン（含む０．５％酸素）４時間の熱処理することで、
これらの荒れが消失すると報告されている。一方、１１
５０度の熱処理では、表面の荒れは変化しない。S. Nakashima, K .; Iz
umi (J. Mater. Res. (1990)
Vol. 5, No. 9, p. 1918)
A rough surface with numerous dents with a diameter of several tens of nm
By heat treatment at 60 degrees (in nitrogen) for 2 hours or 1300 degrees (argon (including 0.5% oxygen) for 4 hours),
It has been reported that these storms will disappear. On the other hand, 11
The heat treatment at 50 degrees does not change the surface roughness.
【０００７】[0007]
【発明が解決しようとしている課題】上記した研磨によ
る平坦化を図２に示す。図２（ａ）に示すような荒れの
ある単結晶の表面は、研磨により表面層を一定量除去す
ることで図２（ｂ）に示すような平坦、平滑な表面とな
る。図の破線は研磨前の形状である。このように研磨で
は、平坦化をするために表面を一定量除去しなければな
らなかった。しかも、研磨のばら付きにより面内で研磨
量にもばら付きを生じてしまうという問題点がある。し
たがって、単結晶の最表面、あるいはその近傍を利用す
る場合、更には厚さの制御が要求される場合には表面層
を除去する研磨を用いた平坦、平滑化は適さない。さら
に、通常研磨で得られる単結晶の表面層には、研磨によ
る加工歪みや、転位などの欠陥が導入されている。した
がって、研磨に引き続いて数百ｎｍから数ｕｍ、すくな
くとも数十ｎｍのエッチングを行なってこれを除去する
必要がある。FIG. 2 shows the above-mentioned planarization by polishing. The surface of the roughened single crystal as shown in FIG. 2A becomes a flat and smooth surface as shown in FIG. 2B by removing a certain amount of the surface layer by polishing. The broken line in the figure is the shape before polishing. As described above, in polishing, a certain amount of the surface had to be removed in order to flatten the surface. Moreover, there is a problem in that the amount of polishing varies within the surface due to variation in polishing. Therefore, when the outermost surface of the single crystal or its vicinity is used, or when the control of the thickness is required, flattening and smoothing using polishing for removing the surface layer are not suitable. Further, defects such as dislocation and processing strain due to polishing are introduced into the surface layer of a single crystal obtained by ordinary polishing. Therefore, it is necessary to carry out etching of several hundreds nm to several μm, or at least several tens of nm after polishing to remove this.
【０００８】また、半導体のデバイス作製工程は、パー
ティクルを極限まで抑えたクリーンルームで行なわれる
が、研磨工程は発塵工程であり、他工程との分離はもち
ろん、試料の受渡においても、配慮が要求され、デバイ
ス作製途上での研磨は実用的でない。Further, the semiconductor device manufacturing process is performed in a clean room in which particles are suppressed to the utmost limit, but the polishing process is a dusting process, which requires consideration not only in separation from other processes but also in sample delivery. However, polishing during device fabrication is not practical.
【０００９】一方、熱処理による高温熱処理は、１２６
０度を越える高温、かつ長時間であるため、以下のよう
な問題点を生じる。 １）石英管の耐熱温度（１２００度で石英管はまがって
しまう。）を越えるため、半導体プロセスにおいてはＳ
ｉＣ等を用いた特殊仕様の熱処理炉を要する。 ２）シリコンの融点（〜１４１３度）に近い温度である
ため、基体内の温度分布、あるいは、基体の炉への出し
入れ時に生じる温度むらにより、スリップライン等の欠
陥が多数単結晶内に導入されてしまうことがある。 ３）単結晶層に硼素、燐等の不純物をあらかじめ局所的
に導入しておいた場合、これら不純物が拡散し、再分布
が生じる。On the other hand, the high temperature heat treatment is 126
Since the temperature is higher than 0 degree and the time is long, the following problems occur. 1) Since it exceeds the heat resistant temperature of the quartz tube (the quartz tube is bent at 1200 degrees), S in the semiconductor process.
A special heat treatment furnace using iC etc. is required. 2) Since the temperature is close to the melting point of silicon (up to 1413 degrees), many defects such as slip lines are introduced into the single crystal due to the temperature distribution in the substrate or the temperature unevenness that occurs when the substrate is taken in and out of the furnace. It may happen. 3) When impurities such as boron and phosphorus have been locally introduced into the single crystal layer in advance, these impurities diffuse and re-distribute.
【００１０】上記したような問題点を解決するために
は、素子や集積回路等の作製プロセスと同等、あるいは
それ以下の温度でかつ、単結晶表面を除去することな
く、平坦、平滑化することが要請されていた。In order to solve the above-mentioned problems, it is necessary to flatten and smooth the surface of the single crystal without removing the single crystal surface at a temperature equal to or lower than the manufacturing process of elements and integrated circuits. Was requested.
【００１１】本発明は、上記したような問題点及び上記
したような要求に応える半導体基材の加工方法を提案す
ることを目的とする。It is an object of the present invention to propose a method for processing a semiconductor substrate which meets the above-mentioned problems and the above-mentioned requirements.
【００１２】また、本発明は、単結晶表面を結晶性、表
面平坦性が単結晶ウエハ−並に優れた状態に加工するう
えで、生産性、均一性、制御性、コストの面において卓
越した半導体基材の加工方法を提案することを目的とす
る。Further, the present invention is excellent in productivity, uniformity, controllability, and cost in processing a single crystal surface into a state in which crystallinity and surface flatness are as excellent as those of a single crystal wafer. The purpose is to propose a method for processing a semiconductor substrate.
【００１３】[0013]
【課題を解決するための手段および作用】本発明の半導
体基材の加工方法は、表面に単結晶を有する基体を還元
性雰囲気中で熱処理することにより、該単結晶表面を平
坦、平滑化することを特徴とする。According to the method for processing a semiconductor substrate of the present invention, a substrate having a single crystal on its surface is heat-treated in a reducing atmosphere to flatten and smooth the surface of the single crystal. It is characterized by
【００１４】本発明によれば、結晶を除去しないので、
単結晶の厚さを変えることなく、しかも、加工歪み層あ
るいは、スリップライン等の結晶欠陥を導入することな
く、単結晶表面を単結晶ウエハ並に平坦化できる。According to the present invention, since the crystal is not removed,
It is possible to flatten the surface of a single crystal like a single crystal wafer without changing the thickness of the single crystal and without introducing a processing strain layer or a crystal defect such as a slip line.
【００１５】さらに本発明は、熱処理であるので、容易
に多数枚の一括処理が可能であり、しかも、処理温度は
通常半導体プロセスに用いるのと同等な温度であり、か
つ、超高真空も必須でないので、半導体プロセスライン
において、新たな設備投資を要さず、通常用いる熱処理
装置により実現できる。また、他工程と連続した熱処理
とすることも可能である。Further, since the present invention is a heat treatment, it is possible to easily carry out batch processing of a large number of sheets, and the processing temperature is the same as that used in a normal semiconductor process, and an ultrahigh vacuum is also essential. Since this is not the case, no additional capital investment is required in the semiconductor process line, and this can be realized by the heat treatment apparatus normally used. It is also possible to carry out heat treatment continuous with other steps.
【００１６】また本発明によれば、基体表面に凹凸が加
工され、研磨では平坦化できないような局所的な単結晶
領域も、平坦化できる。Further, according to the present invention, unevenness is processed on the surface of the substrate, and a local single crystal region which cannot be flattened by polishing can be flattened.
【００１７】［実施態様例］本発明者らは、シリコン単
結晶表面の微小な荒れの除去について、熱処理を用いる
方法の検討した結果、還元性雰囲気中の熱処理では、デ
バイスプロセスと同等以下の温度の熱処理でシリコン単
結晶表面の荒れを除去できることを見いだした。ここで
いう還元性雰囲気とは、例えば水素を含む雰囲気、ない
しは、水素雰囲気が挙げられる。しかし、これに限定さ
れるものではない。雰囲気をかえて熱処理による表面荒
れの変化を詳細に高分解能走査型電子顕微鏡や原子間力
顕微鏡等を用いて観察したところ、図１（ａ）に示すよ
うな熱処理前の表面の凹凸が、還元性雰囲気中での熱処
理では減少し、図１（ｂ）に示すような平坦な表面を有
する単結晶薄層が得られることを知見するに至った。具
体的な単結晶薄層の表面の結晶の構造を図３（ａ）、
（ｂ）に示す。さらに、研磨等で表面の荒れを除去する
場合には、面内で単結晶層の膜厚に分布を生じせしめる
場合があるが、本発明の還元性雰囲気での熱処理の場合
は、微小な凹凸が除去されるのみで、単結晶自体の膜厚
は変化しない。従って、表面平坦化により、新たな膜厚
ばらつきを生じることはない。[Embodiment Example] As a result of studying a method using heat treatment for removing minute roughness on the surface of a silicon single crystal, the inventors have found that heat treatment in a reducing atmosphere has a temperature equal to or lower than that of the device process. It was found that the heat treatment of can remove the roughness of the silicon single crystal surface. The reducing atmosphere referred to here is, for example, an atmosphere containing hydrogen or a hydrogen atmosphere. However, it is not limited to this. When the atmosphere was changed and the changes in the surface roughness due to the heat treatment were observed in detail using a high resolution scanning electron microscope, an atomic force microscope, etc., the unevenness of the surface before the heat treatment as shown in FIG. 1 (a) was reduced. It has been found that the heat treatment in a neutral atmosphere reduces the amount and a single crystal thin layer having a flat surface as shown in FIG. 1B is obtained. The specific crystal structure of the surface of the single crystal thin layer is shown in FIG.
It shows in (b). Further, when removing the surface roughness by polishing or the like, a distribution of the thickness of the single crystal layer may be generated in the surface, but in the case of the heat treatment in the reducing atmosphere of the present invention, minute unevenness is generated. Is only removed, and the film thickness of the single crystal itself does not change. Therefore, the flattening of the surface does not cause a new variation in film thickness.
【００１８】数ｎｍから数十ｎｍの高さ、数ｎｍから数
百ｎｍの周期の凹凸が観察される単結晶シリコン表面
（図１（ａ））を還元性雰囲気中で熱処理することによ
り、少なくとも高低差が数ｎｍ以下、条件を整えれば、
２ｎｍ以下の単結晶シリコンウエハ並に平坦な表面（図
１（ｂ））に変質せしめられることがわかった。この現
象は、エッチングというよりは、むしろ表面の再構成で
あると考えられる。即ち、荒れた表面では、表面エネル
ギーの高い稜状の部分が無数に存在し、結晶層の面方位
に比して高次の面方位の面が多く表面に露出している
が、これらの領域の表面エネルギーは、単結晶表面の面
方位に依存する表面エネルギーにくらべて高い。還元性
雰囲気の熱処理では、例えば水素の還元作用により表面
の自然酸化膜が水素雰囲気の熱処理により除去され、熱
処理中は常に除去され再付着しないために、表面Ｓｉ原
子の移動のエネルギー障壁は下がる結果、熱エネルギー
により励起されたＳｉ原子が移動し、表面エネルギーの
低い、平坦な表面を構成していくのだと考えられる。従
って、単結晶表面の面方位は低指数であるほど、本発明
による平坦化は促進される。At least by heat-treating the surface of the single crystal silicon (FIG. 1 (a)) in which unevenness having a height of several nm to several tens nm and a period of several nm to several hundred nm is observed, in a reducing atmosphere. If the conditions are adjusted, the height difference is several nm or less,
It was found that the surface could be transformed into a flat surface (Fig. 1 (b)) that was as thin as a single crystal silicon wafer of 2 nm or less. This phenomenon is considered to be surface reconstruction rather than etching. That is, in a rough surface, there are innumerable ridge-shaped portions with high surface energy, and many planes with higher plane orientations are exposed on the surface as compared with the plane orientations of the crystal layer. Has a higher surface energy than the surface energy depending on the plane orientation of the single crystal surface. In the heat treatment in the reducing atmosphere, the natural oxide film on the surface is removed by the heat treatment in the hydrogen atmosphere, for example, due to the reducing action of hydrogen, and the energy barrier for the movement of the surface Si atoms is lowered because it is always removed during the heat treatment and does not reattach. It is considered that Si atoms excited by thermal energy move to form a flat surface with low surface energy. Therefore, the lower the plane orientation of the single crystal surface, the more the planarization according to the present invention is promoted.
【００１９】その結果、窒素雰囲気や、希ガス雰囲気で
は、表面が平坦化しないような１２００℃以下の温度で
も、十分に平坦化がなされる。本発明による平坦化の温
度は、ガスの組成、圧力等によるが、概ね３００℃以上
融点以下の熱処理、より好ましくは、５００℃以上、特
に、１２００℃以下で有効に作用する。また、圧力は還
元性が強いほど高い圧力でも平坦化が促進されるが、概
ね大気圧以下、より好ましくは２００Ｔｏｒｒ以下がの
ぞましい。また、平坦化の進行が遅い場合には、熱処理
時間を延ばすことで同様に平坦な表面を獲ることができ
る。As a result, in a nitrogen atmosphere or a rare gas atmosphere, the surface is sufficiently flattened even at a temperature of 1200 ° C. or lower at which the surface is not flattened. The temperature of the flattening according to the present invention depends on the gas composition, pressure, etc., but the heat treatment is generally performed at 300 ° C. or higher and the melting point or lower, more preferably 500 ° C. or higher, and particularly 1200 ° C. or lower. Further, the higher the reducing property is, the higher the pressure is, so that the flattening is promoted. However, the pressure is generally atmospheric pressure or less, and more preferably 200 Torr or less. When the progress of flattening is slow, a flat surface can be obtained by extending the heat treatment time.
【００２０】また、本現象は表面が清浄な状態で熱処理
することでその進行が開始するのであって、表面に厚く
自然酸化膜が形成されているような場合には、熱処理に
先立って、これを弗酸などによるエッチングで除去して
おくことにより、表面の平坦化の開始が早まる。大面積
に形成される。Further, this phenomenon begins to progress by heat treatment in a state where the surface is clean. If a thick natural oxide film is formed on the surface, this phenomenon is preceded by heat treatment. By removing the P by etching with hydrofluoric acid or the like, the start of surface flattening is accelerated. It is formed in a large area.
【００２１】こうして得られた平坦な単結晶表面は、半
導体素子作製という点から見ても好適に使用することが
できる。The thus obtained flat single crystal surface can be preferably used from the viewpoint of manufacturing a semiconductor device.
【００２２】[0022]
【実施例】以下、具体的な実施例によって本発明を説明
する。EXAMPLES The present invention will be described below with reference to specific examples.
【００２３】（実施例１）表面に５０ｎｍ周期、高さ３
０ｎｍ程度の凹凸が原子間力顕微鏡により表面に観察さ
れる４インチ（１００）単結晶シリコンを、熱処理炉に
設置し、到達真空度０．０１Ｔｏｒｒに引いた後、水素
ガスを導入し、９５０ｄｅｇ℃、８０Ｔｏｒｒで熱処理
を施した。この試料を原子間力顕微鏡により表面の平坦
性を評価したところ、表面のラフネスは水素処理前の荒
れ３０ｎｍが１．５ｎｍと良好になった。(Example 1) 50 nm period on the surface, height 3
4 inch (100) single crystal silicon, on the surface of which unevenness of about 0 nm is observed by an atomic force microscope, is installed in a heat treatment furnace, and after reaching an ultimate vacuum of 0.01 Torr, hydrogen gas is introduced and the temperature is 950 deg. Heat treatment was performed at 80 Torr. When the flatness of the surface of this sample was evaluated by an atomic force microscope, the surface roughness was as good as 1.5 nm when the roughness before the hydrogen treatment was 30 nm.
【００２４】また、透過型電子顕微鏡による断面観察の
結果、Ｓｉ層には新たな結晶欠陥は導入されておらず、
良好な結晶性が維持されていることが確認された。Further, as a result of cross-sectional observation with a transmission electron microscope, no new crystal defect was introduced into the Si layer,
It was confirmed that good crystallinity was maintained.
【００２５】（実施例２）表面に５０ｎｍ周期、高さ３
０ｎｍ程度の凹凸が原子間力顕微鏡により表面に観察さ
れる４インチ（１１０）単結晶シリコンを、熱処理炉に
設置し、水素ガスを導入し１０分放置した後、１１５０
℃、７６０Ｔｏｒｒで熱処理を施した。この試料を原子
間力顕微鏡により表面の平坦性を評価したところ、表面
のラフネスは水素処理前の荒れ３０ｎｍが１．６ｎｍと
良好になった。(Embodiment 2) 50 nm period and height 3 on the surface
4 inch (110) single crystal silicon, in which irregularities of about 0 nm are observed on the surface by an atomic force microscope, was placed in a heat treatment furnace, hydrogen gas was introduced, and the mixture was left for 10 minutes and then left at 1150.
A heat treatment was performed at 760 Torr. When the flatness of the surface of this sample was evaluated by an atomic force microscope, the roughness of the surface was as good as 1.6 nm when the roughness before the hydrogen treatment was 30 nm.
【００２６】また、透過型電子顕微鏡による断面観察の
結果、Ｓｉ層には新たな結晶欠陥は導入されておらず、
良好な結晶性が維持されていることが確認された。Further, as a result of cross-sectional observation by a transmission electron microscope, no new crystal defect was introduced in the Si layer,
It was confirmed that good crystallinity was maintained.
【００２７】（実施例３）表面に５０ｎｍ周期、高さ３
０ｎｍ程度の凹凸が原子間力顕微鏡により表面に￥観察
される４インチ４度オフ（１００）単結晶シリコンを、
熱処理炉に設置し、到達真空度０．０１Ｔｏｒｒに引い
た後、水素ガスを導入し、９００ｄｅｇ℃、１０Ｔｏｒ
ｒで熱処理を施した。この試料を原子間力顕微鏡により
表面の平坦性を評価したところ、表面のラフネスは水素
処理前の荒れ３０ｎｍが１．７ｎｍと良好になった。(Example 3) 50 nm period and height 3 on the surface
4 inch 4 degree off (100) single crystal silicon whose surface roughness of about 0 nm is observed by an atomic force microscope
It is installed in a heat treatment furnace, and after reaching an ultimate vacuum of 0.01 Torr, hydrogen gas is introduced, and 900 deg ° C. and 10 Torr.
Heat treatment was performed at r. When the flatness of the surface of this sample was evaluated by an atomic force microscope, the roughness of the surface was as good as 1.7 nm when the roughness was 30 nm before the hydrogen treatment.
【００２８】また、透過型電子顕微鏡による断面観察の
結果、Ｓｉ層には新たな結晶欠陥は導入されておらず、
良好な結晶性が維持されていることが確認された。As a result of observing the cross section with a transmission electron microscope, no new crystal defect was introduced into the Si layer.
It was confirmed that good crystallinity was maintained.
【００２９】（実施例４）表面に５０ｎｍ周期、高さ３
０ｎｍ程度の凹凸が原子間力顕微鏡により表面に観察さ
れる４インチ（１１１）単結晶シリコンを、熱処理炉に
設置し、到達真空度０．０１Ｔｏｒｒに引いた後、水素
ガスを導入し、１１００ｄｅｇ℃、７６０Ｔｏｒｒで熱
処理を施した。この試料を原子間力顕微鏡により表面の
平坦性を評価したところ、表面のラフネスは水素処理前
の荒れ３０ｎｍが１．７ｎｍと良好になった。(Embodiment 4) The surface has a period of 50 nm and a height of 3
4 inch (111) single crystal silicon, on the surface of which unevenness of about 0 nm is observed by an atomic force microscope, is placed in a heat treatment furnace, and after reaching an ultimate vacuum of 0.01 Torr, hydrogen gas is introduced and the temperature is 1100 deg. Heat treatment was performed at 760 Torr. When the flatness of the surface of this sample was evaluated by an atomic force microscope, the roughness of the surface was as good as 1.7 nm when the roughness was 30 nm before the hydrogen treatment.
【００３０】また、透過型電子顕微鏡による断面観察の
結果、Ｓｉ層には新たな結晶欠陥は導入されておらず、
良好な結晶性が維持されていることが確認された。Further, as a result of cross-sectional observation with a transmission electron microscope, no new crystal defect was introduced in the Si layer,
It was confirmed that good crystallinity was maintained.
【００３１】（実施例５）表面に５０ｎｍ周期、高さ３
０ｎｍ程度の凹凸が原子間力顕微鏡により表面に観察さ
れる４インチ４インチ４度オフ（１１１）単結晶シリコ
ンを、熱処理炉に設置し、到達真空度０．０１Ｔｏｒｒ
に引いた後、窒素９０％、水素ガス１０％の混合ガスを
導入し、９５０ｄｅｇ℃、５０Ｔｏｒｒで熱処理を施し
た。この試料を原子間力顕微鏡により表面の平坦性を評
価したところ、表面のラフネスは水素処理前の荒れ３０
ｎｍが１．９ｎｍと良好になった。(Embodiment 5) 50 nm period and height 3 on the surface
Unevenness of about 0 nm is observed on the surface by an atomic force microscope. 4 inches 4 inches 4 degrees off (111) single crystal silicon is installed in a heat treatment furnace, and the ultimate vacuum is 0.01 Torr.
After that, a mixed gas of nitrogen 90% and hydrogen gas 10% was introduced, and heat treatment was performed at 950 deg ° C. and 50 Torr. When the flatness of the surface of this sample was evaluated by an atomic force microscope, the surface roughness was 30 before the hydrogen treatment.
nm was as good as 1.9 nm.
【００３２】また、透過型電子顕微鏡による断面観察の
結果、Ｓｉ層には新たな結晶欠陥は導入されておらず、
良好な結晶性が維持されていることが確認された。Further, as a result of cross-sectional observation by a transmission electron microscope, no new crystal defect was introduced in the Si layer,
It was confirmed that good crystallinity was maintained.
【００３３】（実施例６）表面に５０ｎｍ周期、高さ３
０ｎｍ程度の凹凸が原子間力顕微鏡により表面に観察さ
れる４インチ（１００）単結晶シリコンを、熱処理炉に
設置し、窒素９０％、水素ガス１０％の混合ガスを導入
し１５分放置した後、７００ｄｅｇ℃、０．１Ｔｏｒｒ
で熱処理を施した。この試料を原子間力顕微鏡により表
面の平坦性を評価したところ、表面のラフネスは水素処
理前の荒れ３０ｎｍが１．７ｎｍと良好になった。(Embodiment 6) 50 nm period and height 3 on the surface
After placing 4 inch (100) single crystal silicon in which unevenness of about 0 nm is observed on the surface by an atomic force microscope in a heat treatment furnace and introducing a mixed gas of 90% nitrogen and 10% hydrogen gas and leaving it for 15 minutes. , 700 deg ° C, 0.1 Torr
It heat-treated in. When the flatness of the surface of this sample was evaluated by an atomic force microscope, the roughness of the surface was as good as 1.7 nm when the roughness was 30 nm before the hydrogen treatment.
【００３４】また、透過型電子顕微鏡による断面観察の
結果、Ｓｉ層には新たな結晶欠陥は導入されておらず、
良好な結晶性が維持されていることが確認された。Further, as a result of cross-section observation by a transmission electron microscope, no new crystal defect was introduced in the Si layer,
It was confirmed that good crystallinity was maintained.
【００３５】（実施例７）表面に１００ｕｍ角の（１０
０）単結晶シリコン領域が露出し、それ以外の部分は窒
化シリコン膜で被覆されている表面のシリコン領域では
５０ｎｍ周期、高さ３０ｎｍ程度の凹凸が原子間力顕微
鏡により観察される試料を、熱処理炉に設置し、窒素９
０％、水素ガス１０％の混合ガスを導入し炉内の雰囲気
を十分に置換した後、１１００ｄｅｇ℃、１００Ｔｏｒ
ｒで熱処理を施した。この試料の単結晶シリコン領域を
原子間力顕微鏡により表面の平坦性を評価したところ、
表面のラフネスは水素処理前の荒れ３０ｎｍが１．７ｎ
ｍと良好になった。(Embodiment 7) 100 μm square (10
0) The single crystal silicon region is exposed, and the other part is covered with the silicon nitride film. In the silicon region on the surface, heat treatment is performed on a sample in which irregularities of 50 nm cycle and a height of about 30 nm are observed by an atomic force microscope. Installed in a furnace, nitrogen 9
After introducing a mixed gas of 0% and 10% hydrogen gas to sufficiently replace the atmosphere in the furnace, 1100 deg ° C., 100 Tor
Heat treatment was performed at r. When the flatness of the surface of the single crystal silicon region of this sample was evaluated by an atomic force microscope,
The surface roughness is 1.7n when the roughness before hydrogen treatment is 30nm.
It became good with m.
【００３６】また、透過型電子顕微鏡による断面観察の
結果、Ｓｉ層には新たな結晶欠陥は導入されておらず、
良好な結晶性が維持されていることが確認された。Further, as a result of cross-sectional observation with a transmission electron microscope, no new crystal defect was introduced in the Si layer,
It was confirmed that good crystallinity was maintained.
【００３７】[0037]
【発明の効果】本発明によれば、結晶を除去しないの
で、単結晶の厚さを変えることなく、しかも、加工歪み
層あるいは、スリップライン等の結晶欠陥を導入するこ
となく、単結晶表面を市販の単結晶ウエハ並に平坦、平
滑化できる。According to the present invention, since the crystal is not removed, the surface of the single crystal can be removed without changing the thickness of the single crystal and without introducing a processing strain layer or a crystal defect such as a slip line. Can be flat and smooth like commercial single crystal wafers.
【００３８】さらに本発明は、熱処理であるので、容易
に多数枚の一括処理が可能であり、しかも、処理温度は
通常半導体プロセスに用いるのと同等な温度であり、か
つ、超高真空も必要としないので、半導体プロセスライ
ンにおいて、新たな設備投資を要さず通常用いる半導体
の熱処理炉で実現できる。また、他工程と連続した熱処
理とすることも可能である。Further, since the present invention is a heat treatment, it is possible to easily carry out batch processing of a large number of sheets, and the processing temperature is the same as that used in a normal semiconductor process, and ultra high vacuum is also required. Therefore, it can be realized in a semiconductor heat treatment furnace that is normally used in the semiconductor process line without requiring new capital investment. It is also possible to carry out heat treatment continuous with other steps.
【００３９】また本発明によれば、基体表面に凹凸が加
工され、研磨では平坦化できないような局所的な単結晶
領域も、平坦化できる。Further, according to the present invention, unevenness is processed on the surface of the substrate, and a local single crystal region which cannot be flattened by polishing can be flattened.
【００４０】以上詳述したように、本発明によれば、上
記したような問題点及び上記したような要求に答え得る
半導体基材の加工方法を提案することができる。As described in detail above, according to the present invention, it is possible to propose a method for processing a semiconductor substrate which can meet the above-mentioned problems and the above-mentioned requirements.
【図１】本発明の工程を説明するための模式図である。FIG. 1 is a schematic diagram for explaining a process of the present invention.
【図２】従来技術を説明するための模式図である。FIG. 2 is a schematic diagram for explaining a conventional technique.
【図３】単結晶薄層の表面の結晶の構造を示す図であ
る。FIG. 3 is a diagram showing a structure of crystals on a surface of a single crystal thin layer.
１１ 単結晶 １２ 表面荒れ １３ 元の形状 １４ 平坦な表面 ２１ 単結晶 ２２ 表面荒れ ２３ 元の形状 ２４ 平坦な表面 ３１ 単結晶 ３２ 表面荒れ ３３ 平坦な表面 11 Single Crystal 12 Surface Roughness 13 Original Shape 14 Flat Surface 21 Single Crystal 22 Surface Roughness 23 Original Shape 24 Flat Surface 31 Single Crystal 32 Surface Roughness 33 Flat Surface
Claims (4)
融点以下の温度において還元性雰囲気中で熱処理するこ
とを特徴とする半導体基材の加工方法。1. A method for processing a semiconductor substrate, which comprises subjecting a substrate having a single crystal on its surface to heat treatment in a reducing atmosphere at a temperature equal to or lower than the melting point of the single crystal.
である請求項１に記載の半導体基材の加工方法。2. The method for processing a semiconductor substrate according to claim 1, wherein the reducing atmosphere is an atmosphere containing hydrogen.
圧以下の圧力で実施する請求項１〜２に記載の半導体基
材の加工方法。3. The method for processing a semiconductor substrate according to claim 1, wherein the heat treatment in the reducing atmosphere is performed at a pressure of atmospheric pressure or less.
３に記載の半導体基材の加工方法。4. The single crystal is silicon.
4. The method for processing a semiconductor substrate according to item 3.
Priority Applications (10)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP01652492A JP3287596B2 (en) | 1992-01-31 | 1992-01-31 | Semiconductor substrate and processing method thereof |
| DE69334324T DE69334324D1 (en) | 1992-01-30 | 1993-01-29 | Production method for semiconductor substrate |
| EP93101413A EP0553852B1 (en) | 1992-01-30 | 1993-01-29 | Process for producing semiconductor substrate |
| DE69333152T DE69333152T2 (en) | 1992-01-30 | 1993-01-29 | Method of manufacturing a semiconductor substrate |
| DE69333619T DE69333619T2 (en) | 1992-01-30 | 1993-01-29 | Production process for semiconductor substrates |
| EP02009679A EP1251556B1 (en) | 1992-01-30 | 1993-01-29 | Process for producing semiconductor substrate |
| EP00113703A EP1043768B1 (en) | 1992-01-30 | 1993-01-29 | Process for producing semiconductor substrates |
| US08/402,975 US5869387A (en) | 1992-01-30 | 1995-03-13 | Process for producing semiconductor substrate by heating to flatten an unpolished surface |
| US09/118,872 US6121117A (en) | 1992-01-30 | 1998-07-20 | Process for producing semiconductor substrate by heat treating |
| JP2000266977A JP3507422B2 (en) | 1992-01-31 | 2000-09-04 | Manufacturing method of semiconductor substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP01652492A JP3287596B2 (en) | 1992-01-31 | 1992-01-31 | Semiconductor substrate and processing method thereof |
Related Child Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000266977A Division JP3507422B2 (en) | 1992-01-31 | 2000-09-04 | Manufacturing method of semiconductor substrate |
| JP2001394366A Division JP2002255700A (en) | 2001-12-26 | 2001-12-26 | Producing method of semiconductor substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05218053A true JPH05218053A (en) | 1993-08-27 |
| JP3287596B2 JP3287596B2 (en) | 2002-06-04 |
Family
ID=11918665
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP01652492A Expired - Lifetime JP3287596B2 (en) | 1992-01-30 | 1992-01-31 | Semiconductor substrate and processing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3287596B2 (en) |
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2000041227A1 (en) * | 1998-12-28 | 2000-07-13 | Shin-Etsu Handotai Co.,Ltd. | Method for thermally annealing silicon wafer and silicon wafer |
| US6171982B1 (en) | 1997-12-26 | 2001-01-09 | Canon Kabushiki Kaisha | Method and apparatus for heat-treating an SOI substrate and method of preparing an SOI substrate by using the same |
| JP2001035790A (en) * | 1998-07-17 | 2001-02-09 | Semiconductor Energy Lab Co Ltd | Crystalline semiconductor thin film and manufacture thereof, and semiconductor device and manufacture thereof |
| JP2001035789A (en) * | 1998-07-17 | 2001-02-09 | Semiconductor Energy Lab Co Ltd | Crystalline semiconductor thin film and manufacture thereof, and semiconductor device and manufacture thereof |
| US6407367B1 (en) | 1997-12-26 | 2002-06-18 | Canon Kabushiki Kaisha | Heat treatment apparatus, heat treatment process employing the same, and process for producing semiconductor article |
| US6413874B1 (en) | 1997-12-26 | 2002-07-02 | Canon Kabushiki Kaisha | Method and apparatus for etching a semiconductor article and method of preparing a semiconductor article by using the same |
| US6653209B1 (en) | 1999-09-30 | 2003-11-25 | Canon Kabushiki Kaisha | Method of producing silicon thin film, method of constructing SOI substrate and semiconductor device |
| JP2005005674A (en) * | 2003-05-21 | 2005-01-06 | Canon Inc | Method of manufacturing substrate and substrate treatment apparatus |
| US7256104B2 (en) | 2003-05-21 | 2007-08-14 | Canon Kabushiki Kaisha | Substrate manufacturing method and substrate processing apparatus |
| JP2012136371A (en) * | 2010-12-24 | 2012-07-19 | Toyo Tanso Kk | Feed material for epitaxial growth of single crystal silicon carbide and method for epitaxial growth of single crystal silicon carbide |
| JP2012136375A (en) * | 2010-12-24 | 2012-07-19 | Toyo Tanso Kk | Feed material for epitaxial growth of single crystal silicon carbide, and method for epitaxial growth of single crystal silicon carbide |
| JP2012136368A (en) * | 2010-12-24 | 2012-07-19 | Toyo Tanso Kk | Feed material for epitaxial growth of single crystal silicon carbide, and method for epitaxial growth of single crystal silicon carbide |
| JP2012136365A (en) * | 2010-12-24 | 2012-07-19 | Toyo Tanso Kk | Feed material for epitaxial growth of single crystal silicon carbide, and method for epitaxial growth of single crystal silicon carbide |
| US8993410B2 (en) | 2006-09-08 | 2015-03-31 | Silicon Genesis Corporation | Substrate cleaving under controlled stress conditions |
| US9362439B2 (en) | 2008-05-07 | 2016-06-07 | Silicon Genesis Corporation | Layer transfer of films utilizing controlled shear region |
-
1992
- 1992-01-31 JP JP01652492A patent/JP3287596B2/en not_active Expired - Lifetime
Cited By (25)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| AU750664B2 (en) * | 1997-12-26 | 2002-07-25 | Canon Kabushiki Kaisha | Method and apparatus for etching a semiconductor article and method of preparing a semiconductor article by using the same |
| US6171982B1 (en) | 1997-12-26 | 2001-01-09 | Canon Kabushiki Kaisha | Method and apparatus for heat-treating an SOI substrate and method of preparing an SOI substrate by using the same |
| US6506665B1 (en) | 1997-12-26 | 2003-01-14 | Canon Kabushiki Kaisha | Method and apparatus for heat-treating an SOI substrate and method of preparing an SOI substrate by using the same |
| EP1993123A2 (en) | 1997-12-26 | 2008-11-19 | Canon Kabushiki Kaisha | Method and apparatus for heat-treating an SOI substrate and method of preparing an SOI substrate by using the same |
| AU745766B2 (en) * | 1997-12-26 | 2002-03-28 | Canon Kabushiki Kaisha | Method and apparatus for heat-treating an SOI substrate and method of preparing an SOI substrate by using the same |
| US6407367B1 (en) | 1997-12-26 | 2002-06-18 | Canon Kabushiki Kaisha | Heat treatment apparatus, heat treatment process employing the same, and process for producing semiconductor article |
| US6413874B1 (en) | 1997-12-26 | 2002-07-02 | Canon Kabushiki Kaisha | Method and apparatus for etching a semiconductor article and method of preparing a semiconductor article by using the same |
| JP2001035789A (en) * | 1998-07-17 | 2001-02-09 | Semiconductor Energy Lab Co Ltd | Crystalline semiconductor thin film and manufacture thereof, and semiconductor device and manufacture thereof |
| JP2001035790A (en) * | 1998-07-17 | 2001-02-09 | Semiconductor Energy Lab Co Ltd | Crystalline semiconductor thin film and manufacture thereof, and semiconductor device and manufacture thereof |
| US6573159B1 (en) | 1998-12-28 | 2003-06-03 | Shin-Etsu Handotai Co., Ltd. | Method for thermally annealing silicon wafer and silicon wafer |
| US6809015B2 (en) | 1998-12-28 | 2004-10-26 | Shin-Etsu Handotai Co., Ltd. | Method for heat treatment of silicon wafers and silicon wafer |
| WO2000041227A1 (en) * | 1998-12-28 | 2000-07-13 | Shin-Etsu Handotai Co.,Ltd. | Method for thermally annealing silicon wafer and silicon wafer |
| US7011717B2 (en) | 1998-12-28 | 2006-03-14 | Shin-Etsu Handotai Co., Ltd. | Method for heat treatment of silicon wafers and silicon wafer |
| US6653209B1 (en) | 1999-09-30 | 2003-11-25 | Canon Kabushiki Kaisha | Method of producing silicon thin film, method of constructing SOI substrate and semiconductor device |
| JP2005005674A (en) * | 2003-05-21 | 2005-01-06 | Canon Inc | Method of manufacturing substrate and substrate treatment apparatus |
| US7256104B2 (en) | 2003-05-21 | 2007-08-14 | Canon Kabushiki Kaisha | Substrate manufacturing method and substrate processing apparatus |
| US8993410B2 (en) | 2006-09-08 | 2015-03-31 | Silicon Genesis Corporation | Substrate cleaving under controlled stress conditions |
| US9356181B2 (en) | 2006-09-08 | 2016-05-31 | Silicon Genesis Corporation | Substrate cleaving under controlled stress conditions |
| US9640711B2 (en) | 2006-09-08 | 2017-05-02 | Silicon Genesis Corporation | Substrate cleaving under controlled stress conditions |
| US9362439B2 (en) | 2008-05-07 | 2016-06-07 | Silicon Genesis Corporation | Layer transfer of films utilizing controlled shear region |
| US11444221B2 (en) | 2008-05-07 | 2022-09-13 | Silicon Genesis Corporation | Layer transfer of films utilizing controlled shear region |
| JP2012136371A (en) * | 2010-12-24 | 2012-07-19 | Toyo Tanso Kk | Feed material for epitaxial growth of single crystal silicon carbide and method for epitaxial growth of single crystal silicon carbide |
| JP2012136375A (en) * | 2010-12-24 | 2012-07-19 | Toyo Tanso Kk | Feed material for epitaxial growth of single crystal silicon carbide, and method for epitaxial growth of single crystal silicon carbide |
| JP2012136368A (en) * | 2010-12-24 | 2012-07-19 | Toyo Tanso Kk | Feed material for epitaxial growth of single crystal silicon carbide, and method for epitaxial growth of single crystal silicon carbide |
| JP2012136365A (en) * | 2010-12-24 | 2012-07-19 | Toyo Tanso Kk | Feed material for epitaxial growth of single crystal silicon carbide, and method for epitaxial growth of single crystal silicon carbide |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3287596B2 (en) | 2002-06-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP1251556B1 (en) | Process for producing semiconductor substrate | |
| KR100362311B1 (en) | Method and apparatus for etching a semiconductor article and method of preparing a semiconductor article by using the same | |
| JP3287596B2 (en) | Semiconductor substrate and processing method thereof | |
| US5266824A (en) | SOI semiconductor substrate | |
| EP2256787A1 (en) | Process for producing soi wafer | |
| US8058173B2 (en) | Methods for producing smooth wafers | |
| US8003494B2 (en) | Method for producing a bonded wafer | |
| US20050020084A1 (en) | Method of preparing a surface of a semiconductor wafer to make it epiready | |
| US20060154445A1 (en) | Method for manufacturing soi wafer | |
| KR100634659B1 (en) | A processing method of silicon epitaxial growth wafer and a processing apparatus thereof | |
| JPH09260619A (en) | Soi substrate and its manufacture | |
| Kimura et al. | Epitaxial film transfer technique for producing single crystal Si film on an insulating substrate | |
| JP3507422B2 (en) | Manufacturing method of semiconductor substrate | |
| JP2002255700A (en) | Producing method of semiconductor substrate | |
| JPH11354761A (en) | Soi substrate and its production | |
| JP4470231B2 (en) | Manufacturing method of semiconductor silicon wafer | |
| JP3430499B2 (en) | Semiconductor wafer and method of manufacturing the same | |
| JP3945130B2 (en) | Manufacturing method of bonded dielectric isolation wafer | |
| JP3473654B2 (en) | Method for manufacturing semiconductor mirror-surface wafer | |
| KR101032564B1 (en) | Method for producing bonded wafer | |
| JP3131968B2 (en) | Manufacturing method of semiconductor silicon wafer | |
| JP2002176155A (en) | Method for manufacturing laminated soi wafer | |
| CN114334792A (en) | Semiconductor silicon wafer of SOI structure and method for manufacturing the same | |
| CN116868308A (en) | Method for manufacturing support substrate for bonded wafer and support substrate for bonded wafer | |
| JPH11195774A (en) | Manufacture of semiconductor substrate |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20011106 |
|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20020226 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080315 Year of fee payment: 6 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090315 Year of fee payment: 7 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100315 Year of fee payment: 8 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100315 Year of fee payment: 8 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110315 Year of fee payment: 9 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120315 Year of fee payment: 10 |
|
| EXPY | Cancellation because of completion of term |