JPH0521767A - Manufacturing for semiconductor device - Google Patents

Abstract

PURPOSE:To form a channel region thinly up to a given thickness, by oxidizing a first silicon wafer selectively from the surface in thermal treatment so as to reduce an effective thickness of the channel region in the wafer. CONSTITUTION:A surface of a silicon wafer 1 is oxidized in thermal treatment so that a separation insulating layer 4 is formed. In a device region surrounded by the separation insulating layer 4, a mask 3 is removed from a channel region. The renewed face of the silicon wafer 1 is oxidized in thermal treatment so as to form an insulating layer 5 in the channel region. In this case, since the separation insulating layer 4 and the insulating layer 5 are different in thickness, these insulating layers have each different depth of interfacial places. Then, insulating layers 7 and 9 are put closely to each other so that the first silicon wafer 1 and a second silicon wafer 8 are bonded in thermal treatment. Moreover, the silicon wafer 1 is abraded from the rear side thereof until the separation insulating layer 4 appears on the surface. In this way, the wafer can be made thin up to a given thickness.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufactured by using a substrate having a structure in which a silicon wafer is bonded to a supporting substrate via an insulating layer, and more particularly, an insulated gate field effect transistor (IGFET). Regarding

[0002]

2. Description of the Related Art A semiconductor substrate having an SOI (silicon on insulator) structure can reduce the parasitic capacitance of the IGFET, improve radiation resistance, and prevent latch-up of a semiconductor device having a CMOS structure. Is expected as a substrate for manufacturing high-density and high-performance semiconductor integrated circuits.

At present, there is a method of manufacturing an SOI substrate by bonding two silicon wafers with an insulating layer in between.
It is being developed as one of the closest to practical use. In the SOI substrate produced by this bonding technique, one silicon wafer has a thickness of several μm or less.

In order to prevent the short channel effect in a fine IGFET, in a normal bulk IGFET, the junction in the source / drain region is made shallow and a high concentration region (retrograded well) for preventing punch through is formed.
It is generally performed to provide a portion having a depth of the junction. In the SOI substrate, since the underlying layer of the silicon layer is the insulating layer, punch through does not easily occur without providing such a high concentration region. Also, if the thickness of the silicon layer is reduced, the junction depth is determined by this thickness, and a shallow junction can be formed by itself, and there is a possibility that the channel can be shortened more easily than in a bulk IGFET.

The thickness of the silicon layer required for this purpose may be about several tens of microns only for the purpose of preventing the short channel effect. However, in order to suppress, for example, the floating body effect (eg, kink in the IV characteristic), the full-depletion type
pe) IGFET, but in this case, it is desirable that the thickness is even thinner, for example, 0.1 μm or less.

FIG. 4 shows that the surface potential is 2φ _f (φ _f
Is a graph showing the result of a simulation in which the thickness of the silicon layer of the SOI structure that is depleted at the voltage (V _th ) that becomes the Fermi potential of the silicon layer with the impurity concentration N _sub , which will be described later, is obtained. Silicon layer thickness (t _Si ; n
m), the vertical axis represents the impurity concentration (N _sub ; cm ^-3 ), and the lower side of the curve is the depleted region. For example, if the impurity concentration is 3 ×
When forming a fully depleted IGFET in a silicon layer of 10 ¹⁷ (cm ^-3 ), if the thickness of this silicon layer is set to about 60 nm or less, the channel region will be spread over the entire thickness direction at the above voltage V _th. Be depleted. Therefore, it is possible to obtain an IGFET in which the floating body effect is suppressed and which has high driving capability.

[0007]

However, if the silicon layer is made thin, the sheet resistance of the source / drain regions increases, and good transistor characteristics cannot be maintained. For example, 0.1 by ion implantation in bulk IGFET
Compared with the resistance of the source / drain region formed to a depth of μm, the IGFE of the SOI structure having a silicon layer with a thickness of 0.05 μm
The source / drain resistance of T is doubled. Also, SOI
In the structure, the insulating layer that is the base of the silicon layer is usually amorphous, so this silicon layer, which has been made amorphous by ion implantation, becomes polycrystalline in the process of recrystallization by subsequent annealing, and the sheet resistance Will be even larger.

According to the present invention, the thickness of the silicon layer in the channel region can be selectively reduced, and the thickness of the source / drain regions can form an IGFET on the SOI substrate having a sufficiently low sheet resistance. The purpose is to

[0009]

The above-mentioned object is to form a structural means on the surface of the semiconductor substrate for reducing the effective thickness of the semiconductor substrate in a channel region defined on the one surface of the semiconductor substrate. An insulating layer for flattening the surface is formed on the surface on which the semiconductor substrate is bonded to the supporting substrate through the insulating layer, and the other surface of the semiconductor substrate bonded to the supporting substrate is attached to the supporting substrate. Forming a gate insulating layer on the other surface of the semiconductor substrate that has been removed flat, and forming a gate electrode facing the channel region on the other surface of the semiconductor substrate through the gate insulating layer; Impurities are introduced into the semiconductor substrate exposed on both sides of the gate electrode to form a source.
Including various steps of forming a drain region, in particular, reducing the effective thickness of the semiconductor substrate in the channel region by an oxide film formed by selectively oxidizing the one surface of the semiconductor substrate in the channel region. This is achieved by the method for manufacturing a semiconductor device according to the present invention.

[0010]

[Operation] When two silicon wafers are bonded to each other via the insulating layer to manufacture an SOI substrate, the first silicon wafer, which will be an active layer in which a semiconductor device is formed in the future, is selectively heated from its surface, for example. Oxidation keeps the effective thickness of the wafer in the channel region small. After forming an insulating layer on the surface of at least one silicon wafer, both silicon wafers are bonded together. Then, the first silicon wafer is thinned by polishing or the like. In this way, the channel region is thinned to a desired value, and the source / drain regions are maintained at a layer thickness having a sufficiently low sheet resistance.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A process description of an embodiment of the present invention will be described below with reference to FIG.
Will be described with reference to. As shown in FIG. 1 (a), for example, an element region defined on the surface of the first silicon wafer 1 is
Cover with a mask 3 made of silicon nitride (Si ₃ N ₄ ). In the figure, reference numeral 2 is a pad oxide film of SiO _{2 having a} thickness of about 0.01 μm formed by thermally oxidizing the surface of the silicon wafer 1.

Next, the surface of the silicon wafer 1 exposed from the mask 3 is thermally oxidized to form an isolation insulating layer 4 having a thickness of about 0.1 μm. Due to this thickness, a step difference (x ₁ ) of about 0.05 μm occurs between the interface between the silicon wafer 1 and the isolation insulating layer 4 and the surface of the silicon wafer 1. The above steps are the same as in the normal LOCOS (local oxidation of silicon) method. An example of the conditions for forming the isolation insulating layer 4 having the above thickness is heating the silicon wafer 1 in a wet atmosphere at 950 ° C. for 30 minutes.

Next, as shown in FIG. 1B, the mask 3 on the channel region in the element region surrounded by the isolation insulating layer 4 is selectively removed. For this removal, a well-known lithographic technique using a photoresist is applied, and the Si ₃ N ₄ mask 3 may be etched using a hot phosphoric acid solution. The Si ₃ N ₄ mask 3 used in the LOCOS process for forming the isolation insulating layer 4 may be removed and a new Si ₃ N ₄ layer mask may be formed instead.

Next, the surface of the silicon wafer 1 exposed from the mask 3 etched as described above is thermally oxidized, and as shown in FIG. 1 (c), a thickness of about 0.
An insulating layer 5 of 07 μm is formed. An example of the conditions for forming the insulating layer 5 is heating the silicon wafer 1 in a wet atmosphere at 950 ° C. for 17 minutes. Due to the thicknesses of the isolation insulating layer 4 and the insulating layer 5, a height difference (x ₂ ) of about 0.015 μm is generated between the respective interfaces between these insulating layers and the silicon wafer 1.

Instead of forming the insulating layer 5 by selective oxidation, a groove 6 may be formed in the channel region as shown in FIG. 1 (d). The depth of the groove 6 is determined so that the same height difference (x ₂ ) as described above occurs between the interface between the isolation insulating layer 4 and the silicon wafer 1 and the bottom of the groove 6.

Then, after removing the mask 3, FIG.
As shown in (e), on the surface of the silicon wafer 1, for example, Si
An insulating layer 7 made of O ₂ and having a thickness of about 1 μm is deposited. It is convenient to carry out this deposition by using, for example, a well-known CVD (Chemical Vapor Deposition) method and selecting a condition under which the surface of the insulating layer 7 becomes flat.
If necessary, the surface of the insulating layer 7 is mirror-polished to be flat.
Even when the groove 6 is provided as shown in FIG. 1D, the insulating layer 7 is embedded in the groove 6. If necessary, the surface of the insulating layer 7 filling the groove 6 is mirror-polished to be flat.

On the other hand, as shown in FIG. 2 (f), for example, SiO ₂
A second silicon wafer 8 having substantially the same diameter is prepared on one surface of which an insulating layer 9 having a thickness of about several tens to 1 .mu.m is formed. Then, the silicon wafer 1 and the second silicon wafer 8 shown in FIG. 2 (e) are heat-treated in a state of being superposed so that the insulating layer 7 and the insulating layer 9 in each are in contact with each other. ) Bond both silicon wafers. An example of this heat treatment condition is heating at 1000 ° C for 12 minutes in a dry atmosphere. Incidentally, there is no problem even if the formation of the insulating layer 9 is omitted. Further, since the silicon wafer 8 is a supporting substrate, any material can be selected as long as it is compatible with the above-mentioned bonding with the silicon wafer 1 and the subsequent heat treatment conditions.

Next, as shown in FIG. 2H, the back surface of the silicon wafer 1 is polished until the isolation insulating layer 4 is exposed. As a result, the silicon wafer 1 becomes islands separated by the isolation insulating layer 4 for each element region. Thus, the SOI substrate having the island-shaped separated silicon layer 12 is obtained. The thickness of the island-shaped silicon wafer 1 is equal to the height difference (x ₂ ) in the channel region on the insulating layer 5, and the step difference (x ₁ ) in the source / drain regions on both sides thereof. be equivalent to.

A gate insulating layer 10 is formed on each of the island-shaped silicon layers of the SOI substrate manufactured as described above according to a normal IGFET manufacturing process, as shown in FIG. A gate electrode 11 is formed on. Then, using the gate electrode 11 as a mask, impurities are ion-implanted into the silicon layer 12 exposed on both sides of the gate electrode 11 to form source / drain regions 13 to complete the IGFET.

In the above embodiment, the thickness of the silicon layer on the SOI substrate is set to V _th as described with reference to FIG.
By controlling the thickness to fully deplete the channel region in the
You can get IGFET. The SO of the structure according to the present invention
For example, an enhancement type IGFET or a high breakdown voltage IGFET may be formed on any island-shaped silicon layer 12 of the I substrate.

[0021]

According to the present invention, the silicon layer in the channel region of the IGFET manufactured using the SOI substrate is thinned to the extent effective for preventing the short channel effect, while the silicon layer in the source / drain region is reduced. It is possible to increase the thickness so that a sufficiently low sheet resistance can be obtained, which contributes greatly to the manufacture of high-density and high-performance semiconductor integrated circuits, especially semiconductor integrated circuits composed of fully depleted IGFETs with high drive capability. .

[Brief description of drawings]

FIG. 1 is a process explanatory diagram of an embodiment of the present invention (No. 1)

FIG. 2 is a process explanatory view of the embodiment of the present invention (No. 2)

FIG. 3 is an explanatory diagram of an embodiment of the present invention.

FIG. 4 is an example of data for determining conditions of an embodiment of the present invention.

[Explanation of symbols]

1 Silicon Wafer 8 Silicon Wafer 2 Pad Oxide Film 9 Insulating Layer 3 Mask 10 Gate Insulating Layer 4 Isolation Insulating Layer 11 Gate Electrode 5 Insulating Layer 12 Silicon Layer 6 Groove 13 Source / Drain Region 7 Insulating Layer

Claims (4)

[Claims] 1. A step of forming a structural means on a surface of the semiconductor substrate for reducing an effective thickness of the semiconductor substrate in a channel region defined on the surface, and the surface on which the structural means is formed. A step of forming an insulating layer that covers the substrate and has the flat upper surface, a step of joining the semiconductor substrate to a supporting substrate through the insulating layer, and the other surface of the semiconductor substrate joined to the supporting substrate. To remove the gate electrode flatly, a step of forming a gate insulating layer on the other surface of the semiconductor substrate that has been removed flat, and a gate electrode facing the channel region through the gate insulating layer. A method of manufacturing a semiconductor device, comprising: a step of forming on a surface; and a step of introducing an impurity into the semiconductor substrate exposed on both sides of the gate electrode to form a source / drain region. 2. A means for reducing the effective thickness of the semiconductor substrate in the channel region is an oxide film formed by selectively oxidizing the one surface of the semiconductor substrate in the channel region. The method of manufacturing a semiconductor device according to claim 1. 3. A step of forming structural means on the surface for reducing the effective thickness of the semiconductor substrate in a channel region defined on one surface of the semiconductor substrate, and the surface on which the structural means is formed. Forming an insulating layer for planarizing the surface of the semiconductor substrate, joining the surface of the semiconductor substrate on which the insulating layer is formed to one surface of the supporting substrate through the second insulating layer, and joining the supporting substrate Removing the other surface of the semiconductor substrate flattened, forming a gate insulating layer on the other surface of the semiconductor substrate removed flat, and the channel region via the gate insulating layer. And a step of forming a source / drain region by introducing impurities into the semiconductor substrate exposed on both sides of the gate electrode. Semiconductor device Manufacturing method. 4. The means for reducing the effective thickness of the semiconductor substrate in the channel region is an oxide film formed by selectively oxidizing the one surface of the semiconductor substrate in the channel region. The method for manufacturing a semiconductor device according to claim 3, wherein