JP2002057309A - Method of forming soi substrate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable to easily form a gate electrode having a desired Vth when an SOI substrate is formed by using a sticking method to form elements thereon. SOLUTION: An insulating film 6 for element isolation is formed on a first semiconductor substrate 1 constituted of a porous Si layer 2. The insulating film 6 in an SOI layer forming part is eliminated, and the porous Si layer 2 is exposed to a surface. An Si single crystal layer 3 is grown on the porous Si layer 2, and an insulating film 7 for a back gate is formed on the Si single crystal layer 3 and the insulating film 6. A trench 8 for a back gate is formed on the insulating film 7, and an electrode layer 9 for a back gate is so formed that the trench 8 is filled. The first semiconductor substrate 1 is stuck on a second semiconductor substrate 4 via an insulating film 5 for sticking and subjected to grinding or the like from an unstuck surface side, and the SOI substrate 100A in which the electrode layer 9 for a back gate is buried is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing an SOI substrate useful for manufacturing a semiconductor substrate having a back gate electrode.

[0002]

2. Description of the Related Art An SOI (Si on Insulator) substrate is a substrate in which a single crystal Si semiconductor layer (SOI layer) is formed on an insulating film, and various devices are formed by using this SOI layer to form an integrated circuit. Has been made.

[0003] Conventionally, a bonding etch-back method (BESOI) has been known as one of the methods for fabricating an SOI substrate, and an improved bonding-etch-back method is a method in which a porous film is formed on a first semiconductor substrate (device wafer). A porous Si layer is formed, and a Si single crystal is grown on the porous Si layer by an epitaxial method, while a second semiconductor substrate (handle wafer)
ELTRAN to form an oxide film as a bonding insulating film on the surface of the substrate, bond the single-crystal Si or the like of the first semiconductor substrate with the oxide film of the second semiconductor substrate, and grind and polish the first semiconductor substrate. Method (Applied Physics Letters, Vol.64, No.1
6, p2108-2110, Apr 1994, JP-A-5-21338).

FIG. 3 is a manufacturing process diagram of an SOI substrate by the ELTRAN method. In this method, a Si single crystal substrate 1 is used as a device wafer A, and a porous Si layer 2 is first formed on the surface of the device wafer A by an anodic oxidation method (FIG. 3A). Next, the surface of the porous Si layer 2 is flattened, and the porous S
The holes on the surface of the i-layer 2 are sealed, and then the Si single crystal layer 3 is grown on the surface of the porous Si layer 2 by an epitaxial growth method (FIG. 3B). The thickness of the Si single crystal layer 3 is determined by the required thickness of the SOI layer, and is conventionally generally 100 nm to 500 nm.

On the other hand, as a handle wafer B, an Si substrate 4
Is prepared, and the surface thereof is formed of Si as an insulating film 5 for bonding.
An O ₂ film is formed by a thermal oxidation method or a CVD method (FIG. 3)
(C)). The thickness of the bonding insulating film 5 is an important factor that greatly affects the quality of insulation and the yield in the subsequent bonding step, and is conventionally set to 200 nm to 400 nm.

Next, the Si single crystal layer 3 of the device wafer A
Insulating film (SiO
_The device wafer A and the handle wafer B are overlapped with each other so that the _second film
A bonding state between the single crystal layer 3 and the bonding insulating film (SiO ₂ film) 5 is formed (FIG. 3D).

After bonding the device wafer A and the handle wafer B in this manner, the back surface of the device wafer A is ground and polished to expose the porous Si layer 2 (FIG. 3).
(E)) Further, the porous Si layer 2 is etched. In this etching, the etching rate of the porous Si layer 2 and the etching rate of the Si single crystal layer 3 are greatly different from each other to about 10 ⁵ .
When the Si single crystal layer 3 is exposed by the etching, the etching rate is greatly reduced, the etching is stopped (FIG. 3F), and the SOI layer (Si single crystal layer 3) is formed.

Since the etched surface of the Si single crystal layer 3 has a rough surface, the device is formed after the surface roughness is improved by touch polishing or hydrogen annealing.

When the SOI substrate is formed by the ELTRAN method, the SOI layer can be formed at a level of 50 nm.

[0010]

SUMMARY OF THE INVENTION For an SOI substrate,
Due to the demand for finer pattern rules (at the 0.1 μm level), it is required to make the SOI layer ultra-thin to a thickness of 30 to 50 nm.

However, the S formed by the ELTRAN method
When forming an element on an OI substrate, there are various problems as follows.

First, S formed by the conventional ELTRAN method
Since no embedded gate is formed on the OI substrate,
As a gate electrode, a top gate electrode is formed. In this case, Vth is the SOI layer (Si single crystal layer 3).
Depends on the thickness of the Therefore, in order to form a gate electrode having a low Vth, it is necessary to reduce the thickness of the SOI layer in accordance with the pattern rule. It is required that the thickness be 10 nm or less. However, forming a 10 nm thick SOI layer is very difficult in practice.

Further, it is necessary to reduce the thickness of the gate oxide film at the same time as reducing the thickness of the SOI layer.
In the ELTRAN method, when the gate oxide film is thinned, bubbles are likely to be generated on the bonding surface, so that the yield of substrate fabrication is significantly reduced. Therefore, there is a limit in reducing the thickness of the gate oxide film, which is a barrier in device fabrication.

The present invention solves the above-mentioned problems of the prior art by fabricating an SOI substrate by a bonding method,
It is an object of the present invention to easily form a gate electrode having a desired Vth when forming an element on a substrate.

[0015]

Means for Solving the Problems In forming a gate electrode on an SOI substrate, the present inventors have found that when a back gate electrode is formed, Vth can be controlled to a desired value without depending on the thickness of the SOI layer. Also, as a method for manufacturing an SOI substrate corresponding to formation of a back gate electrode, it has been found that it is effective to previously form a back gate electrode layer on a device wafer before bonding by an ELTRAN method.

That is, the present invention relates to a method for manufacturing an SOI substrate by a substrate bonding method, wherein a Si substrate is formed on a first semiconductor substrate comprising a porous Si layer by an epitaxial growth method.
A single crystal layer is grown, an insulating film for a back gate is formed on the Si single crystal layer, an electrode layer for the back gate is formed on the insulating film for the back gate, and the back gate electrode layer or the second
Forming a bonding insulating film on the semiconductor substrate, bonding the first semiconductor substrate and the second semiconductor substrate through the bonding insulating film, and bonding the first semiconductor substrate from the non-bonding surface side Consisting of grinding, polishing or etching,
Provided is a method for manufacturing an SOI substrate in which a back gate electrode layer is embedded.

Further, the present invention relates to a method of manufacturing an SOI substrate by a substrate bonding method, which is a method of manufacturing an SOI substrate by a substrate bonding method, wherein the SOI substrate is formed on a first semiconductor substrate comprising a porous Si layer. An insulating film for element isolation is formed,
The insulating film for element isolation at the portion where the OI layer is formed is removed to remove the porous S
exposing the i layer, growing a Si single crystal layer on the porous Si layer by an epitaxial growth method, forming an insulating film for a back gate on the Si single crystal layer and the insulating film for element isolation, Forming a back gate groove on the substrate, forming a back gate electrode layer so as to fill the back gate groove, and forming a bonding insulating film on the back gate electrode layer or the second semiconductor substrate; A first semiconductor substrate and a second semiconductor substrate are bonded to each other with an insulating film interposed therebetween, and the first semiconductor substrate is ground, polished, or etched from the non-bonded surface side, and a back gate electrode layer is embedded. Provided is a method for manufacturing a SOI substrate.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the drawings. In each of the drawings, the same reference numerals represent the same or equivalent components.

FIG. 1 is a manufacturing process diagram of one embodiment of the present invention. In this method, first, the Si single crystal substrate 1 is used as a first semiconductor substrate (device wafer A), and a porous Si layer 2 is formed on the surface thereof by an anodic oxidation method (FIG. 1).
(A)). It is preferable to perform hydrogen annealing in vacuum at about 1040 ° C. to fill the holes on the surface of the porous Si layer 2 so that epitaxial growth can be performed on the surface of the porous Si layer 2.

Next, the surface of the porous Si layer 2 is coated with SiO ₂
A device isolation insulating film 6 made of a film is formed (FIG. 1).
(B)). The layer thickness of the isolation insulating film 6 is the required thickness of the SOI layer, and is usually 30 nm to 300 nm.

The portion where the SOI layer is to be formed is removed from the element isolation insulating film 6 to expose the porous Si layer 2 (FIG. 1).
(C)) An Si single crystal layer 3 is grown on the porous Si layer 2 by an epitaxial growth method (FIG. 1 (d)).
In this case, the thickness of the Si single crystal layer 3 is
Layer thickness.

Next, a back gate insulating film 7 is formed on the Si single crystal layer 3 and the isolation insulating film 6 by CVD or the like (FIG. 1E). The thickness of the back gate insulating film 7 is determined by the sum of the required thickness of the back gate electrode BG and the thickness of the gate oxide film. For example, when the thickness of the back gate electrode BG is 300 nm and the thickness of the gate oxide film is 30 nm, the thickness of the back gate insulating film 7 is 330.

A back gate groove 8 is formed in the back gate insulating film 7 (FIG. 1F), and the back gate groove 8 is formed.
Is formed to form a back gate electrode layer 9 (FIG. 1 (g)). More specifically, as the back gate electrode layer 9, for example, poly Si is
Is deposited by CVD. In this case, poly Si
Is deposited in the next step in the back gate electrode layer 9.
Is flattened so that the back gate electrode BG can be formed while leaving the back gate electrode layer 9 in the back gate groove 8. For example, the thickness of the back gate electrode BG is set to 300 n
m, the back gate electrode layer 9 is poly
450 nm of Si is deposited.

The back gate electrode layer 9 is polished to make the upper surface of the back gate electrode layer 9 and the upper surface of the back gate insulating film 7 uniform in height, and the back gate electrode layer 9 is formed only on the back gate electrode BG. To form a back gate electrode BG (FIG. 1H). SiO ₂ is deposited as a bonding insulating film 5 on the back gate electrode layer 9 by CVD or the like, and the surface thereof is flattened by CMP or the like to finish the surface to a bonding surface roughness (FIG. 1).
(I)).

As a surface finish state of the bonding insulating film 5, for example, the surface is polished to a surface roughness Ra of 0.4 nm level to leave no particles on the bonding surface. As the CMP, for example, an average particle diameter of 40 n
The polishing pad is made of a polishing slurry of colloidal silica of m and urethane foam (such as a suede-type continuous foam). Furthermore, since it is necessary to make OH exist on the bonding surface and make it hydrophilic, a hydrophilic treatment is performed. As the hydrophilic treatment, aqueous ammonia, aqueous hydrogen peroxide, high-purity pure water (NH ₃ : H ₂ O ₂ : H ₂ O = 1: 2: 7)
RCA cleaning is performed.

On the other hand, a Si substrate 4 is prepared as a second substrate (handle wafer B) (FIG. 1 (j)), and the bonding surface thereof is formed in the same manner as the surface of the bonding insulating film 5 of the device wafer A. Perform hydrophilic treatment.

The handle wafer B and the insulating film 5 for bonding the device wafer A are overlaid (FIG. 1 (k)).
In this case, it is preferable to use the method described in JP-A-6-69476 so that the bonding method does not cause any inconvenience in the expansion and contraction of the pattern of the back gate electrode due to the difference in thermal expansion coefficient between the two wafers. .

After the superposition, for example, a heat treatment is performed in an oxygen or nitrogen atmosphere at 800 to 1100 ° C. for 30 to 120 minutes using a vertical diffusion furnace to form a strong bonded state.

Next, the bonded device wafer A
The (Si single crystal substrate 1) is ground and polished from the surface opposite to the surface on which the insulating film 5 for bonding is formed to the porous Si layer 2 (FIG. 1 (l)). In this case, since the damage due to the grinding is usually about 20 μm,
It is preferable that the single-crystal substrate 1 be left on the porous Si layer 2 by about 20 μm, and thereafter, the remaining Si single-crystal substrate 1 of about 20 μm be polished to remove damage due to grinding.

As a specific method of grinding, for example, a diamond grindstone (grindstone # 2000) is used, and is ground while being rotated at high speed (2400 to 3000 rpm). It should be noted that if the grinding speed is high, a certain degree of accuracy can be obtained on the ground surface, but even in that case, it is necessary to remove damage.

The polishing for removing the damage is performed using, for example, a polishing slurry of colloidal silica having an average particle diameter of 40 nm and a polishing pad of urethane foam. By this polishing, the porous Si layer 2 is exposed.

Next, the porous Si layer 2 is removed by selective etching to expose the SOI layer (Si single crystal layer 3) (FIG. 1 (m)). In this selective etching, since there is a high selectivity of about 10 ⁵ between the SOI layer (Si single crystal layer 3) and the porous Si layer 2, the SOI is obtained with high accuracy of about ± 5%.
It is possible to control the thickness of the layer.

After the selective etching, touch polishing or hydrogen annealing is performed to improve the surface roughness.
Touch polishing is performed using, for example, a polishing slurry made of colloidal silica having an average particle size of 40 nm and a polishing pad made of urethane foam (such as a suede-type continuous foam).

The SOI substrate 100A thus obtained is
Since the back gate electrode BG is formed, this SO
In an integrated circuit formed using the I substrate 100A, Vth can be easily controlled by controlling the back gate electrode BG. Further, device design becomes easy, and a high-performance integrated circuit can be manufactured. Further, since the bonding insulating film 5 can be formed thick, bonding can be stabilized, and the yield of products can be improved.

FIG. 2 is a manufacturing process diagram of another embodiment of the present invention. In this method, as in the embodiment shown in FIG.
A porous Si layer 2 is formed on a single crystal substrate 1 by anodization (FIG. 2A), and a Si single crystal layer 3 is grown on the surface thereof by an epitaxial growth method (FIG. 2B). For example, an SiO ₂ film is formed as a back gate insulating film 7 on the Si single crystal layer 3 without forming a trench for CV.
It is deposited by the D method (FIG. 2C).

Next, poly Si is deposited on the back gate insulating film 7 as the back gate electrode layer 9 (FIG. 2).
(D)) Further, an insulating film 5 for bonding is formed, and the surface thereof is flattened by CMP, and further subjected to a hydrophilic treatment, thereby finishing the surface to be bondable (FIG. 2).
(E)).

On the other hand, as the handle wafer B, a Si substrate 4
Is prepared (FIG. 2 (f)), and a hydrophilic treatment is performed on the bonding surface in the same manner as the surface of the bonding insulating film 5 of the device wafer A.

Next, the handle wafer B and the insulating film 5 for bonding the device wafer A are overlaid (FIG. 2).
(G)).

The bonded device wafer A (Si single crystal substrate 1) is made of porous S from the surface opposite to the surface on which the bonding insulating film 5 is formed, similarly to the process after bonding in FIG.
Grinding and polishing to the i-layer 2 exposes the porous Si layer 2 (FIG. 2 (h)), removes the porous Si layer 2 by selective etching, and exposes the SOI layer (Si single crystal layer 3). (FIG. 2I) to obtain an SOI substrate 100B.

Although the SOI substrate 100B obtained by the method shown in FIG. 2 is not separated, the SOI substrate 100B has an embedded electrode layer 9 (poly Si layer) for forming the back gate electrode BG. A back gate electrode can be easily formed on the substrate 100B, and other various devices can be formed.

The present invention is not limited to the illustrated embodiment. In manufacturing an SOI substrate by a substrate bonding method, various modes can be employed as long as a back gate electrode layer is formed in advance before bonding the first semiconductor substrate and the second semiconductor substrate.

For example, as the back gate electrode layer, po
In addition to the lySi layer, a Si compound, Al, W, or the like may be formed.

In the embodiment shown in FIGS. 1 and 2, before bonding the first semiconductor substrate and the second semiconductor substrate, the bonding insulating film 5 is bonded to the first semiconductor substrate (device wafer A). But the insulating film 5 for bonding.
May be formed on the bonding surface of the second semiconductor substrate.

In the method of manufacturing an SOI substrate according to the present invention,
Techniques such as grinding, polishing, and etching can be appropriately determined.

[0045]

According to the method of manufacturing an SOI substrate of the present invention, the back gate electrode layer is embedded in the SOI substrate. Therefore, when forming an integrated circuit using the SOI substrate obtained by the present invention, A back gate electrode capable of controlling Vth to a desired value can be easily formed without depending on the thickness of the layer.

[Brief description of the drawings]

FIG. 1 is a process explanatory diagram of one embodiment of the present invention.

FIG. 2 is a process explanatory view of another embodiment of the present invention.

FIG. 3 is a manufacturing process diagram of an SOI substrate by a conventional ELTRAN method.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... 1st semiconductor substrate (Si single crystal substrate), 2 ... Porous Si layer, 3 ... Si single crystal layer, 4 ... 2nd semiconductor substrate (Si substrate), 5 ... Bonding insulating film, 6 ... Element isolation insulating film, 7: Back gate insulating film, 8: Back gate groove, 9: Back gate electrode layer, BG
… Back gate electrode,

Claims (3)

[Claims] 1. A method for manufacturing an SOI substrate by a substrate bonding method, wherein a Si single crystal layer is grown on a first semiconductor substrate composed of a porous Si layer by an epitaxial growth method, and a back is formed on the Si single crystal layer. Forming an insulating film for the gate, forming an electrode layer for the back gate on the insulating film for the back gate, forming an insulating film for bonding on the electrode layer for the back gate or on the second semiconductor substrate, A first semiconductor substrate and a second semiconductor substrate are bonded to each other with an insulating film interposed therebetween, and the first semiconductor substrate is ground, polished, or etched from the non-bonded surface side, and a back gate electrode layer is embedded. Method for manufacturing a SOI substrate. 2. A method for manufacturing an SOI substrate by a substrate bonding method, wherein an insulating film for element isolation is formed on a first semiconductor substrate made of a porous Si layer, and an insulating film for element isolation is formed in a portion where the SOI layer is formed. Removing the film to expose the porous Si layer,
An Si single crystal layer is grown on the porous Si layer by an epitaxial growth method, a back gate insulating film is formed on the Si single crystal layer and the isolation insulating film, and a back gate groove is formed in the back gate insulating film. Then, a back gate electrode layer is formed so as to fill the back gate groove, a bonding insulating film is formed over the back gate electrode layer or the second semiconductor substrate, and the first insulating film is formed via the bonding insulating film. Of the SOI substrate in which the back gate electrode layer is embedded, by bonding the first semiconductor substrate to the second semiconductor substrate and grinding, polishing, or etching the first semiconductor substrate from the non-bonded surface side Method. 3. The method for manufacturing an SOI substrate according to claim 1, wherein the back gate electrode layer is made of a polySi layer.