JPH05211632A - Two-screen television circuit - Google Patents

Abstract

PURPOSE:To improve the vertical resolution of a slave screen in a two-screen image as the number of scanning lines of a master screen increases and to simplify the circuit constitution. CONSTITUTION:A master screen signal inputted is converted from analog to digital and after video signal processing, a 7/5-fold scanning line converting circuit 18 converts the number of scanning lines according to the clock generated by a 7/5-fold clock generating circuit 24. A slave screen signal inputted, on the other hand, is passed through a horizontal low-pass filter circuit 28 and horizontally sampled by an A/D converter 30 to about l/3. Then the signal is passed through a vertical low-pass filter circuit 32, vertically sampled by a vertical 1/2-fold sampling circuit 34 to about 1/2, and stored in a field memory 36. Then the slave screen data from the field memory 36 are read out according to the clock of a 7/5-fold clock generating circuit 24 and a composing circuit 20 composes data of the master screen data and slave screen data in the form of the digital signals as they are.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dual-screen television circuit, and more particularly to a high-quality dual-screen television circuit in which the number of vertical scanning lines of the main screen is increased by scanning line interpolation.

[0002]

2. Description of the Related Art In a conventional dual-screen television circuit 1 shown in FIG.
After D / D conversion, digital video signal processing (for example, digital Y / C separation processing) is performed, and further D /
It is A-converted and input to the synthesis circuit 2.

On the other hand, when the sub-screen signal is band-limited in the horizontal direction in advance by the horizontal low-pass filter circuit 3, for example, when a sub-screen with an area ratio of 1/9 is created with respect to the main screen, A
Sampled horizontally by 1/3 in the / D converter 4,
Further, the vertical low-pass filter circuit 5 performs band limitation in the vertical direction, and then the vertical sampling circuit 6 makes 1/1 in the vertical direction.
Sampled at 3. The vertical sampling circuit 6 performs vertical sampling as shown in FIG. That is, in each of the first field and the second field, three adjacent scanning lines in the vertical low-pass filter circuit 5 are set as a set of three scanning lines to form a tap region. And
Sampling is performed with the tap coefficient of the scanning line in the center of each tap area, that is, the weighting being 1/2 and the tap coefficient of the scanning lines above and below that being 1/4, and the position of the scanning line in the center being a sample point. The child screen data sampled by the vertical sampling circuit 6 is then input to the field memory 7.

The child screen data input to the field memory 7 is read from the field memory 7 by a read clock synchronized with the parent screen created by the read clock generation circuit 8, D / A converted, and then combined. Two
Entered in. Then, the synthesis circuit 2 synthesizes the parent screen signal and the child screen signal, and outputs a synthesized video signal. The timing of writing the child screen data to the field memory 7 and reading it from the field memory 7 is
It is controlled by the memory control circuit 9 according to the respective synchronizing signals of the parent screen and the child screen.

[0005]

However, when the number of vertical scanning lines of the parent screen is increased by scanning line interpolation in the two-screen television circuit, in the conventional child screen data processing method, the processing of the child screen data is performed by the parent screen. Since it does not support scanning line number conversion of screen data, if 1/3 of the sampling is done in the vertical direction, the child screen will appear vertically contracted by the smaller number of scanning lines of the child screen relative to the parent screen. Get lost. Further, the vertical low-pass filter circuit 5 requires a 3-tap filter circuit. Further, if the parent screen and the child screen are combined by an analog signal, a memory read clock generating circuit and a D / A converter dedicated to the child screen data are required.

Therefore, a main object of the present invention is to provide a dual-screen television circuit in which the child screen does not shrink in the vertical direction even if the image quality of the parent screen is improved. Another object of the present invention is to provide a dual screen television which does not require a read clock generating circuit dedicated to a small screen.

[0007]

DISCLOSURE OF THE INVENTION The present invention is a dual-screen television in which a second TV screen is compressed at a constant ratio into a part of the first TV screen which is the main screen and is inserted and displayed as a sub-screen. The circuit is a circuit for generating a predetermined clock, and based on the predetermined clock, the field frequency of the parent screen data is constant and the number of vertical scanning lines is n /
Scanning line conversion means for converting m (n / m> 1, n and m are positive integers) times, and the area ratio of the child screen is about 1 / x ² of the parent screen.
When displaying in the size of (x is a positive integer of 2 or more),
First sampling means for sampling the child screen data in the horizontal direction to approximately 1 / x, and in the vertical direction approximately (1 / x)
A two-screen television circuit provided with a second sampling means for sampling (n / m) ≈1 / k (k is a positive integer of 2 or more).

[0008]

The parent screen signal is converted into a digital signal by the A / D converter, and then the scanning line conversion means converts the number of vertical scanning lines into n / m times to generate parent screen data with a constant field frequency. On the other hand, when the child screen is displayed in an area ratio of about 1 / x ² with respect to the parent screen, the child screen signal is horizontally moved by about 1 / x by the first sampling means including an A / D converter. To sample. Then, by the second sampling means, about (1
/ X) · (n / m) ≅1 / k and write it to the memory. Therefore, as the image quality of the parent screen increases, the image quality of the child screen also increases, and the child screen does not shrink in the vertical direction.

To read the child screen data from the memory, the clock generating means for generating the clock of n / m times is sent to the scanning line converting means for converting the parent screen data into the scanning line number of n / m times. The clock is used. The memory read clock generation circuit dedicated to the child screen data can be omitted. Further, since the vertical sampling frequency of the child screen data is increased, the number of taps of the vertical low pass filter circuit in the preceding stage of the second sampling means is reduced.

[0010]

According to the present invention, it is possible to prevent the child screen from being shrunk in the vertical direction even when the image quality of the parent screen is improved, and the vertical resolution of the child screen is improved. Furthermore, the memory read clock generation circuit dedicated to the child screen data can be omitted, and the number of taps of the vertical low-pass filter circuit for the child screen data can be reduced, so that a high-quality dual-screen TV screen can be obtained with a simple circuit configuration. Be done.

The above-mentioned objects, other objects, features and advantages of the present invention will become more apparent from the detailed description of the following embodiments with reference to the drawings.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIG. 1, a dual screen television circuit 10 of this embodiment includes an input terminal 12 to which a master screen signal is inputted. The parent screen signal input from the input terminal 12 is converted into a digital signal by the A / D converter 14, and the video signal processing circuit 1
6 is input. In the video signal processing circuit 16, the parent screen data is processed by digital signal processing (for example, digital Y /
C separation processing). And the parent screen data is n /
It is inputted to the scanning line conversion circuit 18 m times (here, 7/5 times), and the number of vertical scanning lines is converted to 7/5 times. That is, in this case, the number of scanning lines of 525 is normally 735. After that, the parent screen data is input to the synthesis circuit 20. The clock used for processing the parent screen data is generated based on the parent screen signal input from the input terminal 12. That is, the parent screen signal is the clock generation circuit 2
2 based on the clock generated here, A
The A / D conversion operation in the / D converter 14 and the parent screen video signal processing in the video signal processing circuit 16 are performed. And
The output from the clock generation circuit 22 is also input to the 7/5 times clock generation circuit 24, where the clock is multiplied by 7/5 and sent to the 7/5 times scanning line number conversion circuit 18. Then, the 7/5 times scanning line number conversion circuit 18 performs the scanning line number conversion process based on the 7/5 times clock.

On the other hand, the child screen signal is input from the input terminal 26. Then, the band is limited in the horizontal direction in advance by the horizontal low-pass filter circuit 28, and then is sampled in the horizontal direction by the A / D converter 30 to about 1 / x (here, 1/3). Then, this sub-screen data is band-limited in the vertical direction by the vertical low-pass filter circuit 32, and then, in the vertical sampling circuit 34, approximately (1 /
3). (7/5) ≈1 / 2 sampled and stored in the field memory 36.

The vertical 1/2 sampling circuit 34 shown in FIG.
Vertical sampling is performed as shown in FIG. That is,
In each of the first field and the second field, two vertically adjacent low-pass filter circuits 32 are provided.
A set of two scanning lines is set as a tap area. Then, the tap coefficient of each of the two scanning lines in each tap area, that is, the weighting is set to ½, a scanning line indicated by a cross mark in FIG. 2 is created, and it is set as a sample point. Therefore, in this case, since the vertical sampling is ½, the vertical low pass filter circuit 32 may have two taps. That is, only one line memory is required to obtain the delay of one horizontal period, the vertical low-pass filter circuit has 3 taps, and the number of line memories is smaller than that of the conventional vertical low-pass filter circuit which requires two line memories. I'm sorry.

The writing clock of the child screen data to the field memory 36 is generated by the writing clock generating circuit 38 based on the child screen signal from the input terminal 26, and A /
The clock is also given to the D converter 30. Further, a clock from the 7/5 times clock generation circuit 24 is given as a read clock of the child screen data from the field memory 36. Then, the child screen data read from the field memory 36 is input to the combining circuit 20. Writing the memory 36 of the child screen data and the memory 36
The timing of reading from the memory control circuit 40 depends on the synchronization signal between the parent screen signal and the child screen signal.
Controlled by.

In the synthesis circuit 20, the parent screen data from the 7/5 times scan line conversion circuit 18 and the field memory 3 are sent.
The child screen data from 6 is synthesized. After that, the combined two-screen video data is converted into an analog signal by the D / A converter 42 and output from the output terminal 44 as a two-screen video signal. In this way, if the parent screen and the child screen are digitally combined together, the conventional D / A converter dedicated to the child screen becomes unnecessary.

In the above embodiment, n / m = 7 /
5, the area ratio of the sub-screen was 1 / x ² = 1/9, but the general formula (1 / x) · (n / m) ≈1 / k (x, n, m and k are positive values of 2 or more). Of course, the same effect can be obtained as long as it satisfies the integer, n / m> 1).

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is an illustrative view showing a state of vertical sampling in the embodiment shown in FIG.

FIG. 3 is a block diagram showing a conventional technique.

FIG. 4 is an illustrative view showing a state of vertical sampling in the conventional technique shown in FIG.

[Explanation of symbols]

 10 ... 2 screen television circuit 14, 30 ... A / D converter 18 ... 7/5 times scanning line number conversion circuit 20 ... combination circuit 24 ... 7/5 times clock generation circuit 32 ... vertical low pass filter circuit 34 ... vertical 1 / 2 Sampling circuit 36 ... Field memory 42 ... D / A converter

Claims (2)

[Claims] 1. A two-screen television circuit for compressing a second TV screen at a constant rate into a part of the first TV screen which is a main screen and inserting it as a sub-screen for display. A clock generating means for generating a constant frequency and a vertical scanning line number of n / m with respect to the parent screen data based on the predetermined clock.
(N / m> 1, n and m are positive integers) scanning line conversion means for converting the size of the sub-screen by an area ratio of about 1 / x ² (x is a positive integer of 2 or more) In this case, a first sampling means for sampling the sub-screen data in the horizontal direction to approximately 1 / x, and in the vertical direction approximately (1 / x) · (n / m) ≈1
Second sampling to / k (k is a positive integer greater than or equal to 2)
Dual-screen television circuit with sampling means. 2. The first sampling means and the second sampling means
2. The dual-screen television circuit according to claim 1, further comprising a memory for storing the child screen data sampled by the sampling means, and a means for giving the predetermined clock from the clock generating means as a read clock of the memory.