JPH05211498A - Clock extraction circuit - Google Patents

Abstract

PURPOSE:To obtain a stable clock output from inputted burst data. CONSTITUTION:A change point detection circuit 12 receiving burst data 11 in which a data absence part and a data presence part appear alternately periodically detects a change point included in the data and outputs 1st change point information 13. A mask circuit 14 detects a data absence part based on the 1st change point information 13, the burst data 11 and a frequency divider clock 21 and outputs 2nd change point information 15 and mask information 22 making a false data part in the 1st change point information 13. A control circuit 16 uses data for a period not masked with respect to a period of 2nd change point information 15 to be masked and generates new change point information and control information 20 so that the control information 20 given to a frequency divider circuit 19 is not discontinuous at the part having no data and outputs the control information 20. The frequency divider circuit 19 frequency-divides an output clock 18 of an oscillation circuit 17 based on the control information 20 to obtain an object frequency division clock 21.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transmission line clock extraction method, and more particularly to a transmission line clock extraction from burst data in which data is dispersed.

[0002]

2. Description of the Related Art Conventionally, a transmission line clock extraction method of this type has a method of extracting a clock by analog processing using an inductance or a capacitor, and an oscillator having an integral multiple of the transmission line clock as in this method. A method has been known in which the frequency division ratio of the frequency divider circuit for the oscillator output is controlled for each signal change point.

[0003]

However, the above-described conventional analog-type clock extraction circuit is premised on that data is continuously input, and when the data is discretely input, the output level is However, there is a problem in that the clock cannot be extracted due to a decrease in the clock.

Further, in the conventional system having an oscillator, there is a problem that the timing jitter becomes large in a portion without data because the portion without data is not protected.

The present invention has been made in view of the above-mentioned conventional circumstances, and therefore an object of the present invention is to provide a novel clock extraction circuit which can solve the above-mentioned problems inherent in the prior art. To do.

[0006]

In order to achieve the above object, a clock extraction circuit according to the present invention has a target extraction clock frequency for burst data input in which data is present for a specific period of time at a fixed cycle. A highly stable oscillator having an oscillation frequency that is an integer multiple of, a frequency divider circuit that divides the output of the oscillator to a target clock frequency, a change point detection circuit that detects a change point of the received data, and the input data. A mask circuit that counts the length of the data and outputs the information obtained by masking the change point information of the change point detection circuit in the portion having no data,
Of the change point information output from the mask circuit, the change point information of the section masked as a portion having no data by the mask circuit is used as the change point information of the section not masked, A control circuit for generating new change point information and controlling the frequency dividing circuit so that the control information does not become discontinuous in a portion without data.

[0007]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will now be described in detail with reference to the accompanying drawings with reference to the accompanying drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention.

Referring to FIG. 1, a change point detection circuit 12 which receives burst data 11 in which a portion having no data and a portion having data alternately appear, detects a change point of data included in the data, The first change point information 13 is created and output. The mask circuit 14 measures the data length in the burst data from the burst data 11, the first change point information 13 and the divided clock 21, detects a portion without data, and is included in the first change point information 13. Mask the false data and output the second change point information 15 and the mask information 22. The control circuit 16 uses the second change point information 15 output from the mask circuit 14 and the mask information 22 to use the data of the unmasked section with respect to the masked section of the second change point information 15. In order to prevent the control information 20 given to the frequency dividing circuit 19 from becoming discontinuous in a portion having no data, new change point information is generated and the control information 20 is output. The frequency dividing circuit 19 divides the output clock 18 of the oscillation circuit 17 based on the control information 20 to obtain a target frequency dividing clock 21.

[0010]

As described above, the transmission path clock extraction circuit of the present invention prohibits the use of the data of the part without data for the control of the frequency dividing circuit, and the data of the burst data is not transferred to the part without data. The feature is that it is less likely to be adversely affected by clock noise due to superposition of noise.

Further, according to the present invention, the frequency dividing circuit is used in order to generate the control information so that the control information does not become discontinuous by using the control information of the portion having the data even in the section where the change point of the data does not appear. However, the effect of reducing the timing jitter due to self-transmitting in a portion without data can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

[Explanation of symbols]

 11 ... Burst data 12 ... Change point detection circuit 13 ... First change point information 14 ... Mask circuit 15 ... Second change point information 16 ... Control circuit 17 ... Oscillation circuit 18 ... Output clock 19 ... Dividing circuit 20 ... Control Information 21 ... Output clock 22 ... Mask information

Claims (1)

[Claims] 1. A highly stable oscillator having an oscillation frequency that is an integral multiple of the frequency of a target extraction clock for burst data input that has data for a specific time at a fixed period, and an output of the oscillator. A frequency dividing circuit for dividing the frequency into a clock frequency, a changing point detecting circuit for detecting a changing point of the received data, and a changing point information of the changing point detecting circuit for counting the length of the input data and having no data. A mask circuit that outputs masked information, and change point information of a section that is masked by the mask circuit as a portion having no data among the change point information that is output from the mask circuit. A control circuit for generating new change point information and controlling the frequency dividing circuit so that the frequency division ratio control information of the frequency dividing circuit does not become discontinuous in a portion without data. A clock extraction circuit characterized by the above.