JPH05204874A - Processor - Google Patents

Abstract

PURPOSE:To enable data required for an arithmetic operation to be fetched autonomously from external memory and to improve global performance of the whole system more than ever by remarkably reducing load on a host processor. CONSTITUTION:This processor is equipped with an instruction holding means (c) which holds a specific instruction (a) including a code part which includes a code string to instruct to load prescribed instruction and data from the external memory and an address part which includes information representing the storage position of the instruction and the data in the external memory by receiving from the host processor, a decoder means (e) which decodes the specific instruction, an address extraction means (g) which extracts the address part included in the specific instruction replying to the output of the decoder means, a readout control means (k) which generates a series of memory addresses based on the extracted information of the address part and also, reads out plural instructions and data according to the address, and a buffer (h) which stores the plural instructions and data read out by the readout control means.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention is directed to processors, such as
The present invention relates to a coprocessor that is externally attached to a general-purpose processor and executes dedicated arithmetic processing. In general, including a function for executing a complicated operation at high speed in a general-purpose processor reduces performance / price in many applications, and thus is not suitable for the general-purpose processor. Therefore, there is a system in which a dedicated processor is provided outside the general-purpose processor, and this processor is dedicated to execute complicated operations. A processor that performs complicated processing in cooperation with the host processor is called a co-processor.

[0002]

2. Description of the Related Art A conventional coprocessor receives data required for operation one by one from a host processor and exclusively executes, for example, floating point operation, vector operation or other high speed operation. During this time, the host processor can execute other arbitrary processing, so that the total performance of the entire system can be improved.

[0003]

However, in such a conventional coprocessor, almost all of the data required for the operation is received from the host processor, so that the host is required each time the required data is generated. The processor side must execute processing such as data access and transfer, and the burden on the host processor is not necessarily light. Therefore, from the viewpoint of further improving the total performance of the entire system, there is still room for improvement.

Therefore, an object of the present invention is to be able to autonomously take in data required for calculation from an external memory, significantly reduce the load on the host processor, and further improve the total performance of the entire system. To do.

[0005]

In order to achieve the above object, the present invention has a code including a code string instructing to load a predetermined instruction and data from an external memory as shown in the principle diagram of FIG. Section and an instruction holding section for receiving and holding a specific instruction from the host processor including an address section including information indicating the storage location of the instruction and data in the external memory, and a decoding section for decoding the specific instruction. Address extracting means for extracting an address part included in the specific instruction in response to the output of the decoding means, a series of memory addresses based on the information of the extracted address part, and a plurality of memory addresses according to the address. Read control means for reading instructions and data from the external memory, and a plurality of instructions and data read by the read control means. And a buffer for storing the data.

[0006]

According to the present invention, when a specific instruction is transferred from the host processor to the processor (for example, coprocessor),
Instructions and data required for calculation are autonomously executed on the processor side. Therefore, the burden on the host processor side is limited, and the total performance of the entire system is further enhanced.

[0007]

Embodiments of the present invention will be described below with reference to the drawings. 2 and 3 are diagrams showing an embodiment of the processor according to the present invention. First, the configuration will be described. In FIG. 2, 10 is a processor (for example, a coprocessor).
The coprocessor 10 is connected to a CPU (host processor) 13, an external memory 14, etc. via an external address bus 11 and an external data bus 12, and internally has a buffer circuit (instruction holding means, buffer) 15 and a decoding circuit. (Decoding means, address extracting means) 16, command load control circuit 17, command length register 18, general-purpose register group 19, bus control circuit (reading control means) 20, program pointer circuit 21, and the like.

Here, the buffer circuit 15 has a predetermined capacity.
Storage space B₀To B_nThat divided into n up to -1
Each area is assigned a predetermined address signal (first address signal).
Issue A ₁Or the second address signal A₂) Individually
It can be specified, for example, the first address
Issue A₁In the area specified by
Store / read (Read / Write operation),
Alternatively, the second address signal A₂From the area specified by
Instructions, data, etc. can be read.

The decode circuit 16 decodes the prefetch register 16a for storing the instruction read from the area designated by the second address signal A ₂ , the instruction decoder 16b for decoding the contents of the prefetch register 16b, and the instruction decoder 16b. A dispatch unit 16c for outputting various signals of clock operation (for example, load start signal S _START and load address A _LOAD ) according to the result is provided.

The command load control circuit 17 is
Address register 17 for storing load address A _LOAD
a and a pointer 17b that increments the contents for each clock with the contents of the register 17a as an initial value, and the contents of the pointer 17b is output as a _first address signal A ₁ to the buffer circuit 15 via the internal address bus 22. ..

The command length register 18 sets information (command length length C _LEN ) indicating the number of instructions and data to be loaded from the external memory 14, and the general-purpose register group 19 includes R ₀ to R. _{It has m} registers up to _m −1, and sets information (base address A _BASE ) indicating a storage position of an instruction and data to be loaded in the external memory 14 in one register.

The bus control circuit 20 includes a general-purpose register group 19
Base address set in one register of A _BASE
20a for registering and storing
Pointer 20b of incrementing the contents for each clock as an initial value the contents of the address translation 20c for outputting the content of the pointer 20b as an address of the external memory 14 (third address signal A _3), in accordance with the third address A ₃ A slave access logic 20d for reading instructions and data from the external memory 14 and outputting them to the buffer circuit 15 via the internal data bus 23 is provided.

The program pointer circuit 21 has a predetermined space.
Tart address A_STARTStart Regis in which is set
Data 21a and the contents of register 21a as the initial value.
Pointer 21b that increments the contents for each
Including the contents of the pointer 21b to the second address signal A₂
Is output to the buffer circuit 15. FIG. 3 shows the CPU 13
Of a specific instruction transferred from the processor to the coprocessor 10
FIG. In this figure, the CM of the code part
D loads predetermined instructions and data from the external memory 14.
It is a code string instructing to do so. Operand 1 R _i
Is the base address A_BASEGeneral-purpose register for storing
One register number of group 19 and operand
B of 2_jIs the load address A_LOADIt is itself.

With such a structure, the "command load instruction system" can be realized. That is, by the slave access, a specific instruction from the CPU 13 to the coprocessor 10 is transmitted to the buffer circuit 15 according to the fourth address signal A ₄ (A ₄ ← A _START ) designated by the external address bus.
_Is stored in one area (B _START ). Around this time, the command length length C _LEN is written in the command length register 18, and the base address A _BASE is written in one register (R _j ) of the general-purpose register group 19. These C _LEN and A _BASE are set by the CPU 13, for example.

In the operand 1 of the specific instruction, the number (R _j ) of one register in the general-purpose register group 19 is set. In addition, the buffer circuit 1 is used for the operand 2.
An address (load address A _LOAD ) indicating one area (B _i ) 5 is set. As described above, when the storage of the specific instruction in the buffer (B _START ) and the setting of the command length length C _LEN and the base address A _BASE are completed, the value of the second address signal A ₂ (the initial value A
Area of buffer circuit 15 (B _{STAR T} ) according to _START )
Is designated, and the instruction in that area is read and decoded by the decoding circuit 16. Since the instruction in the area (B _START ) is the specific instruction previously transferred from the CPU 13, the decode circuit 16 outputs the load start signal S _START and the load address A _{LO AD} (the content of the operand 2 of the specific instruction). It Then, this A _LOAD is set in the register 17a of the command load control circuit 17, and
The base address A _BASE stored in one register (R _j ) of the general-purpose register group 19 is set in the register 20 a of the bus control circuit 20.

Therefore, while the value of the first address signal A ₁ is sequentially incremented from A _LOAD , the value of the third address signal A ₃ is sequentially incremented from A _BASE to obtain the first value. In each area of the buffer circuit 15 designated by the address signal A ₁ , the third address signal A
Each instruction and data from the external memory 14 read in ₃ is sequentially written.

As described above, in this embodiment, by transferring a specific instruction from the CPU 13 and executing the specific instruction, the data required for the operation can be directly fetched from the external memory 14 to the coprocessor 10. Yes (realization of command load method). For this reason, processing such as data access and data transfer on the CPU 13 side becomes unnecessary, and the CPU
It is possible to significantly reduce the burden of 13. as a result,
The CPU 13 can be dedicated to other processing, and the performance of the entire system can be further improved.

Moreover, slave LSI (coprocessor)
In the buffer that does not have write back like the command group of, the control buffer can be simplified by adopting the above command buffer method rather than having complicated control such as cache. Since it can be assigned and placed under the control of the OS, there is an advantage that the program of the slave LSI can be easily managed by the OS.

In the above embodiment, the buffer for storing the specific instruction can be arbitrarily designated, but it may be stored in a predetermined buffer. Further, in the embodiment, the register number for storing the base address A _BASE is designated by the operand of the specific instruction, which is a so-called indirect addressing system. However, the base address A _BASE may be directly designated by the operand of the specific instruction. I do not care.

[0020]

According to the present invention, the data required for the operation can be autonomously taken in from the external memory, the load on the host processor can be significantly reduced, and the performance of the entire system can be further improved. ..

[Brief description of drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is a configuration diagram of an embodiment.

FIG. 3 is a format diagram of a specific instruction according to an embodiment.

[Explanation of symbols]

13: CPU (host processor) 14: External memory 15: Buffer circuit (instruction holding means, buffer) 16: Decoding circuit (decoding means, address extracting means) 20: Bus control circuit (reading control means)

Claims (1)

[Claims] 1. A specific part including a code part including a code string for instructing to load a predetermined instruction and data from an external memory, and an address part including information indicating a storage position of the instruction and data in the external memory. An instruction holding means for receiving and holding an instruction from a host processor, a decoding means for decoding the specific instruction, an address extraction means for extracting an address portion included in the specific instruction in response to an output of the decoding means, A series of memory addresses are generated on the basis of the information of the extracted address part, and a read control means for reading a plurality of instructions and data from an external memory in accordance with the addresses, and a plurality of instructions read by the read control means and A processor comprising: a buffer for storing data.