JPH05204641A - Microprocessor - Google Patents

Abstract

PURPOSE:To provide a microprocessor for efficiently processing signals indicating wait or branch. CONSTITUTION:The microprocessor 1 is provided with an instruction storing means 11 for storing plural instructions and data applied from the external, an instruction decoding means 12 for decoding the instructions and data stored in the means 11, an address specifying means 13 for specifying a prescribed execution address based upon a decoded instruction by the means 12 or an operation starting instruction, and an updating selecting means 14 for selecting whether the value of the execution address specified by the means 13 is to be update based upon the instruction decoded by the means 12 or not.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor, and more specifically, to a command buffer for holding a series of instruction sequences in a chip, and one instruction from the command buffer.
The present invention relates to a microprocessor that reads out one by one and sequentially executes it. When operating a microprocessor, usually, instructions and necessary data are stored in an external memory such as a DRAM (Dynamic Random Access Memory), and the instructions and data are fetched into the microprocessor to process the instructions.

However, since a DRAM generally used as an external memory has a long access time, the DRAM is
If the instructions are input one by one from the instruction sequence stored in, the execution time becomes long and the processing efficiency deteriorates. Therefore, as one means for avoiding deterioration of processing efficiency, the instruction string stored in the external memory is transferred in advance to a register in the processor that can be accessed at high speed, and the instruction is fetched from the register during operation. Method is used.

Incidentally, a register holding this instruction may be called a "command buffer".

[0004]

2. Description of the Related Art A conventional microprocessor of this type is shown in FIG. The microprocessor 1 includes an external input / output control circuit 2, a start flag / start address storage unit 3, an internal input / output control circuit 4, latches 5 and 6, a program pointer 7, a command buffer 8, an adder 9, an OR gate OR, and a decoder. DE
C, selectors SEL1 and SEL2.

In the figure, IB is an internal data bus, S,
S'is a select signal, A is an address signal, CB-AD
R and CB-W / R are signals for controlling data input / output between the command buffer 8 and the internal data bus.
In the above configuration, as shown in FIGS. 6 and 7, first, after the start, each data of the start flag and the start address is fetched from the external data bus, and the external input / output control circuit
Is transferred to the internal data bus IB via (steps 1 and 2).

Next, the start flag and the start address are latched in the start flag / start address storage unit 3 (step 3), and when the select signal S is asserted, the start address is fetched into the program pointer 7. If the select signal S is negated (steps 4 and 5), the program pointer 7 is incremented (steps 4 and 6).

Then, the contents of the command buffer 8 are read using the contents of the program pointer 7 as an address (step 7), and the read instruction is latched (step 8) and decoded by the decoder DEC (step). 9). If the decoded instruction in the process of step 9 is a branch instruction (step 10), the select signal S'is asserted and the branch destination address is transferred to the internal data bus IB (step 11). ).

If the decoded instruction is an instruction that requires a plurality of clocks to execute the instruction (step 1
2) The select signal S'is asserted and the address of the next instruction is transferred to the internal data bus IB (step 13). On the other hand, if the decoded instruction is a normal instruction, the select signal S'is negated. (Step 14).

[0009]

However, in such a conventional microprocessor, when a decoded instruction requires a plurality of clocks for execution or a branch, it is necessary to re-initialize the microprocessor. Since it is necessary to control the program pointer by operating the address or the select signal S, the control becomes complicated and the efficiency of processing the signal indicating the wait or branch is deteriorated. There was a point.

[Object] Therefore, an object of the present invention is to provide a microprocessor which efficiently processes a signal indicating a weight or a branch.

[0011]

In order to achieve the above-mentioned object, a microprocessor according to the present invention decodes an instruction accumulating means for accumulating a plurality of instructions and data from the outside, and an instruction and data accumulated in the instruction accumulating means. Instruction decoding means, address designating means for designating a predetermined execution address based on the instruction decoded by the instruction decoding means or an operation start instruction, and the value of the execution address designated by the address designating means for decoding the instruction. Update selecting means for selecting whether to update based on the instruction decoded by the means.

[0012]

According to the present invention, a predetermined execution address is designated for the instruction storage means based on the instruction decoded by the instruction decoding means or the operation start instruction, and the value of this execution address is updated by the update selection means as needed. Will be updated. That is,
Even if the decoded instruction requires, for example, a plurality of clocks for execution or a branch, the processing for the signal indicating the wait or the branch is efficiently performed.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing an embodiment of a microprocessor according to the present invention, and is a block diagram showing the configuration of the main part thereof. First, the configuration will be described.

In FIG. 1, the same numbers as the numbers given to the conventional example shown in FIG. 5 indicate the same parts. The microprocessor 1 of this embodiment is roughly classified into the instruction storage means 1
1, an instruction decoding means 12, an address designating means 13 and an update selecting means 14, an instruction accumulating means 11 comprises an internal input / output control circuit 4 and a command buffer 8, and an instruction decoding means 12 comprises a latch 6 and a decoder DEC. The address designating means 13 comprises an external input / output control circuit 2, a start flag / start address storing section 3, a program pointer 7, selectors SEL1 and SEL2, and the update selecting means 14 comprises an adder 9 and a selector SEL3. There is.

Although not shown, an instruction control circuit is provided outside FIG. 1, and an interface signal with the microprocessor 1 in this embodiment is mainly to the instruction control circuit. The internal data bus IB is a 32-bit bus for transferring data inside the processor, and the CB-ADR and CB-W / R control input / output of data between the command buffer 8 and the internal data bus IB. CB-ADR has 8 bits because the command buffer 8 has 256 words in this embodiment.

The start flag / start address storage unit 3 stores a 1-bit register (start flag) for indicating the start of execution of an instruction stored in the command buffer, and a command storing the first instruction to be executed. This is an 8-bit register (start address) that indicates the buffer address. When "1" is written to the star and flag, it indicates that the execution of the instruction will be started. It is automatically cleared in the next cycle to "0". Return to.

The internal input / output control circuit 4 is, for example, a tri-state control circuit or the like for input / output to / from the internal data bus IB. The program pointer 7 is an 8-bit register indicating a command buffer address in which an instruction to be executed next is stored. The command buffer 8 is
This is a register for storing a series of instruction sequences or data, and in the present embodiment, SRA having a length of 32 bits × 256 words.
It is composed of M.

The selector SEL1 is a circuit for selecting the data to be inputted to the program pointer 7, and selects the start address when the start flag is asserted, and selects the branch address when the branch signal is asserted. The output from the adder 9 is selected in other cases, and the start flag and the branch signal are not asserted at the same time.

The update selection means 14 consisting of the selector SEL2 and the adder 9 has the program pointer 7 during the execution of the instruction.
It is a circuit for controlling whether to update the contents of the. The selector SEL3 is a circuit for selecting an address to be given to the command buffer 2. The selector SEL3 selects CB-ADR when in the input / output state with the internal data bus IB, and the value of the program pointer 7 when the instruction storage address is required. Is to be selected.

The start write signal is a write signal to both registers of the start flag / start address storage unit 3. When this signal is asserted, the data of the internal data bus IB is written to both registers. is there. The branch signal and the branch address are signals for branching by a branch instruction. When branching, the branch signal is asserted, and at the same time, the address to be branched is transferred to the branch address. Incidentally, the branch destination address is 8 bits.

Next, the operation will be described. 2 to 4 are diagrams for explaining an operation example of this embodiment, FIGS. 2 and 3 are flowcharts thereof, and FIG. 4 is a timing chart. First, after start-up, each data of the start flag and the start address is fetched from the external data bus and transferred to the internal data bus IB via the external input / output control circuit 2 (steps 21 and 22).

Next, the start flag and the start address are latched in the start flag / start address storage unit 3 (step 23), and when the select signal S is asserted, the start address is fetched into the program pointer 7. If the select signal S is negated and the select signal S'is asserted (steps 24, 25), the contents of the dedicated bus are fetched into the program pointer 7 (steps 24, 26, 27),
If the select signals S and S'are both negated,
The output from the adder 9 is fetched into the program pointer 7 (steps 24, 26, 28).

Then, the contents of the command buffer 8 are read using the contents of the program pointer 7 as an address (step 29), and the read instruction is latched (step 30) and decoded by the decoder DEC (step). 31). Next, as a result of decoding in the processing of step 31, if the decoded instruction is a branch instruction (step 32), select signal S '
Is asserted, the branch destination address is output to the dedicated bus (step 33), and if the decoded instruction is an instruction that requires multiple clocks to execute the instruction (step 34), the select signal S ″ is asserted. (Step 35) At this time, the selector SEL3 outputs “0”.
Is selected, no increment operation occurs.

If the decoded instruction is a normal instruction, the select signals S'and S "are negated (step 36). Thus, in the present embodiment, the update selection which is the updating means of the program pointer 7 is performed. The means 14 makes it possible to efficiently generate a command buffer address for various instructions.

Therefore, the decoded instruction is, for example,
Even when a plurality of clocks are required for execution or a branch is required, it is possible to efficiently process the signal indicating the wait or the branch.

[0026]

According to the present invention, a predetermined execution address is designated to the instruction storage means based on the instruction decoded by the instruction decoding means or the operation start instruction, and the value of this execution address is required by the update selection means. Therefore, even if the decoded instruction requires a plurality of clocks for execution or a branch is required, the decoded instruction can be updated accordingly. The processing can be performed efficiently.

[Brief description of drawings]

FIG. 1 is a block diagram showing a main configuration of the present embodiment.

FIG. 2 is a flowchart for explaining an operation example of the present embodiment.

FIG. 3 is a flowchart for explaining an operation example of the present embodiment.

FIG. 4 is a timing chart for explaining an operation example of the present embodiment.

FIG. 5 is a block diagram showing a configuration of a main part of a conventional example.

FIG. 6 is a flowchart for explaining an operation example of a conventional example.

FIG. 7 is a timing chart for explaining an operation example of a conventional example.

[Explanation of symbols]

 1 Microprocessor 2 External Input / Output Control Circuit 3 Start Flag / Start Address Storage Section 4 Internal Input / Output Control Circuit 5, 6 Latch 7 Program Pointer 8 Command Buffer 9 Adder 11 Instruction Storage Means 12 Instruction Decoding Means 13 Address Designation Means 14 Update Selector OR OR gate DEC decoder SEL1, SEL2 selector

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Tatsuya Nagasawa 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Fujitsu Limited

Claims (1)

[Claims] 1. An instruction storage means for storing a plurality of instructions and data from the outside, an instruction decoding means for decoding the instructions and data stored in the instruction storage means, and an instruction decoded by the instruction decoding means or Addressing means for designating a predetermined execution address based on the operation start instruction, and whether to update the value of the execution address designated by the address designating means based on the instruction decoded by the instruction decoding means A microprocessor comprising: update selecting means;