JPH0520192A - Cache memory store system - Google Patents

Abstract

PURPOSE:To perform the store reflection processing at a high speed to a cache memory in preparation for the following read processing without increasing the cache busy probability. CONSTITUTION:A comparator group 108 compares the address included in a store address buffer 102 with a read request address after a cache coincidence processing request address received from a normal cache queue 105 referred to a flash address array 113 in preference to the store address received from the buffer 102. Then the coincidence is secured between both addresses, the array 113 is referred to with the preference given to the store address received from the buffer 102.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pipeline type information processing apparatus comprising a plurality of arithmetic processing units having a store-through type cache memory, and more particularly to a cache memory store method.

[0002]

2. Description of the Related Art Conventionally, when an arithmetic processing unit and an input / output processing unit rewrite data in a main memory, an information processing device of this type is rewritten (stored) in the cache memory of another arithmetic processing device. A cache matching process is performed in order to reflect in the. That is, the system control unit sends the address of the rewritten data in the main memory to all the arithmetic processing units, and the arithmetic processing unit which receives the address,
The flash address array, which is a copy of the address array, is searched for whether or not the block containing the data indicated by the address exists in the cache memory, and if there is, the block is erased. However, in case the cache match processing request from the system control unit cannot be processed immediately, the request address is stored in the flash queue (hereinafter referred to as F
It is stored in a buffer called LQ). on the other hand,
When the self-processing unit stores, in order to reflect the store by the self-processing unit in the self-cache memory as well, it is searched whether the block of data indicated by the store address exists in the self-cache memory. There is a need. Although it is conceivable to use an address array for the search, the address array has a high access frequency, and the search for reading data is prioritized, so that the search process by the store is difficult to select. Therefore, the method of searching with the flash address array, which is less frequently accessed than the address array, is adopted. The advantage of searching with this flash address array is that one block of the cache memory is physically divided into a plurality of sub-blocks of a certain size, and reading and writing can be performed in units of this sub-block. If data read and store are for different blocks, these two processes can be performed in reverse. In the pipeline type information processing device, the timing at which the store address and the store data are obtained are different, so it is necessary to absorb this time difference. Therefore, the store address and the store data are stored respectively in the store address buffer (hereinafter referred to as SAB) and the store data buffer (hereinafter referred to as SDB). If the read address for the cache and the address in the SAB match, the above store reflection processing by the self-processing unit is continued until the data for the matched address is flushed to the cache. After that, the latest data is taken out by accessing the cache memory again with the same read address.

There is a possibility that the cache coincidence processing request and the store reflection processing request by the self arithmetic unit may conflict with each other. However, if the cache coincidence processing request is made to wait, the cache coincidence processing request address becomes full in the FLQ (flash busy). That is, there is a high probability that the subsequent cache coincidence processing request will not be accepted and the system control device will stop the processing of all arithmetic processing devices and input / output processing devices connected thereto. Therefore, conventionally, the index of the flash address array by the cache coincidence processing address from FLQ is prioritized.

[0004]

In the conventional cache memory store method described above, since the cache match process from the FLQ uses the flash address array in preference to the store reflection process request, the index of the flash address array by the store is set. Delay, store to cache memory is delayed.

An object of the present invention is to prepare for a subsequent read process without increasing the probability of cache busy.
The purpose is to perform store reflection processing to the cache memory at high speed.

[0006]

A cache memory storing method according to a first aspect of the present invention is an information processing apparatus comprising a plurality of arithmetic processing units, a main storage unit, an input / output processing unit, and a system control unit. A cache memory, which is a copy of a part of the data in the main memory, is stored in the main memory when a data is written to the main memory in the self-processing unit, and a write address and a write address. A store data buffer for storing the address, an address array for storing an address on the main memory of the data stored in the cache memory which is referred to for writing to the cache memory and reading of the data from the cache memory, and the address array Separately from the other processing units, the cache match for writing to the main memory A flash address array, which is a copy of the address array referred to for processing, and a flash queue, which is a buffer for storing the cache match processing request address from the system controller, are stored in the store address buffer. The flash address array is referenced to check if the stored store address is already registered in the cache memory, and the cache match processing request address from the normal cache queue has priority over the store address from the store address buffer. See
A means for comparing the address in the store address buffer with the read request address for the cache is provided, and when the comparing means indicates a match, the priority is inverted to give priority to the store address from the store address buffer to set the flash address array. refer.

According to a second aspect of the present invention, in the cache memory store method, means for comparing the reference of the flash address array with a predetermined number of entries of the cache coincidence processing address in the flash queue is provided, and the comparing means is provided. Is greater than a predetermined number, the cache match processing address from the flash queue is prioritized over the store address from the store address buffer to refer to the flash address, and the comparison means sets a predetermined value. When it is detected that it is smaller than the number, the store address from the store address buffer is prioritized over the cache match processing request address from the cache queue to refer to the flash address.

The cache memory store system of the third invention is provided with a means for detecting the number of requests in the store address buffer and the store data buffer by referring to the flash address array, and in the comparison means of the second invention. The predetermined number of is changed according to the result of the detecting means.

[0009]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a store system of a cache memory of the first invention. Here, the arithmetic processing unit has a cache memory that performs data replacement with the main memory in block units, and when this arithmetic processing unit performs a store, at the same time, the store by the own arithmetic processing unit is reflected in the cache memory. It is assumed that the store-through method is adopted.

First, the store operation in the cache will be described. The cache memory comprises a data array (DA) 122 in which data is registered and an address array (AA) 114 in which addresses of those data are registered.
The reflection processing of the store by the self-processing unit means that when the self-processing unit rewrites the data in the main memory, it is reflected in the cache memory, which is a copy of a part of the data in the main memory. It is something to do. Therefore, it is necessary to search whether or not the block indicated by the store address exists in the cache, but in the present embodiment, the flash address array (F
AA) 113 is searched. The store address stored in the address register (FAAR) 111 is F
The FAA 113 is indexed below the AAR 111, the read data is compared with the rest of the FAAR 111 by the comparator 115, and if hit, the comparator 115 outputs 1 and 1 is stored in the bit signal register (FHR) 118. . Further, as for store data, the store address is stored in the FAAR and at the same time the store data register (SDBR) 11
Stored in 0. The selection circuit 120 includes a request from the address register (AAR) 112 and FAAR 111.
If the requests from FAAR 111 conflict, select the request from FAAR 111; otherwise, AAR 112
Select a request from. At the same time when 1 is set in the FHR 118, the store request of the FAAR 111 is sent to the address register (DAR) 121 in the SDBR 110.
Is stored in the write data register (DWR) 117.
Stored in. DA122 has a write enable signal of 1
In this case, the RAM becomes data writable. In this case,
When FHR 118 becomes 1, the store data of DWR 117 will be written at the address indicated by DAR 122. The store address and the store data are sent from the arithmetic unit in the own arithmetic processing unit, and are stored in the store address buffer (SAB) 102 and the store data buffer (SDB) 101 for storing them. SAB
102 and SDB 101 have the same number of words as the store address and store data from the arithmetic unit and the write pointer (S
(IR) 103 is stored in the address. The comparator group 108 receives the read address from the instruction processing unit and S
This is a circuit that compares each store address in the AB 102 and outputs 1 to the signal line 150 if a match with even one address is shown. The store address and store data in the SAB 102 and SDB 101 are usually read pointers (SO
The store address and store data indicated by R) 104 are swept out, but when the signal line 150 is 1, the SAB 102
The address showing the match with the read address is swept out from the SDB 101, and the reflection processing of the store is continued to the cache until the data corresponding to the address is swept out from the SDB 101. Flash cue (F
LQ) 105 is a buffer for storing the flash address from the system controller, and is a write pointer (FI).
R) is stored in the address indicated by 106 and the flash address indicated by the read pointer (FOR) 107 is read out. The priority circuit 109 uses the signal line 15
When 0 is 0, store request from SAB 102 and FLQ1
When the flash request from the 05 conflicts with the FAA 113, the flash request from the FLQ 105 is given priority and the flash address is set to the address register (FAAR).
111, and when the signal line 150 is 1, SAB1
This is a circuit for giving priority to the store address from 02 and sending it to the FAAR 111.

Next, the read operation will be described. The read address from the instruction processing unit is stored in the AAR 112, and the contents of the AA 114 shown in the lower part of the AAR 112 and the upper part of the AAR 112 are compared with each other in order to search whether the data indicated by the address exists in the DA 122. Comparing with, if there is a hit, the comparator 116 is 1
Is output to the hit signal register (AHR) 119.
Is set. At the same time, the address of the AAR 112 passes through the selection circuit 120 and is stored in the DAR 121, and the content of the DA 122 indicated by it is output. The read data register (CRR) 123 has a strobe signal of 1
Is a register for storing the output data of DA122, and when AHR119 becomes 1, DA is stored in CRR123.
The data indicated by R122 is stored. However, when the comparator group 108 indicates a match with any of the addresses in the SAB 102, the signal line 150 becomes 1 as described above, and the matched address, that is, the read address and the data corresponding thereto are SAB 102 and SBB, respectively.
The store reflection process by the self-processing unit is continued until it is swept from 101. That is, the store address is stored in the FAAR 111 through the priority circuit 109, and at the same time the same address is stored in the AAR 112, but the store address on the FAAR 111 side is stored in the DAR 121 by the selection circuit 120, and at the same time, the output of the comparator 115 is stored in the FHR 118. Store data from SDBR110 to D
The data is stored in the WR 117 and the data is written in the DA 122. After that, the DA 122 is read at the same address as the previous store address in the AAR 112.

FIG. 2 is a block diagram showing an embodiment of a cache memory store system of the second invention. Here, 201 to 207 and 209 to 223 in FIG.
Corresponding to 107, 109 to 123, it is assumed that the FLQ 205 has a total capacity of 16 words and the flash coincidence processing request address in the FLQ 205 becomes 8 words and the flash busy occurs. The feature of the second invention is that the cache match processing request address normally indexes the FAA 213 in preference to the store address, but it is also necessary to reflect the latest data in the SDB 201 to the cache early in preparation for the subsequent read. FLQ because there is
The cache match processing request address in 205 is F
If it is 4 words or less, which is 1/4 or less of the capacity of the LQ 205, the FAA 213 is indexed with priority on the store address. The comparison circuit 208 is FLQ20.
FIR206 the number of entries of the flash address in 5
And the FOR 207, and if the number is 4 or less, 1 is output to the signal line 250. Therefore FLQ205
When the cache match processing request address in the cache is few and there is little possibility of flash busy, FAA21
3 can be used with priority over the index for the store reflection processing of the self-processing unit, and the store data can be swept out to the cache memory quickly.

FIG. 3 is a block diagram showing an embodiment of the cache memory store system of the third invention. Here, 301 to 323 of FIG. 3 correspond to 201 to 223 of FIG.

Also in the embodiment of the second invention, the cache matching process and the store reflection process by the self-calculation process still conflict with each other, but in order to reflect the store data in the cache earlier, the priority order of the cache matching process is higher. If an attempt is made to make the number of cache matching processing requests in the FLQ 305, which is a reference for change, larger than 4 words, then the probability of flash busy increases. In order to improve it, in the embodiment of the third invention, SAB302, SDB
When the store address and the store data in 301 become full, the priority change criterion is changed from 4 words to 8 words. The detection circuit 330 includes SIR 303 and SOR3.
04, the SAB 302, the store address in the SDB 310, and the number of entries of store data are calculated.
If the capacity of the SDB 301 is full, 1 is output to the signal line 351. When the signal line 351 is 0, the comparison circuit 308 outputs FLQ.
When the number of entries of the cache match processing request address in is less than or equal to 4 words of 1/4 of the capacity, 1 is output to the signal line 350, and when the signal line 351 is 1, the number of cache match processing address entries in the FLQ Is a circuit that outputs 1 to the signal line 351 when is less than 8 words, which is half the capacity. Therefore, when SAB102 and SDB101 are likely to be busy and FLQ is less likely to be busy,
The store address has priority and the FAA 313 is indexed.

In the above-described three embodiments, when the cache matching process is performed by the FLQ for the same address as the store address immediately after the store reflection process, the data in the cache memory is invalidated, but the read process is performed. Even if there is a miss, the necessary data is obtained from the main memory and is simultaneously registered in the cache memory, so the data in the cache memory is always guaranteed. Also, if you get a mishit and get data from the main memory,
Although the read processing will take a lot of time, the frequency of miss hits due to the above is much lower than the frequency of flash busy and the frequency of store reflection processing. The impact is considered to be small.

[0016]

As described above, according to the first aspect of the invention, when the latest data is desired to be read, and according to the second aspect of the invention, when the FLQ is unlikely to be busy, the third aspect of the invention is used. According to the invention, when the FLQ is less likely to be busy and the SAB and the SDB are more likely to be busy, the store address flush address is indexed with priority over the cache matching process from the FLQ.
Can store data in cache at high speed.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a store system of a cache memory of the first invention.

FIG. 2 is a block diagram showing one embodiment of a cache memory store system of the second invention.

FIG. 3 is a block diagram showing an embodiment of a store system of a cache memory of a third invention.

[Explanation of symbols]

101, 201, 301 Store data buffer (S
DB) 102, 202, 302 strike address buffer (S
AB) 103, 203, 303 Write pointer (SIR) 104, 204, 304 Read pointer (SOR) 105, 205, 305 Flash queue (FL)
Q) 106, 206, 306 Write pointer (FIR) 107, 207, 307 Read pointer (FOR) 108 Comparator group 208, 308 Comparison circuit 109, 209, 309 Priority circuit 110, 210, 310 Store data register (SDBR) ) 111, 211, 311 address register (FAA
R) 112, 212, 312 Address Register (AA
R) 113, 213, 313 Flash address array (FAA) 114, 214, 314 Address array (AA) 115, 215, 315, 116, 216, 316
Comparator 117, 217, 317 Write data register (DW
R) 118, 218, 318 Hit signal register (F
HR) 119, 219, 319 Hit signal register (A
HR) 120, 220, 320 Selection circuit 121, 221, 321 Address register (DA
R) 122, 222, 322 Data array (DA) 123, 223, 323 Read data register (CRR) 330 Detection circuit 150, 250, 350, 351 Signal line

Claims (3)

[Claims] 1. An information processing device comprising a plurality of arithmetic processing devices, a main memory device, an input / output processing device and a system control device, wherein a cache memory is a copy of a part of the data of the main memory in the arithmetic processing device. In the case where data is written to the main memory by the self-processing device, a store address buffer for storing a write address, a store data buffer for storing write data, writing to a cache memory and a cache memory An address array for storing the address on the main memory of the data stored in the cache memory that is referred to for reading the data from, and for writing to the main memory from another arithmetic processing device separately from the address array, A copy of the address array referenced to perform cache match processing. A rush address array and a flash queue that is a buffer for storing the cache match processing request address from the system controller, and checks whether the store address stored in the store address buffer is already registered in the cache memory. The flash address array is referenced for checking, and the cache match processing request address from the normal cache queue has priority over the store address from the store address buffer, and the flash address array is referenced, and the read request for the address in the store address buffer and the cache is requested. A means for comparing addresses is provided, and when the comparing means indicates a match, the priority is inverted and the store address from the store address buffer is prioritized to refer to the flash address array. Store method of Yasshumemori. 2. A reference to the flash address array is provided with means for comparing the number of entries of the cache coincidence processing address in the flash queue with a predetermined number, and it is detected that the comparison means is larger than the predetermined number. In this case, the cache match processing address from the flash queue is prioritized over the store address from the store address buffer to refer to the flash address, and the store is performed if the comparing unit detects that it is smaller than a predetermined number. 2. The cache memory store system according to claim 1, wherein the store address from the address buffer refers to the flash address in preference to the cache match processing request address from the cache queue. 3. A means for detecting the number of requests in the store address buffer and the store data buffer is provided by referring to the flash address array, and a predetermined number in the comparing means according to claim 2 is set in the detecting means. 3. The cache memory store method according to claim 2, wherein the cache memory store method is changed according to a result.