JPH0693230B2 - Buffer storage way control circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] (1) In a data processing device equipped with a buffer storage (BS) storing a copy of a part of a storage device, when a match signal is obtained by a search of a tag part By providing a buffer storage (BS) address register for storing a value obtained by encoding the search result in a part thereof, way data is provided in the address direction of the buffer storage (BS).

(2) In the buffer storage way control circuit of the item (1), the address of the way whose LRU is the latest is predicted and read at the same time as the search of the tag part, and is read as a part of the buffer storage (BS) address register. By providing a means for setting, the data of the latest way indicated by the LRU is read in advance, and when the address of the latest way indicated by the LRU and the search result of the tag unit match, the preceding read way It is designed to use data.

[Industrial application field]

The present invention relates to a buffer storage way control circuit in a data processing device having a buffer storage storing a copy of a part of a storage device.

With the recent remarkable progress in semiconductor technology, main memory devices (MS) have been increasing in capacity, and control devices such as central processing units (CPU) have become faster and the speed difference between them has increased. There is a tendency to open, and as a measure to absorb this speed difference, for example, a relatively large capacity, medium speed global buffer storage (GBS) and a high speed but small capacity local buffer storage (LBS) are provided. In addition, a so-called two-level cache memory system is often adopted.

On the other hand, in medium-sized computer systems, there is a strong demand for downsizing of the entire system due to its economic efficiency and high speed, and the global buffer storage (GBS) when the above two-tier cache memory system is adopted. In such cases, downsizing is an essential condition.

However, since the tag portion of the cache memory has a relatively small capacity, the data portion has a large capacity as described above, and therefore the data portion must be downsized.

[Problems to be solved by conventional technology and invention]

FIG. 3 is a diagram for explaining a conventional buffer storage way control method, (a) shows an example of the entire configuration, and (b).
Shows the operation time chart, and FIG. 4 is a diagram showing the position of the buffer storage way control circuit of the present invention.

As described above, in the high-speed data processing device, the fourth
As shown in the figure, a buffer storage way control circuit is provided between the main storage device (MS) and the central processing unit (CPU). In the buffer storage way control circuit, the main storage device (MS) A so-called cache memory method that aims to improve the apparent access time to the main storage device (MS) by storing a copy of the data in a high-speed, small-capacity memory, that is, a buffer storage (hereinafter referred to as BS). Adopting is a common technique.

The buffer storage way control circuit is shown in FIG.
Also, the configuration shown in FIG.

Normally, the BS is composed of a plurality of BS ways (0 to n) 1 as shown in the figure in order to improve its effect, and simultaneously reads out the plurality of BS ways (0 to n) 1. I do.

At the same time, the tag section (0 to n) 2 corresponding to each way is searched to determine which way the copy of the access target block of the main storage device (MS) is in the comparator (0 to n). n)
In step 21, the coincidence signal of the comparator (0 to n) 21 is used to select and read the data from each of the BS ways (0 to n) 1 by the selection circuit 11. {Refer to the time chart of FIG. 4 (b)} The selection processing as to whether the access request from the central processing unit (CPU) is in the buffer storage (BS) 1 or the main storage (MS) is shown in FIG. As shown in, the value of the main memory (MS) address (upper) registered in the tag unit 2 and the main memory (MS) address (higher) requested by the central processing unit (CPU) ) And the comparison. In the comparison process, if there is a way that matches (hits), the corresponding data in the buffer storage (BS) 1 is selected by the selection circuit 11 and sent to the central processing unit (CPU) shown in FIG. . In the above comparison process, if no matching way is found, the data in the main memory (MS) shown in FIG. 4 is selected and the central processing unit (CPU) is selected.
The buffer storage (BS) 1
Is the data of the main memory (MS), and the tag unit 2 is
The main memory (MS) access (upper level) is registered. At this time, the way to store in which way is the well-known "LRU".
Of control. In this way, "comparison and coincidence signal of tag part"
Is either one way or no way.

Thus, in the conventional method, as shown in FIG. 4, the main memory (MS) address (lower) is used as it is.
It is used as a buffer storage (BS) address, and it is necessary to read the buffer storage (BS) data of all the ways at the same time regardless of the comparison processing in the tag unit 2.

Therefore, the number of ways (0 to n) 1 of the BS,
There is a problem in that separate memory elements are required, the number of parts is increased, and this becomes a factor that hinders the downsizing of a medium-sized computer system including the BS.

In view of the above conventional drawbacks, the present invention provides a buffer storage (BS) having a relatively large capacity in a computer system including a buffer storage (BS) including a plurality of ways.
By storing the data of each way in the address direction,
By reducing the number of memory elements constituting the buffer storage (BS) to reduce the size of the buffer storage (BS), and storing the way data in the address direction of the buffer storage (BS). The purpose is to improve the increase in access time that occurs.

[Means for solving problems]

FIG. 1 is a diagram showing a configuration example of a buffer storage way control system of the present invention.

In the present invention, a buffer storage (1) storing a part of the main storage (MS) in a plurality of ways between the main storage (MS) and the central processing unit (CPU), In a data processing device comprising a tag unit (2) for selecting a plurality of ways of the buffer storage (1), a plurality of ways of the buffer storage (1) are arranged in an address direction of the buffer storage (1). The main storage device (M) registered in the tag unit (2) is provided.
The address (upper) of S) and the access address (upper) from the central processing unit (CPU) are compared, and the encoded signal () of the comparison result when the coincidence signal is obtained is stored in the buffer storage (1). ), The way provided in the above address direction is selected and used as a part of the read address.

A register 25 that predicts and holds the address of the hit way from the value of LRU28 in the system that uses the encoded signal of the comparison result of the tag unit 2 as a part of the address for reading the way of the buffer storage (BS) 1. A means 26 for comparing the search result in the tag unit 2 with the hit way prediction result is provided, and when the comparison circuit matches, the predicted way address is stored in the buffer storage (BS) 1 way. A way provided in the address direction of the buffer storage (BS) 1 is selected and used as part of the read address, and when the comparison result does not match, the comparison result of the tag unit 2 The encode signal is configured to be used as a part of the address for reading the way of the buffer storage (BS) 1.

[Operation] That is, according to the present invention, (1) In a data processing device including a buffer storage (BS) storing a copy of a part of a storage device, when a match signal is obtained by a search of a tag part By providing a buffer storage (BS) address register that stores the value obtained by encoding the search result in part thereof, way data is provided in the address direction of the buffer storage.

(2) In the buffer storage way control circuit of the item (1), the address of the way whose LRU is the latest is predicted and read at the same time as the search of the tag part, and is read as a part of the buffer storage (BS) address register. By providing a means for setting, the data of the latest way indicated by the LRU is read in advance, and when the address of the latest way indicated by the LRU and the search result of the tag unit match, the preceding read way It is designed to use data.

Therefore, unlike the conventional case, a memory element for each way data is not required, the buffer storage (BS) can be downsized, and the latest way with a high hit rate can be predicted and the buffer storage can be performed in advance. By reading out (BS), there is an effect that it is possible to improve the decrease in access time caused by the above-mentioned miniaturization.

〔Example〕

 Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a diagram showing a configuration example of the buffer storage way control circuit of the present invention, (a) shows an example of the basic configuration, and (b) shows how to select a way of the buffer storage. FIG. 2 shows an example of predicting the latest way from the LRU logic and reading it in advance. FIG. 2 is a time chart of the way selecting operation according to the present invention.
(B) corresponds to (a) and (b) of FIG.
Encoder 22, BS address register 23, read way prediction circuit 24, prediction way register 25, and comparator in the figure
26, select gate circuit 27 is a necessary means for implementing the present invention. The same reference numerals indicate the same objects throughout the drawings.

The buffer storage way control circuit of the present invention will be described below with reference to FIGS. 1 and 2.

First, the basic operation of the buffer storage way control method of the present invention will be described with reference to FIGS.

In FIG. 1 (a), from a processing device not shown,
The tag portion (0 to n) 2 corresponding to each way (0 to n) of BS1 is searched by the value of the lower bit (tag address) of the main memory address set in the MS address register 20,
The comparator (0 to n) 21 compares with the upper bit (comparison address) of the MS address register 20. {Refer to cycle 1 and 2 of the time chart in Fig. 2 (a)} Here, if there is no address corresponding to the tag part (0 to n) 2, it is shown as a hit miss. Move in the data block containing the corresponding data from the main memory (MS) that is not present and register it in the empty block of BS1. At this time, when there is no free block in the BS1, the known LRU mechanism 28, 29 searches the oldest way and registers the move-in data in the way.

If the contents of the tag part (0 to n) 2 (tag address)
, If it matches the comparison address that is the upper bit of the MS address register 20, that is, if there is a block containing the data accessed to BS1 (hit),
The coincidence output signal of the comparator (0 to n) 21 is encoded by the encoder 22, and the encoded signal is included in the BS address register 23 of the present invention together with the lower bits of the MS address register 20 (for example, the least significant, Alternatively, it is set to the highest level). {Refer to the cycle 23 in FIG. 2 (a)} The encode signal indicates the number of the way hit by i.
Then, in the 4-way buffer storage (BS), for example, the following table is obtained.

Next, in cycles 3 and 4 shown in FIG.
Read operation is performed on the
It functions so that the read data is passed to the processing device.

As a result, the number of cycles for accessing BS1 is increased by one as compared with the conventional method shown in the time chart of FIG. 3 (b), but like the global buffer storage (GBS) described above, BS When the tag search time is shorter than the read time, this increase in the number of cycles causes almost no problem.

Further, in the cycles 3 and 4 shown in FIG. 2A, if the value of the MS address register 20 is held, only the lower bit of the MS address register 20 and the portion holding the output of the encoder 22 are BS1 can be read and the number of bits in the BS address register 23 can be reduced.

Next, referring to FIGS. 1 and 2 (b), in the buffer storage control circuit of the present invention, in selecting the way of the buffer storage (BS), the latest way is predicted by the LRU logic, An example of reading in advance will be described.

First, in FIG. 1B, the tag unit (0 to 0) of each way is set according to the value of the lower bit (tag address) set in the MS address register 20 from a processor (not shown).
n) 2 is searched, and the above MS is searched by the comparator (0 to n) 21.
A comparison is made with the upper bits (comparison address) of the address register 20. {Refer to Cycles 1 and 2 in FIG. 2 (b)} In the cycle 1, at the same time, the known LRU 28 is read, the read way prediction circuit 24 checks the latest way address, and the selection gate circuit 27 To a part of the BS address register 23 (most significant, least significant, etc., least significant in this example).

Further, the output of the read way prediction circuit 24 is stored in the prediction way register 25, and in cycle 2, the comparator 26 compares the result with the search result of the tag section 2.

When a coincidence signal is obtained by this comparison operation, the read result of the buffer storage (BS) obtained in cycle 3 is sent to the processing device. {Refer to FIG. 2 (b) (a)} However, if there is a mismatch in the comparison operation, in cycle 2, the match output of the comparators (0 to n) 21 is encoded by the encoder 22. The value is reset to a part (for example, the lowest level) of the BS address register 23 via the selection gate circuit 27, and the buffer storage (BS) 1 is read again.

Therefore, the read data of the buffer storage (BS) 2 in this case is obtained in the cycle 4. {See FIG. 2 (b) (b)} As described above, the address of the hit way of the buffer storage (BS) 1 is predicted and read (the latest way) by the prediction by the known LRU logic. With this, the probability of hitting the prediction can be increased considering the locality of the address distribution.

As described above, in the present invention, in the processing device including the buffer storage (BS) including a plurality of ways, the encoding result of the search result of the tag unit is used as a part of the address register of the buffer storage (BS). The buffer storage (BS) is configured to be read out, and the way data is provided in the direction of the address.
The latest way is predicted using the LRU machine, and the way address is used as part of the address register to read the buffer storage (BS) in advance, and the search result of the tag section and the prediction result are obtained. If and match, the way data that has been read in advance is used.

〔The invention's effect〕

As described in detail above, the buffer storage way control circuit according to the present invention includes: (1) In a data processing device including a buffer storage (BS) storing a copy of a part of a storage device, searching for a tag portion By providing a buffer storage (BS) address register that stores the encoded value of the search result when a match signal is obtained in part, it is possible to have way data in the address direction of the buffer storage. is there.

(2) In the buffer storage way control circuit of the item (1), the address of the way whose LRU is the latest is predicted and read at the same time as the search of the tag part, and is read as a part of the buffer storage (BS) address register. By providing a means for setting, the latest way indicated by the LRU is read out in advance, and when the latest way data indicated by the LRU and the search result of the tag part match, the address of the preceding read way is set, The data of is used.

Therefore, unlike the conventional case, a memory element for each way is not required, the buffer storage (BS) can be downsized, and the latest way with a high hit rate can be predicted to detect the buffer storage (BS) in advance. By reading (1), there is an effect that it is possible to improve the decrease in access time caused by the above-mentioned miniaturization.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration example of a buffer storage way control circuit of the present invention. FIG. 2 is a time chart of a way selection operation according to the present invention. FIG. 3 is a diagram for explaining a conventional buffer storage way control system. FIG. 4 is a diagram showing the positioning of the buffer storage way control circuit. In the drawing, 1 is a buffer storage (BS), 11 is a selection circuit, 2 is a tag unit (0 to n), 21 is a comparator (0 to n), 22 is an encoder, 23 is a BS address register, and 24 is a read way. Prediction circuit, 25 is a prediction way register, 26 is a comparator, 28 is an LRU, 27 is a selection gate circuit, 29 is a replace way control circuit, is an encode signal, is a predicted way address, or the latest way or hit way, Are shown respectively.

Claims (2)

[Claims] 1. A main memory (MS) and a central processing unit (CP)
U), a buffer storage (1) storing a part of the main storage device (MS) in a plurality of ways, and a tag unit (a) for selecting a plurality of ways of the buffer storage (1). And a plurality of ways of the buffer storage (1) are provided in the address direction of the buffer storage (1), and the main unit registered in the tag unit (2) is provided. Storage device (M
The address (upper) of S) and the access address (upper) from the central processing unit (CPU) are compared, and the encoded signal () of the comparison result when the coincidence signal is obtained is stored in the buffer storage (1). 3.) A buffer storage way control circuit, characterized in that a way provided in the above address direction is selected and used as part of an address to be read. 2. A value of LRU (28) in a buffer storage way control circuit which uses an encoded signal () as a comparison result of said tag section (2) as a part of an address for reading a way of said buffer storage (1). A prediction way register (25) for predicting () and holding the address of the hit way from is held, and a comparison circuit (26) for comparing the search result in the tag section (2) with the hit way prediction result, If the comparison results in the comparison circuit (26) match, the way address indicated by the prediction way register (25) is used as a part of the address for reading the way of the buffer storage (1), The way provided in the address direction of the storage (1) is selected and read, and when the comparison result in the comparison circuit (26) does not match, the tag section (2 ) Is used as a part of an address for reading the way of the buffer storage (1) to select and read the way provided in the address direction of the buffer storage (1). 3. The buffer storage way control circuit according to claim 1, wherein the buffer storage way control circuit is controlled according to claim 1.