JPH0520120A - Parallel processing computer system - Google Patents

Abstract

PURPOSE:To attain the reduction in cost, to reduce a packaging area, and to easily set the breaking condition by providing single piece of debugger against plural CPUs. CONSTITUTION:As for a debugger, single piece of debugger 5 in common to CPUs 1a-1d is provided, and the debugger 5 is provided with a CPUID resister 52 for holding address information set to a data resister 51, and an identification code for executing a program corresponding to the data, in addition to the data register 51. Also, to a comparator 53, a function for executing the exclusive NOR operation of the contents of the data register 51 and an address signal AD from a shared bus 3, and the contents of data DT at every corresponding bit, and also, executing an exclusive NOR operation of the contents of the CPUID register 52 and a busy signal BS at every corresponding bit is added, and these operation results are integrated. The integrated one is outputted as a breaking signal to all CPUs 1a-1d.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel processing computer system, and more particularly, to a parallel processing and a debugging operation having a structure in which a plurality of microprocessors and one memory are connected by a common bus. A parallel processing computer system capable of processing.

[0002]

2. Description of the Related Art A block diagram of a conventional parallel processing computer system using four microprocessors (CPUs) is shown in FIG. 7, and a specific example of its debugger is shown in FIG.

In FIG. 7, 1a, 1b, 1c and 1d output an address signal AD and input / output data DT and the like,
Moreover, the CPU 4, which is a microprocessor having a function of requesting the use of the shared bus 3 with respect to the bus arbiter 4, accepting the arbitration result (busy signals BSa to BSd), and accepting the break request, CPUs 4a to 1d.
A bus arbiter 2 that outputs an arbitration result (BSa to BSd) of the use of the shared bus 3 by a signal (bus request signals RQa to RQd) that requests the bus use of the shared bus 3 output by the CPUs 1a to 1d. Signal A
D, shared memory unit for holding input / output data DT, 3
Are CPUs 1a to 1d, shared memory unit 4, debugger 15a
The shared buses 5A to 5D connected to the CPUs 15a to 15d receive address signals AD, data DT, etc. input and output by the CPUs 1a to 1d, and output break requests (break signals BKa to BKd) to the CPUs 1a to 1d. Is.

In FIG. 8, reference numeral 51 is a data register for preliminarily holding information such as an address and data to be broken in the program, 53 is a comparison between signals output from the shared bus 3 and the data register 51, and a comparison result is output. Is a comparator for performing an exclusive NOR operation for each corresponding bit of the signal from the data register 51 and the address signal AD and the data DT from the shared bus 3, and integrating the result by an AND operation. There is.

The operation of this example will be described below. Data register 5 in debuggers 5A, 5B, 5C and 5D connected to four CPUs 1a, 1b, 1c and 1d, respectively.
In FIG. 1, address signals, data, etc. of the break condition are held in advance (break condition is set by software), and the signal 12 output from the data register 51 and the address signal AD, data DT from the shared bus 3 are stored. The contents are compared with each other, and the comparison result is compared with break signals BKa, BKb,
CPUs 1a, 1b, 1c corresponding to BKc and BKd,
Output to 1d.

[0006]

The conventional parallel processing computer system described above requires the same number of debuggers 5A to 5D as the number of CPUs 1a to 1d, so that it is expensive if the number of CPUs is large. There are drawbacks such as taking up a mounting place. Further, there is a drawback that it is complicated because it is necessary to set break conditions in the data registers 51 of all the debuggers when it is not known which CPU executes the program which is the target of the break.

An object of the present invention is to provide a parallel processing computer system in which the number of debuggers is reduced and break conditions for data registers can be easily set.

[0008]

A parallel processing computer system of the present invention includes a shared bus for transmitting an address signal and data, and a data from the shared bus for an address designated by an address signal from the shared bus. A shared memory unit that stores and reads the data stored at this address to the shared bus, and requests the bus to be used for the shared bus by a bus request signal and obtains the bus use right by a corresponding busy signal. A plurality of CPUs that output the address signals to the shared bus, input / output corresponding data, and stop program execution by corresponding break signals, and the respective CPs.
A bus arbiter that arbitrates a request from the U to use the shared bus and outputs a busy signal to the predetermined CPU, address information that stops program execution, data register that holds data, and stop execution of the program Of the CPU that receives the identification code of each CPU, and the contents of the data register and the contents of the address signal and data from the shared bus match, and the contents of the CPUID register and the CPU that receives the busy signal. And a depagger having a comparator which outputs at least the corresponding break signal when the identification code matches.

[0009]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention, and FIG. 2 is a circuit diagram showing a concrete example of a debugger of this embodiment.

This embodiment differs from the conventional parallel processing computer system shown in FIGS. 7 and 8 in that the debugger is a single debugger 5 common to the CPUs 1a to 1d. In addition to the data register 51, a CPUID register 52 that holds the address information set in the data register 51 and the identification code of the CPU that executes the program corresponding to the data is provided, and the comparator shares the contents of the data register 51. An exclusive NOR operation is performed for each corresponding bit of the address signal AD from the bus 3 and the contents of the data DT.
The point is that a function of performing an exclusive NOR operation for each bit corresponding to the busy signals BSa to BSd of the contents of the ID register 52 is added, and the results of these exclusive operations are all integrated by an AND operation. CP
The identification code of the CPU held in the UID register 52 is the busy signal BSa-corresponding to each CPU 1a-1d.
BSd is configured as a corresponding bit.

FIGS. 3A and 3B are a flow chart and a memory map of the shared memory unit 2 when a program for parallel processing is allocated to each of the CPUs 1a to 1d and the shared memory unit 2 is loaded.

The parallel processing loader loads the object program obtained by compiling the source program into 4
CPUs 1a to 1d are allocated to the respective CPUs 1a to 1d.
Program stored in the shared memory unit 2 is stored in the shared memory unit 2.
To memorize inside.

The CPUID table includes the CPUs 1a to 1d.
It consists of the address of the area of the program to be processed by and the identification code of the CPU corresponding to this address. The address (hexadecimal number) is the start address of the program area of each of the CPUs 1a to 1d and the final address of the program area of the CPU 1d + 1 (the area of the program processed by the CPU 1d,
It is necessary for distinction outside the program area)
Corresponding identification codes (binary numbers) are "0001", "0"
"010", "0100", "1000", "0000"
Consists of. A memory map of the shared memory unit 2 of the CPUID table is shown in FIG. Further, FIG. 4B shows the data format of the register part.

The data register 51 holds 32 bits of address information ADI of break conditions and 32 bits of data DTI, and also holds control information CNT. CP
The UID register 52 holds the identification code ID of the CPU, as described above. Break condition address information A
DI, data DTI and the like can be arbitrarily set (setting is performed by software), but the identification code ID is set by the parallel processing loader referring to the CPUID table.

The operation of this embodiment will be described below. In a program in which the source program is compiled and allocated to each of the CPUs 1a to 1d by the parallel processing loader, and the CPUID table is created, the data register 51 in the debugger 5 stores the address information A of the break condition.
Holds DI, data DTI, etc. For example, when the address of the break condition is set to "5F", the parallel processing loader immediately refers to the CPUID table and "5F" is larger than "3A" (the head address of the CPU 1b) and "67".
Since it is smaller than (the head address of the CPU 1c), it is understood that the address "5F" is processed by the CPU 1b.
The identification code "0010" corresponding to PU1b is C
It is held in the PUID register 52.

On the other hand, the debugger 5 uses the address signal AD, the data DT and the busy B from the shared bus when executing the program.
Sa to BSd are input, the common bus 3 and the data register 51 are compared, the busy signals BSa to BSd are compared with the contents of the CPUID register 52, and the integrated result is used as a break signal BK for all the CPUs 1a to 1d. Output. That is, in this embodiment, all the CPUs 1a to 1d stop the execution of the program when the break condition is satisfied.

With such a configuration, only one debugger is required, so that the cost can be reduced, the mounting place can be reduced, and the break condition can be easily set.

FIG. 5 is a block diagram showing a second embodiment of the present invention, and FIG. 6 is a circuit diagram showing a concrete example of the debugger of this embodiment.

In this embodiment, the debugger 5a is connected to each CPU
Break signals BK corresponding to 1a to 1d, respectively
a to BKd are output. this is,
The break signal (identical to the break signal BK of the first embodiment) BK output from the comparator 53 by the switching circuit 54.
Is realized by switching according to the contents of the CPUID register 52. In this embodiment, there is an advantage that only the CPU executing the program including the break condition can break.

[0021]

As described above, according to the present invention, the number of debuggers can be reduced by controlling the breaks of a plurality of CPUs with one debugger, so that the cost can be reduced and the mounting area can be reduced. Can be reduced, and the break condition can be easily set.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a specific example of the debugger of the embodiment shown in FIG.

3A and 3B are a flow chart and a memory map of the shared memory unit for explaining a method of allocating a program for parallel processing of the embodiment shown in FIG. 1 to each CPU and a method of loading the shared memory unit.

FIG. 4 is a memory map of the CPUID table and a data register of the embodiment shown in FIG. 1, and a data format diagram of the CPUID register.

FIG. 5 is a block diagram showing a second embodiment of the present invention.

FIG. 6 is a circuit diagram showing a specific example of the debugger of the embodiment shown in FIG.

FIG. 7 is a block diagram showing an example of a conventional parallel processing computer system.

8 is a circuit diagram showing a specific example of a debugger of the parallel processing computer system shown in FIG.

[Explanation of symbols]

1a-1d CPU 2 Shared memory section 3 shared buses 4 bus arbiter 5, 5a, 5A-5D Debugger 51 Data register 52 CPU ID register 53,53a comparator 54 Switching circuit

Claims (2)

[Claims] 1. A shared bus for transmitting an address signal and data, storing data from the shared bus for an address specified by an address signal from the shared bus, and sharing the data stored at this address. A shared memory unit for reading out to the bus, and a bus request signal for requesting the use of the shared bus, and a corresponding busy signal to obtain the bus use right to output the address signal to the shared bus. A plurality of CPUs that input / output data and stop program execution by corresponding break signals, and arbitrate bus use requests for the shared bus from these CPUs, and output a busy signal to a predetermined CPU. Bus arbiter, address information to stop program execution, data to hold data Register, a CPU that holds the identification code of each CPU that stops the execution of the program
It corresponds at least when the contents of the ID register and the data register match the contents of the address signal and the data from the shared bus, and the contents of the CPUID register and the identification code of the CPU that receives the busy signal match. A parallel processing computer system, comprising: a depacker having a comparator that outputs the break signal. 2. The parallel processing computer system according to claim 1, wherein the identification code of each CPU is constituted by a busy signal corresponding to each CPU as a corresponding bit.