JPH0519981A - Data write normal end judging method for optical disk device - Google Patents

Abstract

PURPOSE:To judge beforehand a recording fault to a medium so that an effective countermeasure can be taken. CONSTITUTION:In a step 102, recording processing to a data cache device at the time of data write from a host computer is executed in order to compensate a weak point that the throughput of an optical disk device is low and so on. The data-cached data is recorded later in the optical disk device. In the step 104, the recording fault at the time of this later recording to the optical disk device is judged beforehand by executing temporary access processing to the optical disk device. Namely, when the steps 110, 112 result in decision that the data cache device is normal, and besides, the optical disk device is normal, normal end information is transferred to the host computer in the step 116. Thus, the effective countermeasure against the recording fault can be taken.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optical disk device such as a hard disk emulator which is one of auxiliary storage devices for computers.

[0002]

2. Description of the Related Art An optical disk device is capable of exchanging disks, has no risk of crash due to a non-contact recording system, and has a long disk length, as compared with a hard disk device which is most often used as an auxiliary storage device for computers. It has many advantages such as long life expectancy and large storage capacity.

Therefore, in recent years, it has been attracting attention as an auxiliary storage device replacing the hard disk drive.

[0004]

However, the following problems still exist at the present time for the optical disc device to be widely used as an auxiliary storage device for computers.

The first problem is that the hard disk device has already been widely used as an auxiliary storage device for a computer, and therefore new hardware and software must be prepared in order to connect the optical disk device to the computer. That is.

The second problem is that the throughput of the optical disk device is lower than that of the hard disk device.
The first cause of low throughput of the optical disk device is
The second is that the seek time is long, the second is that the data error rate before error correction is bad, and the verify processing after writing is essential, and the third is that the probability of replacement processing is high due to the same error rate problem. To be

A third problem is that if the optical disk device is of the magneto-optical type, it cannot be overwritten and that a magnetization direction reversal time is required between the erase cycle and the write cycle.

For this reason, the optical disk device has a problem that the processing speed is remarkably reduced as compared with the hard disk device, particularly in the case of a write operation.

That is, the optical disk device has many advantages, but on the other hand, it also has many problems.

One of the inventors of the present application has proposed a technique relating to a hard disk emulator capable of solving such conventional problems in Japanese Patent Application No. 2-230807, which has not been published at the time of filing the present invention. There is.

In this Japanese Patent Application No. 2-230807, a hard disk device or a non-volatile memory used as a cache memory is provided between the host computer and the optical disk device and the hard disk device or the non-volatile memory together with an optical disk device which is a main storage device. Is effective as an auxiliary storage device of a computer, which is composed of an emulation unit that operates in response to a request for data recording or data reproduction from a host computer while using the hard disk device or non-volatile memory as a cache memory. Hard disk emulator is proposed.

According to the technique proposed in Japanese Patent Application No. 2-230807, it is possible to eliminate the need for dedicated hardware and dedicated software when introducing the optical disc device and to supplement the low throughput of the optical disc device. It is possible to obtain excellent effects such as

The hard disk device or the non-volatile memory used for data cache when writing data from the host computer to the optical disk device which is the main storage device is also referred to as a data cache device hereinafter.

Furthermore, the inventors, including the inventor of the Japanese Patent Application No. 2302307, will be described in the following Japanese Patent Application No. 2-2.
We have found a theme that further improves the technology of the hard disk emulator proposed in 30807.

When recording data on a disc which is a recording medium of an optical disc device, there are cases where writing to a predetermined address of the disc which is the recording medium cannot be performed due to a problem with the disc which is the recording medium. In such a case, the replacement process is usually performed inside the optical disk device, but in rare cases, the replacement area may become full, or the optical disk device itself may cause a hard error.
In this case, writing to the predetermined address cannot be completed normally.

In an optical disk device that does not perform data cache, if such a recording failure occurs when recording data from the host computer, it is possible to deal with the problem relatively easily.

For example, when a recording failure occurs and this error end information is transferred to the host computer, it is conceivable to record the data that could not be recorded by designating another address of the disk as the recording medium. .

However, if a recording failure occurs in the optical disk device for data cache, it is not easy to deal with this problem.

For example, if such a recording failure occurs in the state where a large amount of cache data is recorded in the data cache device, the end information of the host computer will be output when the recording in the data cache device is completed. This is because it has been sent.

The handling of cache data recorded in the data cache device cannot be processed by an ordinary host computer.

The present invention has been made in view of the theme of further improving the technology relating to the optical disk device for performing data cache, such as such a hard disk emulator, and is more effective against the above-mentioned recording failure. It is an object of the present invention to provide a method for determining the normal end of data writing in an optical disk device, which can deal with the situation.

[0022]

According to the present invention, when data is written from a host computer to an optical disk device which is a main storage device, data is cached by using a hard disk device or a non-volatile memory. Even if it is not necessary to write data to the optical disk device immediately, the temporary access to the optical disk device is performed according to the address of the data accessed from the host computer, the data cache is normally terminated, and the temporary access is normally performed. The above object is achieved by determining the normal end of data writing from the host computer based on the end.

Further, the above object is achieved by executing the data cache and the temporary access in parallel.

[0024]

According to the present invention, in order to more effectively deal with a recording failure in an optical disk device that performs data caching, data caching is performed so that the optical disk device can immediately write data when writing data from the host computer. Even if it is not necessary to write data to the optical disk device, temporary access to the optical disk device is performed according to the address of the data accessed from the host computer.

Further, in the present invention, the normal end of the data write from the host computer is judged by the normal end of the data cache of writing the write data from the host computer to the data cache device and the normal end of the temporary access. To do. This normal termination determination is transferred to the host computer as termination information.

FIG. 2 is a flowchart of a process of recording data on a disc, which is a recording medium, of a general optical disc device.

In FIG. 2, in step 202,
The recording head is positioned (seeked) in the radial direction of the recording medium disk.

In step 204, the above-mentioned step 20 is executed.
After the positioning of 2, the rotation of the address (block) to be recorded, which is physically formatted on the disc that is the recording medium, is waited for.

In step 206, the above-mentioned step 20 is performed.
Predetermined data is recorded in the address (block) for which rotation was waited in 4. When recording data to a large number of consecutive addresses (blocks), the process of step 206 is continuously performed while rotating the disc.

In the optical disk device, the positioning of the recording head in the above-mentioned step 202 is performed by reading the data (information about the address such as the block number) recorded on the disk as the recording medium while reading the data. There is a device for detecting the position of the recording head.

In most optical disk devices, at least when waiting for the rotation of the address (block) to be recorded in step 204, the predetermined data (block number, etc.) written on the disk as the recording medium is read. Address information) is read out, and the address (block) of the data passing through the recording head in accordance with the rotation is detected from the read data.

The present invention has been made paying attention to such positioning detection and address (block) detection of the optical disk device.

That is, in recording data on a disk which is a recording medium, if the recording head positioning detection relating to the address of the recorded data is normally performed, the actual data to be performed after that is detected. It was made by finding that there is a high probability that the writing will be normally performed.

Alternatively, when the address (block) detection according to the address of the data to be recorded is normally performed in writing the data to the disc which is the recording medium, the actual data writing to the disc is normal. It was made by finding that there is a high probability that it will be performed on.

Therefore, according to the present invention, the data is recorded before the data is actually recorded on the disc which is the recording medium of the optical disc device by performing the temporary access for the above-mentioned positioning detection and the above-mentioned address (block) detection. It is determined whether the writing can be completed normally.

FIG. 1 is a flowchart showing the gist of the present invention.

The entire recording process shown in the flowchart of FIG. 1 is a recording process executed in accordance with the data writing from the host computer of the optical disk device which performs the data cache.

Therefore, the recording process shown in the flowchart of FIG. 1 is started by receiving a command from the host computer.

When the recording process of FIG. 1 is executed, first, the recording process to the data cache device in step 102 and the temporary access process to the optical disc device in step 104 are executed in parallel.

The step 102 is a process of recording the write data received from the host computer in the data cache device provided to compensate for the above-mentioned disadvantages of the optical disk device such as low throughput.

The step 104 is performed later.
This is a temporary access process for preliminarily determining whether or not the data received from the host computer and recorded in the data cache device is normally recorded in the optical disc device.

This temporary access processing is the above-described positioning detection and address (block) detection, but it may be processing up to the middle of the recording processing of the optical disk device shown in FIG. 2, and the present invention implements this. It is not limited.

For example, the process shown in the flow chart of FIG. 2 may be the process up to the point where the data recording on the disk which is the recording medium in step 206 is performed halfway.

In this way, step 2 is performed within the range of time.
When the processing up to 06 is performed as a temporary access, when the data sent as the write data from the host computer is a large amount of data, the time required for the temporary access processing does not pose a problem, Further, the accuracy of the data write normal end determination by the temporary access process can be improved.

In FIG. 1, in step 110 and step 112, it is judged whether data writing from the host computer is normally completed.

The judgment of the normal end of the data writing is performed by the data from the host computer when the condition "normal end of data cache device" is satisfied and the condition "normal end of optical disk device" is satisfied. It is determined that the writing has been completed normally.

Therefore, if it is determined to be "Y" in step 110 and "Y" in step 112, the process proceeds to step 116 to transfer the normal termination information to the host computer.

On the other hand, if it is determined to be "N" in step 110 or "N" in step 112, the process proceeds to step 118 to transfer the abnormal termination information to the host computer.

Step 116 or Step 1
After the execution of the processing of 18, the recording processing shown in the flowchart of FIG. 1 is all ended.

As described above, according to the present invention, when data is written from the host computer to the optical disk device for data caching, it is performed later even if it is not necessary to immediately write data to the optical disk device by the data cache. Whether or not the data writing to the optical disk device is normally completed can be determined in advance, and it is possible to more effectively deal with the recording failure.

The recording process described above with reference to FIG.
The recording process to the data cache device in step 102 and the temporary access process to the optical disc device in step 104 are executed in parallel. By executing them in parallel in this way, the recording process shown in FIG. The entire access time can be shortened. However, the present invention is not limited to this, and these steps 1
The processing of 02 and the processing of step 104 may be partially executed in parallel, or these steps 10
The process of 2 and the process of step 104 may be executed in series, and in any case, it is possible to effectively deal with the recording defect.

[0052]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 3 shows the basic configuration of the embodiment of the present invention.

The host computer 1 records data in the hard disk emulator 2 via the interface bus 6 and reproduces the data from the hard disk emulator 2.

The hard disk emulator 2 comprises an emulation unit 3, a hard disk device 4, and an optical disk device 5, and these units and devices 3, 4, and 5 are connected by an interface bus 7.

The emulation unit 3 is a unit for performing overall control of the hard disk emulator 2, and controls emulation as a hard disk, data transfer with the hard disk device 4 and the optical disk device 5, and data transfer with the host computer 1.

The hard disk device 4 is used as a nonvolatile data cache device and has a smaller capacity than the target hard disk device to be emulated.

The optical disc device 5 is capable of exchanging a disc which is a recording medium, and employs a rewritable type for emulating a hard disc.

FIG. 4 shows the data flow during recording in the above embodiment.

The data sent from the host computer 1 is recorded in the hard disk device 4 via the emulation unit 3. When the recording command sequence from the host computer 1 is completed, the data recorded in the hard disk device 4 is transferred to the optical disk device 5. This transfer is performed while the hard disk emulator 2 is not being activated by the host computer 1, that is, as a background process of the hard disk emulator 2. Also, during this background processing,
When the hard disk emulator 2 is started up from the host computer 1, the background processing is immediately stopped, the started command sequence is executed,
After finishing this, the remaining background processing is restarted and executed.

FIG. 5 shows a data flow during reproduction in the above embodiment.

When the data designated by the host computer 1 is in the hard disk device 4, the data is transferred from the hard disk device 4 to the emulation unit 3
Is sent to the host computer 1 via.

In the background process during reproduction, when the reproduction data is sequential file data described later with reference to FIGS. 7 and 8, the data in the area following the reproduction data is transferred from the optical disk device 5 to the hard disk device 4. To be done. That is, prefetching is performed.

In general, the access from the host computer 1 to the auxiliary storage device is often made sequentially, and there is a high possibility that the data following the data will be accessed after the access to the certain data. The prefetch performed in the background process becomes more effective.

If the data designated by the host computer 1 does not exist in the hard disk device 4, it is transferred from the optical disk device 5 via the emulation unit 3.

Since the hard disk device 4 is a randomly accessible memory, the seek time is often not negligible in consideration of the performance of the entire system.

Generally, the seek time of the current hard disk drive is about 20 to 50 ms including the rotation waiting time, while the time required for recording per sector is often 1 ms or less. Considering the case where there are many random accesses, the actual recording is only about several ms, but since the seek requires about several tens of ms, the time required from the viewpoint of the host computer 1 is (several tens ms) + (several ms). Become.

On the other hand, in the hard disk emulator 2 of the above embodiment, since the data is sequentially stored in the hard disk device 4 used as the cache memory regardless of the address designated by the host computer 1, no seek occurs and the host does not The time required from the computer 1 is only a few ms.

Next, a concrete circuit configuration of the emulation unit 3 is shown in FIG.

The emulation unit 3 has an interface with the host computer 1 and an interface with the optical disk device 5 and the hard disk device 4. Inside the emulation unit 3, the host computer side interface control circuit 6 and the memory device side interface control circuit are provided. 7 controls each interface protocol.

The data transfer control circuit 8 is provided between the host computer 1 and the memory device, and between the optical disk device 5.
And data transfer between the hard disk device 4 and the hard disk device 4. The data buffer 9 operates as a buffer memory when transferring these data.

The overall control of the emulation unit 3 is controlled by the CPU (Central Processing Unit) 10
And a program ROM (program read only memory) 11 and a work RAM (work random access memory) 12.

The work RAM 12 is used not only as a general work area for the CPU 10 but also stores address information of data on the hard disk device 4.

As will be described later with reference to FIGS. 9 and 10, this address information is information indicating the correspondence between the cache address (hard disk address) and the emulation address (same as the optical disk address),
Normally, it is generated every time new data is recorded in the cache area.

When using the cache area,
Based on this address information, the CPU 10 transfers data between the host computer and the hard disk device 4, and performs background processing between the optical disk device 5 and the hard disk device 4.

Since the background processing is performed independently of the host computer 1, the memory power backup circuit 13 for the work RAM 12 is prevented in order to prevent the power from being turned off and the address information being lost before the background processing is completed. To provide.

Reference numeral 14 in the drawing denotes an interface bus with the host computer 1, and 15 shows an interface bus with the memory device, that is, the optical disk device 5 and the hard disk device 4. Each block in the emulation unit 3 is connected by a data bus 16 and an address bus 17. Host computer 1
Data between the optical disk device 5 and the hard disk device 4 is transferred via the data bus 16 by the data transfer control signal 18.

Since this data transfer is generally slowed down when it is performed via the CPU 10, it is controlled by a data transfer control signal 18 such as a transfer request signal or a response signal generated by the data transfer control circuit 8. Code 19
Is from the memory power backup circuit 13 to the work RAM 1
2 shows the backup power supply to be supplied.

The operation of this embodiment will be described below.

In the present embodiment, a general cache area to which the present invention is applied (hereinafter, referred to as a normal cache area) and data of continuous emulation addresses including emulation addresses that are frequently accessed are temporarily stored. It has a fixed cache area for recording.

The correspondence between the cache addresses in the fixed cache area and the consecutive emulation addresses assigned to them is one to one.
It is a correspondence of.

When accessing such a fixed cache area, the address information required when accessing the above-mentioned normal cache area is not required.

Further, even if the host computer frequently records to the emulation address assigned to the fixed cache area, the recording of the data to the corresponding cache address of the fixed cache area is performed only the designated number of times. is there.

That is, by using the fixed cache area in this way, when the normal cache area is used, the data that has not been transferred to the main storage device and is still recorded in the normal cache area becomes full. There is no fear that the address information in the work memory for using the normal cache area will be full.

As described above, in the present embodiment, by providing the fixed cache area, even if the host computer frequently accesses, there is a fear that the data of the data cache device will be full, and the data in the work memory will be full. It is possible to reduce the risk that the address information of will become full.

FIG. 7 is a map of the total storage capacity area of the optical disk device 5 of the above embodiment.

In FIG. 7, reference numerals A10b and A12 are used.
b and A14b are a fixed cache area allocation area, a normal cache area allocation area, and a prefetch area allocation area, respectively.

Fixed cache area allocation area A
10b, a normal cache area allocation area A12b, and a prefetch area allocation area A14b are allocated corresponding to a fixed cache area A10a, a normal cache area A12a, and a prefetch area A14a, which will be described later, respectively.

As shown in FIG. 7, the total storage capacity of the optical disk device 5 used in this embodiment is 300M.
It is B (megabytes).

Data relating to the OS management information is recorded in the first 4 MB of the total storage capacity area of the optical disk device 5.

In the optical disk device 5 of this embodiment, the recording medium on which data is actually recorded can be replaced. Accordingly, the OS management information data D3 of 4 MB at the head of the total storage capacity area is mainly information relating to file management of data recorded on the recording medium attached to the optical disk device 5.

The OS management information data D3 is data that is frequently accessed by the host computer.

Therefore, as indicated by reference numeral A10b in FIG. 7, the OS management information data D3 is a fixed cache area allocation area.

Further, in FIG. 7, the area designated by reference numeral A12b is a normal cache area allocation area.

The area of 4 MB to which the code A14b is attached is a prefetch area allocation area.
In the prefetch area allocation area A14b, sequential file data D2 in which access is performed sequentially in the order of addresses is recorded.

Reference numeral D1 in the normal cache area allocation area A12b of FIG. 7 is hot data, and as will be described later with reference to FIG.
The data is expanded in the normal cache area A12a.

FIG. 8 is a map diagram of all cache areas of the hard disk device 4 of the above embodiment.

In FIG. 8, reference numerals A10a and A12 are used.
a and A14a are a fixed cache area, a normal cache area, and a prefetch area, respectively. or,
Reference numerals D1, D2, D3 in FIG. 8 are the same as those of the same reference numerals in FIG.

As shown in FIG. 8, the total storage capacity of the hard disk device 4 is 40 MB.

The total storage capacity of the hard disk device 4 is a cache area composed of a normal cache area A12a, a prefetch area A14a and a fixed cache area A10a.

In the normal cache area A12a, 32 MB is allocated from the head of all cache areas.

Incidentally, this normal cache area A12a
The data recorded in 1 is hereinafter referred to as hot data D1.

The prefetch area A14a is 4M following the aforementioned 32MB normal cache area A12a.
This is area B.

At the time of access from the host computer,
The data to be accessed is the code A14b in FIG. 7 described above.
In the case of the sequential file data D2 recorded in the prefetch area allocation area indicated by, the prefetch area indicated by reference numeral A14a in FIG. 8 is used as the cache area.

At the time of access for reading the sequential file data D2 from the host computer, prefetching by the background processing described above with reference to FIG. 5 is performed.

The fixed cache area A10a of 4 MB, which is an area following the pre-fetch area A14a of 4 MB of FIG. 8, is the same as the fixed cache area allocation area A10b of FIG. 7 of the OS management information data D3. Used for data cache.

The storage capacity of the fixed cache area A10a of the hard disk device 4 is the fixed cache area allocation area A located at the head of the optical disk device 5 described above.
It is the same as the storage capacity of 4 MB of 10b.

Further, in the data cache using the fixed cache area A10a of the hard disk device 4, it is possible to perform the processing promptly without using the address information.

9 to 12 are diagrams showing the cache address table in which the address information of this embodiment is recorded.

The cache address tables shown in FIGS. 9 to 12 are numbers No, a flag, a cache address (hard disk address) consisting of a start address and an end address, and an emulation consisting of a start address and an end address. Address (which is the same as the optical disc address).

9 to 12, the number No.
Is a record of each cache address table, that is, a serial number of individual address information.

Further, the larger the value of this number No, the newer the data.

That is, when specific address information is invalidated by performing address information integration processing as described later, new address information is not written in the invalidated portion, First, in order to fill in this invalid part, the subsequent address information is numbered N
The value of o shifts to a smaller value, and after that, new address information is written at the end.

In the diagrams showing the cache address tables shown in FIGS. 9 to 12, "flag" is a flag indicating whether the corresponding address information is valid or invalid.

That is, when this flag is "1", the cache address value and the emulation address value of the corresponding address information are valid. The valid address information also indicates the correspondence between the cache address and the emulation address of the cache data in the corresponding cache area.

On the other hand, when this flag is "0", the address information corresponding to it, that is, the cache address and the emulation address are invalid. That is, when this flag is "0", this is ignored regardless of the value of the corresponding address information.

The cache address tables shown in FIGS. 9 to 12 are used for accessing the normal cache area A12a on the hard disk 4 in accordance with the address designation from the host computer, that is, the emulation address. It is used when obtaining the cache address (hard disk address).

Alternatively, the cache address table is used for the hard disk address and the optical disk in the data transfer between the normal cache area A12a of the hard disk 4 and the normal cache area allocation area A12b of the optical disk device 5 which is performed in the background processing. It is also used when finding the correspondence with an address.

In this embodiment, the emulation address and the optical disc address correspond one-to-one, and can be regarded as the same.

The address information integrating method in the hard disk emulator of this embodiment will be described below with reference to FIGS. 9 to 12.

In the address information integration method of the hard disk emulator of this embodiment, the processing of each item of the concatenation processing of address information shown in FIG. 13 and the processing of each item of the inclusion processing of address information shown in FIG. Is being done.

First, in FIG. 9 and FIG. 10, the process of the item of number 1 of the concatenation process of the address information of FIG. 13 is performed.

In FIG. 9, the cache address is 00
The emulation addresses of the cache data indicated by the address information of 0000 to 00001E and the cache data indicated by the address information of 00001F to 00003E are 01F001 to 01F01F or 01F020 to 01F03F, respectively. ing.

That is, the cache data corresponding to the address information of No. 1 and the cache data corresponding to the address information of No. 2 are adjacent to each other while being written in the cache area of the hard disk device,
Moreover, the emulation addresses are consecutive.

Similarly, the respective cache data indicated by the address information of numbers 4 to 7 in FIG. 9 are continuous in the state of being written in the cache area of the hard disk device.

That is, the respective cache data corresponding to the address information of the numbers 3 to 7 are written in the hard disk cache area in the order of numbers, and the emulation addresses of the cache data of the numbers 3 to 7 are , Are consecutive in this numerical order.

Therefore, the address information of number 1 and the address information of number 2 in FIG. 9 can be integrated according to the processing of the item of number 1 in the concatenation processing of address information in FIG. Similarly, a total of five pieces of address information from No. 3 to No. 7 can be integrated into one piece of address information.

In the cache address table of FIG. 10, a value for which the concatenation process of the address information of the cache address table of FIG. 9 is completed is written.

That is, the address information of number 1 in FIG. 10 is address information obtained by integrating (connecting) the address information of number 1 and the address information of number 2 in FIG. 9 described above. Further, the address information of No. 2 in FIG. 10 is the address information obtained by integrating (connecting) a total of five pieces of address information from No. 3 to No. 7 in FIG.

The values of the cache address and the emulation address written in the address information of numbers 3 to 7 in FIG. 10 are respectively the caches of the address information of numbers 3 to 7 in FIG. The value written in the address is the same as the value written in the emulation address, but since the flag is "0", these values are invalid.

In this way, by performing the integration (concatenation) processing of the address information of the cache address table of FIG. 9, it is possible to reduce the total of 7 pieces of address information to the total of 2 pieces of address information.

In the diagram showing the cache address table in which the address information shown in FIG. 11 is recorded, the cache data corresponding to the address information of number 3, that is, the cache address 00002 of the cache area.
The cache data written from F to 00007E is the emulation addresses 01F000 to 01F.
The data is data to be written in 04F and is newer than the cache data corresponding to the address information of number 1 and the cache data corresponding to the address information of number 2.

Therefore, the emulation address of the cache data corresponding to the address information of this number 3 is
The emulation addresses of the cache data corresponding to the address information of No. 1 and the cache data corresponding to the address information of No. 2 recorded before that are included. Therefore, a total of three pieces of address information from No. 1 to No. 3 in FIG.
Can be integrated (included) in accordance with the process of item 1 of the inclusion process of the address information.

The cache data corresponding to the address information of No. 6 in FIG. 11, that is, the cache data having emulation addresses from 000020 to 00005F is recorded before the recording of the cache data corresponding to the address information of No. 6. The emulation addresses of the cache data corresponding to the address information of No. 4 and the cache data corresponding to the address information of No. 5 are included.

Therefore, a total of three pieces of address information from No. 4 to No. 6 are integrated (included) according to the processing of the item of No. 1 of the inclusion processing of address information in FIG. 14 described above.
can do.

In the state shown in FIG. 11,
Emulation address is 000090 to 0000
When a new data of AF is to be written in the normal cache area, this data is written in the cache area following the cache address of the address information of No. 7 in FIG.

Data newly written in the cache area in this way, that is, cache data is the cache data corresponding to the address information of number 7 in FIG.
It becomes adjacent in the state of being written in the cache area.

Since the emulation addresses of the cache data newly written in the cache area are 000090 to 0000AF, the emulation addresses 000080 to 000009F of the cache data corresponding to the address information No. 7 in FIG.
Partly overlaps with. That is, these cache data are
Emulation addresses 000090 to 000009
Overlap in F.

Therefore, when writing cache data to such a new cache area, it is determined that the condition of item 2 of the address information concatenation process of FIG. 13 is satisfied.

Therefore, the newly written cache data is the emulation address 0000 of the cache data indicated by the address information No. 7 in FIG.
The writing is performed while overwriting the portion corresponding to the overlapping portion of 90 to 000009F.

That is, the newly written cache data has the cache addresses 0000C5 to 000.
It is written by 0E4.

Further, the address information of number 7 in FIG. 11 and the address information of the newly written cache data can be integrated (connected).

The cache address table shown in FIG. 12 shows the result of integrating the address information of the cache address table of FIG. 11 described above.

The address information of No. 1 in FIG. 12 is address information in which a total of three pieces of address information of No. 1 to No. 3 in FIG. 11 are integrated. That is, the address information of No. 1 in FIG. 12 is address information in which the address information of No. 1 and the address information of No. 2 in FIG. 11 are included in the address information of No. 3 in FIG. .

Further, the address information of No. 2 in FIG. 12 is address information in which a total of three pieces of address information of No. 4 to No. 6 in FIG. 11 are integrated. That is,
The address information of No. 2 in FIG. 12 is the address information in which the address information of No. 4 and the address information of No. 5 in FIG. 11 are included in the address information of No. 6 in FIG. .

The address information of No. 3 in FIG. 12 is integrated (concatenated) with the address information of No. 7 in FIG. 11 and the address information of newly written cache data.
Address information.

As shown in FIG. 12, in this embodiment, the total of 7 + 1 address information can be reduced to a total of three address information.

As described above, the hard disk emulator of this embodiment is an optical disk device that performs data hash. Further, in this embodiment, the data write normal termination judging method of the present invention described above with reference to FIG. 1 is performed.

However, by performing the recording process as shown in FIG. 1 and detecting most of the recording defects in advance, the problems relating to the process for dealing with such recording defects when occurring are reduced. be able to.

As described above, the present embodiment uses the optical disk device 5 which is the main storage device and the hard disk device 4 which is used as a cache area during emulation, for access to recording and reading from the host computer. On the other hand, it conforms to the specifications of the emulated hard disk drive.

In this embodiment, a hard disk device is used as a data cache device, and a hard disk emulator that compensates for the disadvantages of the optical disk device is constructed.

Further, in the hard disk emulator of this embodiment, the hard disk device is provided with the fixed cache area together with the cache area, so that even if the host computer frequently accesses it, it is not transferred to the optical disk device. So, the cache data that is still recorded in the hard disk device used as a data cache device becomes full, or
It is possible to prevent the address information in the work memory from becoming full.

[0153]

As described above, according to the present invention, it is possible to obtain an excellent effect that a recording defect can be detected in advance when data is written from the host computer to an optical disk device which performs data cache. it can.

[Brief description of drawings]

FIG. 1 is a flowchart showing the gist of the present invention.

FIG. 2 is a flowchart showing a process of recording data on a disc, which is a recording medium, of a general optical disc device.

FIG. 3 is a block diagram showing a basic configuration of an embodiment of the present invention.

FIG. 4 is a block diagram showing a data flow during recording in the above embodiment.

FIG. 5 is a block diagram showing a data flow during reproduction in the same manner.

FIG. 6 is a block diagram showing a specific circuit configuration of an emulation unit which is a constituent element in the above embodiment.

FIG. 7 is a map diagram of a total storage capacity area of the optical disk device of the above embodiment.

FIG. 8 is a map diagram of all cache areas of the hard disk device of the embodiment.

FIG. 9 is a diagram showing a cache address table in which the address information of the embodiment is recorded.

FIG. 10 is a diagram showing a cache address table in which address information in which the address information of FIG. 9 is integrated is recorded.

FIG. 11 is a diagram showing a cache address table in which the address information of the above embodiment is recorded.

FIG. 12 is a diagram showing a cache address table in which address information in which the address information of FIG. 11 is integrated is recorded.

FIG. 13 is a diagram showing an address information concatenation process of the embodiment.

FIG. 14 is a diagram showing an address information inclusion process of the embodiment.

[Explanation of symbols]

1 ... host computer, 2 ... Hard disk emulator, 3 ... Emulation unit, 4 ... Hard disk device, 5 ... Optical disk device, 6 ... Host computer side interface control circuit, 7 ... Interface control circuit for memory device side, 8 ... Data transfer control circuit, 9 ... Data buffer, 10 ... CPU, 11 ... Program ROM, 12 ... Work RAM, 13 ... Memory power backup circuit, 14 ... Interface bus, 15 ... Memory device (interface bus), 16 ... Data bus, 17 ... Address bus, 18 ... Data transfer control signal, 19 ... Backup power supply, A4 ... Data cache device all cache areas, A5 ... Total storage capacity area of optical disk device, A10a ... Fixed cash area, A12a ... Normal cash area, A14a ... Prefetch area, A10b ... fixed cache area allocation area, A12b ... Normal cache area allocation area, A14b ... Prefetch area allocation area, D1 ... hot data, D2 ... Sequential file data, D3 ... OS management information data.

Claims (2)

[Claims] 1. When data is written from a host computer to an optical disk device which is a main storage device, data is cached using a hard disk device or a non-volatile memory, and data is immediately written to the optical disk device by the data cache. Even if it is not necessary, a temporary access to the optical disk device is performed according to the address of the data accessed from the host computer, and the normal termination of the data cache and the normal termination of the temporary access cause the host computer to A method for determining a normal end of data writing of an optical disk device, which comprises determining a normal end of data writing. 2. The data write normal end determination method according to claim 1, wherein the data cache and the temporary access are executed in parallel.