JPH0519332B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a binary code conversion method, and more specifically, converts a binary data bit sequence into a binary channel.
Concerning converting to a bit series. That is, a binary data bit sequence is a continuous data bit sequence.
The continuous data block is divided into blocks each having m bits.
A continuous channel block consisting of (n ₁ + n ₂ ) (where n ₁ + n ₂ > m) channel bits, an information block consisting of n ₁ information bit and a separation consisting of n ₂ separate bits. The information block is converted into one in which the information block is separated one by one by the separation block, and the continuous first channel bit of code "1" is converted into at least d consecutive second channel bits. separated by a channel bit of code “0”,
Relating to a binary code conversion method in which the number of consecutive channel bits of the second code "0" does not exceed k, and in particular, a method intended to reduce low frequency spectrum and DC unbalance. It is. In digital transmission and magnetic and optical recording and reproducing systems, information is typically transmitted or recorded as a sequence of symbols. Together, these symbols constitute an alphabet (often a binary alphabet; a code). In the case of a binary code, one symbol, for example “1”, is converted to NRZM
(NRZ-mark) code as a transition between two magnetization states on a magnetic disk or tape, or as a transition between two focused states on an optical disk. The other symbol "0" is then recorded as the absence of such a transition. As a result of certain system requirements, some rules are actually imposed on the sequences of symbols that occur.
Some systems require self-clocking, so that the sequence of transmitted or recorded symbols must be transmitted or recorded with enough transitions to generate the clock signal used for detection and synchronization. There must be. Additionally, since certain symbol sequences are used for special purposes, for example as synchronization signals, it is required that such symbol sequences do not occur in the information signal. When a pseudo synchronization sequence occurs in the information signal,
The synchronization signal becomes unambiguous, thus making it unsuitable for synchronization purposes. Additionally, it is also required that transitions be not spaced too closely to limit inter-symbol interference. In the case of magnetic and optical recording, the requirements on the spacing between transitions are also related to the information density of the recording medium. This is because, at a given minimum distance between two adjacent transitions on the recording medium, if the minimum time interval Tmin corresponding to the signals recorded thereon increases, the information density also increases in the same proportion. The required minimum bandwidth Bmin is also related to the minimum distance between transitions (Bmin=1/2Tmin). As in the case of common magnetic recording channels,
If the information channel does not transmit direct current, it is necessary that the symbol sequence in the information channel contains almost no direct current component. By the way, the first method mentioned is described in the first reference (Tang, DT, Bahl, LR, “Block codes for
a class of constrained noiseless channels.”
Information and Control, Vol.17, no.5,
Dec. 1970, pp. 436-461.). This paper is concerned with block codes based on q-valued symbol blocks of the d-, k-, or d-k rules. Here, such a block satisfies the following requirements. (a) d rule: Two “1”s are separated by at least a string of d consecutive “0”s. (b) k rule: The maximum length of a string consisting of consecutive "0"s is k. For example, a sequence of binary data bits is divided into consecutive blocks. Each of these blocks has m bits. These data blocks of m bits are converted into information blocks of n information bits (where n>m).
Since n>m, the number of combinations of n information bits exceeds the number of possible data blocks, 2 ^m . For example, if d rules are required for information blocks to be transmitted or recorded, there are 2 ⁿ data blocks that can be realized.
The correspondence between the 2 ^m information blocks similarly selected from the 2 ^m information blocks is selected such that the correspondence is established for the information blocks that satisfy the d rule. According to Table 1 on page 439 of the first reference mentioned above, it can be seen how many information blocks there are depending on the length of the block (n) and the imposed request d. Then, under the condition that the minimum distance d is 1,
There are 8 information bit blocks of length n 4.
This results in a data block of length m 3 (2 ³ =
8 data words) is represented by the following information block. That is, an information block having length n of 4 information bits, in which adjacent "1"
At least one "0" symbol is placed between the symbols. For example, such coding is as follows. Here, the arrow ←→ indicates that one block corresponds to the other block, and vice versa. 000←→0000 001←→0001 010←→0010 011←→0100 100←→0101 101←→1000 110←→1001 111←→1010 By the way, sometimes when information blocks are connected, certain requirements, such as the d rule requirements may not be met without using other means. Therefore, in the above-mentioned paper, it is proposed to provide separation bits between information blocks.
If the d rule is required, a separate block of d bits of "0" is valid. In the above example where d is 1, one isolation bit ("0") is sufficient. A data block consisting of three data bits may be converted by (4+1) channel bits. Such a conversion method is disadvantageous in that the low frequency components (including DC components) of the frequency spectrum of the channel bit string are rather large. Another drawback is that the converters (modulators and demodulators), especially the demodulators, become complex. Regarding the first issue, see the second reference (Patel, AM, “Charge-constrained byte-
oriented(0,3) code”, IBM Tecknical
Disclosure Bulletin, Vol.19, No.7.Dec.1976,
It is shown in pp. 2715-2717.) that connecting channel blocks with so-called inverting or non-inverting couplings can limit the DC unbalance of dk rule codes. In this case, the current polarity of the channel block is selected to reduce the DC unbalance of the previous channel block. However, since a dk rule code is considered here that allows information blocks to be combined without violating the dk rule, there is no need to add separation bits for the dk rule. The present invention has been made in consideration of the above circumstances, and is the above-mentioned binary code conversion method for converting a binary data bit series into a binary channel bit series. The purpose of this paper is to propose a method that can improve the low-frequency spectral characteristics of signals. Hereinafter, one embodiment of the present invention will be described with reference to FIG. FIG. 1 is for explaining the method of converting a binary data bit string into a binary channel bit string, and shows several bit sequences. In FIG. 1, a binary data bit string is divided into consecutive blocks. Each of these data blocks consists of m bits. In this example, m is chosen to be 8 in the following description and drawings. The same thing can be applied to other values of m. A data block BDi of m bits is generally one of 2 ^m possible bit sequences. Such bit sequences are unsuitable for direct optical or magnetic recording, and are also unsuitable for several other reasons. That is, two symbols "1" are recorded on the recording medium, for example, as a transition from one direction of magnetization to the other direction of magnetization, or as a transition to a pit, and such symbols "1" are recorded one after the other. When you do,
The transitions must not be too close together in terms of mutual interaction. This limits the information density. At the same time, the smaller the minimum interval Tmin between successive transitions, the smaller the minimum bandwidth required to transmit or record the bit stream.
It is also necessary to consider that Bmin increases (Bmin = 1/2Tmin). Another requirement placed on data transmission and optical or magnetic recording systems is that the transmitted signal must have enough transitions in the bit sequence to be able to recover the clock used for synchronization. That's what it means. In the worst case where one block has m zeros, the preceding block ends with a large number of zeros, and the next block begins with a large number of zeros, there is a possibility that the clock cannot be extracted. be. For example, an information medium that does not transmit direct current, such as a magnetic recording medium, further needs to satisfy the requirement that the data string to be recorded has as few direct current components as possible. In optical recording, from the viewpoint of servo control, it is required that low frequency components of the data spectrum be suppressed to the maximum extent possible. In addition, demodulation can be simplified as the DC component is reduced. For these and other reasons, so-called channel coding is performed on data bits before they are transmitted over a medium or recorded. In the case of block coding (first reference), data blocks each containing m bits are coded as information blocks each containing _n1 information bits. FIG. 1 shows how a data block BDi is converted into an information block BIi. In this example, n ₁ is chosen to be 14 in the following description and figures. n ₁
Since is greater than m, not all combinations that can be formed with n ₁ bits are used. Do not use inappropriate combinations when applying to media. And, in this example, because of the one-to-one correspondence required from data words to channel words, out of over 16,000 possible transmission words,
Only 256 words are selected. Therefore, several requirements can be placed on the channel word. One request consists of two adjacent first codes within the same block of _n1 information bits,
That is, there are at least d consecutive second codes, ie, "0" information bits, between "1" information bits. 1st reference
Table 1 on page 439 shows how many such binary words there are depending on the value of d. According to this table, it is clear that if n ₁ =14, there are 277 words that have at least two bits of "0" between adjacent "1" bits. When encoding a block of 8 data bits, there are 256 (=2 ⁸ ) combinations of those data bits. Since it is a block of 14 channel bits, the requirement that d=2 is fully satisfied. Blocks of information bits cannot be concatenated without other means if similar d-rule requirements are imposed not only within n ₁ bit blocks but also at the boundaries of two adjacent blocks. .
To this end, the first reference proposes on page 451 to include one or more separation bits between channel blocks. It is easy to understand that the d rule is satisfied if at least the same number of separate "0" bits as d are included. Figure 1 shows that channel block BCi is an information block.
It is shown that it consists of BIi and separation block BSi.
The separation block consists of n ₂ bits. Therefore, the channel block BCi consists of (n ₁ +n ₂ ) bits. In this example, n ₂ is chosen to be 3 in the following description and figures unless otherwise specified. In order to generate the clock as accurately as possible, the maximum number of consecutive "0" bits between two adjacent "1" bits in one information block must be determined in advance. is required to remain at the value k. In this example where m is 8 and n ₁ is 14, for example, words with very large k can be deleted from the 277 words satisfying d=2. It is clear that k can be kept to 10. Therefore, a set of 28 (generally 2 m ) blocks each consisting of ⁸ (generally m) data ^bits is also matched one-to-one with a set of ²⁸ (generally 2 ^m ) information blocks. handle. These information blocks are selected from among 2 ¹⁴ (generally 2 ⁿ¹ ) possible information blocks. This is due in part to the imposed conditions such as d=2 and k=10 (generally the dk rule). It remains a matter of choice which data blocks correspond to which information blocks. In the first reference cited above, the number conversion from data bits to information bits is explicitly determined in a mathematically closed form. I see, such a conversion can be adopted in principle. However, in this example, a different relationship is selected as will be explained further below. Channel blocks BIi can be linked to satisfy the k rule only when a separation block is placed between the information blocks BIi. This also applies to the d rule. Since the requirements of the d-rule and the requirements of the k-rule are not mutually exclusive, but rather complementary, one and the same separate block of n ₂ bits each can in principle be used to achieve such a goal. . Therefore, the sum of the number of “0” bits preceding a certain separation block, the number of “0” bits following that separation block, and the _n2 bits (“0”) of the separation block itself exceeds the value of k. When rotating, the series of “0” is k
In order to separate the bits into no more than one series, at least one of the "0" bits of the separation bits must be replaced with a "1" bit. In addition to its role in ensuring that the requirements of the dk rule are met, isolation blocks can be used to reduce DC unbalance. This means that when connecting information blocks, in some cases a predetermined format of the block is specified, but in many cases no conditions are imposed on the format of the separated blocks. , or that only limited conditions are imposed, it is easy to understand. The degrees of freedom created in this way are used to reduce DC unbalance. The occurrence and increase of DC unbalance is explained as follows. Assume that an information block BI ₁ as shown in FIG. 1 is recorded on a recording medium in, for example, the NRZ mark format. In this format, “1”
is marked as a transition at the beginning of the corresponding bit cell. When it is "0", no transition is recorded.
The bit series indicated by BI ₁ has the shape indicated by WF. Then, the bit series is recorded on the recording medium in such a shape. In the series under consideration, the positive level is longer than the negative level, so this series has DC unbalance. Digital sumvalue is often used as a measure of determining DC unbalance. Each waveform level
With WF+1 and -1, the digital sum is equal to the waveform integrated along the series. In the example shown in Figure 1B, the digital sum is +6T.
become. However, T is the length of the bit interval.
If such a sequence is repeated,
DC imbalance occurs. Generally, this DC unbalance causes fluctuations in the baseline and reduces the effective S/N. As a result of the decrease in S/N, the accuracy of detecting the recorded signal decreases. Isolation block to limit DC unbalance
BSi is used as follows. Suppose now that a certain data block BDi is supplied. This data block BDi is converted into an information block BIi by means of a table recorded in a recording device, for example. After this, a set of possible channels
Blocks are generated. This block is (n ₁
+n ₂ ) bits. All these blocks are similar information blocks (bits in Figure 1B).
Cells 1 to 14) have n ₂ separate bits (Fig. 1B
bit cells 15, 16, 17) that can be realized.
As a result, in the example shown in FIG. 1B, a set of 8 (=2 ⁿⁱ ) possible channel blocks is formed. After this, as an essentially arbitrary procedure, the following parameters are determined for each possible channel block: (a) From the point of view of the channel block preceding the applicable channel block,
Determine whether the requirements of the d and k rules are consistent with the current separation block format. (b) Determine the digital summation for the possible channel blocks. A first display signal is generated for each possible channel block consistent with the requirements of the d- and k-rules. If you select the code and parameters,
Such an indication signal can be generated for at least one possible information block. Finally, among the possible channel blocks in which the first display signal is generated,
For example, the channel block with the smallest absolute value of the digital sum is selected. However, a better method is to accumulate digital sums of previous channel blocks. Then, a block whose absolute value of the accumulated digital sum decreases is selected from among the channel blocks most suitable for next transmission. The words selected in this way are transmitted or recorded. One of the advantages of this method is that isolation bits needed for other purposes can simply be used for the purpose of limiting DC unbalance. In addition, there is the advantage that the interference of the transmitted signal is limited to the separation block and does not propagate to the information block (here also ignoring the polarity of the waveform to be transmitted or recorded). Demodulation of the read recorded signal is performed only for information bits. There is no need to consider separate bits. Next, other embodiments of the present invention will be described. FIG. 2 shows some other embodiments of this method. Figure 2 A is the channel block...
The series BCi _-1 , BCi, BCi ₊₁ , ... is shown. These blocks have a predetermined number of (n ₁ +n ₂ ) bits. Each of the channel blocks is
It has an information block consisting of n ₁ bits and a separation block consisting of n ₂ bits...BSi _-1 , BSi, BSi ₊₁ , . . . In this embodiment, the DC imbalance is determined over several blocks. For example, as shown in FIG. 2A, it is determined between two channel blocks BCi and BCi ₊₁ . This DC unbalance is determined in a manner similar to that described for the example of FIG. However, the condition is that a possible super block format is formed for each husband's super block SBCi. That is, block BCi,
In the information block about BCi ₊₁ , block BSi,
The possible combinations that can be generated from two separate bits of BSi ₊₂ are added. The combination that minimizes the DC unbalance is then selected from such a set. This method has the following advantages. That is, the residual DC unbalance becomes more uniform because one or more previous channel blocks are taken into account and the adjustment is optimal. A more preferred variant of this method has notable features. This feature allows super block SBCi (Fig. 2A) to be used only after the DC unbalance has been minimized.
is shifted by one channel block. This means that the super block
Block BCi (Fig. 2A) forming part of SBCi is processed, and the next super block SBCi ₊₁ (not shown) is combined with block BCi ₊₁ and block whose DC unbalance has been minimized as described above. BCi ₊₂ (not shown). And block BCi ₊₁ is super block
It will be part of both the SBCi and the next super block SBCi ₊₁ . Therefore, Super Block SBCi
The tentative selection of separation bits for block BSi ₊₁ for can be quite different from the final selection for super block SBCi ₊₁ . Since each block is evaluated several times (twice in this example), the effects of DC unbalance and noise are further reduced. FIG. 2B shows another embodiment. In this embodiment, the DC unbalance is determined for several blocks (SBCj) at the same time. For example, as shown in Figure 2B, four channel blocks BCj ⁽¹⁾ , BCj ⁽²⁾ ,
This is about BCj ⁽³⁾ and BCj ⁽⁴⁾ . These channel blocks have a predetermined number of information bits, _n1 . However, for each channel bit, the separation blocks BSj ⁽¹⁾ , BSj ⁽²⁾ , BSj ⁽³⁾ ,
The number of separate bits in each of BSj ⁽⁴⁾ is not the same. For example, the number of information bits can be increased to 14, and the number of information bits can be increased to 14, and the number of information bits can be increased to ¹⁴ , and the number of information bits can be increased ^{to 14} .
The number of separation bits of each block BSj ⁽³⁾ can be two, and the number of separation bits of separation block BSj ⁽⁴⁾ can be six. DC unbalance is determined in the same manner as described for example FIG. 2A. The advantages mentioned above can also be obtained in this case. In addition to this advantage, this example has the advantage that the DC unbalance can be reduced by using a relatively long separation block. More specifically, the residual DC unbalance of a channel bit sequence in which each channel block has an equal number of bits, say 3, is such that each separate block has an average of 3 bits, but 2 vs. 2 vs. 2 vs. 6 bits. Channel with bits divided by
This is larger than the residual DC unbalance of the bit series. It should be noted that the above-described time series of functions and related states of the method of the present invention can be implemented by means of common sequential logic circuits, for example microprocessors available on the market, and corresponding recording devices and peripherals. Third
The figure shows a flowchart of such an operation. In the following explanation, step annotations are used to indicate the role and status of the coding method in chronological order. Column A shows reference numbers. Column B shows notes. Column C shows the explanatory text for the corresponding step.

【table】

【table】

[Table] The flowchart described above is applied to the example shown in FIG. The corresponding flowchart can then also be applied to the example of FIG. 2, taking into account the changes already mentioned. In order to distinguish between information bits and separation bits when demodulating a transmitted or recorded channel bit sequence, (n ₃ +n ₄ ) bits are included in the channel block sequence. where n ₃
n4 are synchronization information bits, and _n4 are synchronization separation bits. Synchronization blocks are inserted, for example, every predetermined number of information blocks and separation blocks. After this word is detected, it is possible to know in which bit position the information bit is located and in which bit position the isolation bit is located. Therefore, it is necessary to somehow prevent the synchronization word from colliding with the predetermined bit series of the information block and separation block. To achieve this purpose, a special block of synchronization bits, ie synchronization bits not found in the information bit series or in the separation bit series, can be chosen. Sequences that do not satisfy the d-rule or the k-rule are not very useful in achieving this purpose. This is because in such a case, information density and self-clocking characteristics are adversely affected. However, such selection is limited to groups of sequences that satisfy the d-rule and the k-rule. Therefore, another method is proposed. A synchronization block is constructed by including, for example, at least two consecutive sequences containing an s-bit "0" between two successive "1" bits. Preferably, s is equal to k. Figure 4 shows the synchronization block.
Indicates SYN. This block is SYNP ₁ and
As shown in SYNP ₂ , it is constructed by repeating the sequence (10000000000, 1 followed by 10 0s) twice in succession. Such a sequence may be a channel bit sequence, ie a sequence of k=10. However, in addition to the synchronization block, in order to prevent this sequence from occurring twice in a row,
If the bits are part of a separate block, then
The sum of the number of separated “0” bits immediately before that “1” bit and the number of consecutive “0” information bits is equal to k, and the number of consecutive “0” bits immediately after that “1” bit is equal to k. The first display signal is suppressed when the number of information bits is also equal to the sum of the number of information bits. The method for preventing synchronized blocks from being mixed in with others has already been shown, and this is to repeatedly generate the sequence 100000000000, that is, a 1 followed by 11 0s, twice. Additionally, the synchronization block also has a synchronization isolation block. This separation block has the same role as the separation block between information blocks. Therefore, these satisfy the d rule and the k rule,
It also aims to meet the requirement of limiting DC unbalance. A method similar to the method used to prevent a false synchronization pattern from appearing in the channel bit string when a synchronization pattern occurs twice in succession can also be used to prevent a synchronization pattern from appearing before or after a synchronization block. Prevent this from occurring three times. The method described above can of course be applied to modulation and encoding. However, this method is much simpler in the reverse case, ie, during demodulation and decoding. Since the DC unbalance can be limited without affecting the information bit blocks, the information between the separate blocks is not important in demodulating the information. In addition, selecting which m-bit length data bits are associated with which n-bit information bits in the modulator is important not only in the modulator but also in the demodulator. That is, making such a selection complicates the configuration of the demodulator. In magnetic recording systems, both the modulator and demodulator are built into the device, so
Both the complexity of the modulator and the complexity of the demodulator are problems. In optical recording systems,
Since the recording medium is read-only, the user's equipment need only include a demodulator. In the case of optical recording systems, it is therefore particularly important to simplify the construction of the demodulator as much as possible without having to complicate the modulator. FIG. 5 shows an example of a demodulator. This demodulator has 14
A block of eight data bits is demodulated from a block of eight information bits. FIG. 5A shows a block diagram of the demodulator, and FIG. 5B schematically shows part of the circuit. This demodulator has AND gates 17-0 to 17-51. These AND gates 17-0 to 17-5
1 each have one or more input terminals. One of the 14 bits of the information block is applied to each input terminal. These input terminals are inverting or non-inverting. Figure 5B shows how this is done in the Ci column. The first column shows the least significant bit position _C1 of the 14-bit information block, and the fourteenth column shows the least significant bit position _C14 .
The 2nd to 13th columns in between indicate the remaining digits in relation to their bit positions. Lines l ₀ to _{l 51} correspond to the numbers of the AND gate, respectively. That is, line l ₀ corresponds to the input terminal of AND gate 17-0, and line
_l1 corresponds to the input terminal of AND gate 17-1. The same applies to others. Code 1 on line lj of column i
, it means that the content of the i-th bit position Bi is transferred to the j-th AND
This means that it is supplied to the gate 17. The symbol O in the line lj of the i-th column means that the i-th bit position Ci is applied to the j-th AND gate 17 via the inverting input terminal. As a result, the inverting input terminal of AND gate 17-0 is connected to the lth bit position _C1 ,
The non-inverting input terminal is connected to the fourth bit position _C4 (line _l0 ). And Gate 17
-1 non-inverting input terminal is at the third bit position
Connected to C ₃ (line l ₁ ). The same applies to others. The demodulator further includes eight OR gates 18-1~
It has 18-8. These or gates 18-1
~18-8 input terminal is AND gate 17-0
~17-51. Figure 5 A is Ai
The column shows how this is achieved. Column _A1 corresponds to or gate 18-1.
Column _A2 corresponds to or gate 18-2. The same goes for columns _A3 and after, and finally column _A8 corresponds to the OR gate 18-8. jth Ai
The letter A in the column indicates that the AND gate 17-j is OR.
It shows that it is connected to the gate 18-i. The circuit configuration of AND gates 17-50 and 17-51 is changed as follows. The inverting output terminal of each AND gate 17-50, 17-51 is connected to the input terminal of the other AND gate 19, respectively. The output terminal of OR gate 18-4 is connected to the other input terminal of AND gate 19. Or Gate 18-1, 18-2, 18-3,
The output terminals of 18-5 and 18-8 and the output terminal of AND gate 19 are respectively connected to output terminal 20-i. The decoded 8-bit data block is then taken out from this output terminal as parallel data. The demodulator shown in Figure 5A is a so-called FPLA
(Field Programmable Logic Array). For example, Signetix Bipolar FPLA82S100/82S101 can be used. The table shown in FIG. 5 is programmable because of this array. Due to its simplicity, the demodulator shown in FIG.
Very suitable for read-only optical recording systems. The synchronization block is detected by the circuit shown in FIG. The transmitted signal or the reproduced recording signal is supplied to the input terminal 21. This signal is
It is of MRZ-M format. This signal is supplied directly to the first input terminal of OR gate 22 and is also supplied to the second input terminal of OR gate 22 via delay element 23 . Then, a so-called NRZ-I signal is output from the output terminal of the OR gate 23. or gate 2
The output terminal of 3 is connected to the input terminal of the shift register 24. This shift register 24 consists of a number of bit cells. Each of these bit cells is provided with a tap. The number of bit cells is equal to the number of bits making up the synchronization block. In the example above, the series |0000000000|
It has 23 bit cells to be able to record 0000000000｜. Each tap is and
It is connected to the input terminal of gate 25. The input terminal of AND gate 25 is of an inverting type or a non-inverting type. When the synchronization sequence is supplied to the input of AND gate 25, this AND gate 25
A signal is output from the output terminal 26 of. This signal can be used as a synchronization pattern detection signal. Based on this detection signal, the bit sequence is divided into books each having a length of (n ₁ +n ₂ ) bits. These divided channel blocks are sequentially shifted in other shift registers. The upper n ₁ -digit bits are read out as parallel data and transferred to the input terminal of AND gate 17 as shown in FIG. 5A. The lower n _two digit bits are not used in demodulation. The hooded signal is recorded, for example, on an optical recording medium. This signal has the form shown in FIG. 1B. This signal is recorded on the recording medium in a spiral trajectory. This information format consists of a series of multiple super blocks as shown in FIG. 7, for example. Super block SBi is a synchronous block
SYNi and a large number (33 in this example) of channels.
Consists of blocks. Synchronization block SYNi is the fourth
It is configured as shown in the figure. Channel blocks BC ₁ , BC ₂ , . . . BC ₃₃ each consist of (n ₁ +n ₂ ) bits. A channel bit of "1" is represented as a transition on the recording medium. For example, as a transition from a state without pits to a state with pits. A channel bit of "0" is represented as a non-transitional state in the recording medium. The spiral information track is subdivided into constituent cells, or bit cells. These bits and
Cells form a spatial structure. This production corresponds to the subdivision of channel bits into bit time intervals. Regardless of the contents of the information bits and separation bits,
A number of subdivisions are identified on the recording medium. In this recording medium, the k rule means that the maximum distance between two adjacent transitions is (k+1) bit cell length. The longest pit (the part without pits) therefore consists of (k+1) bit cells. The d rule means that the minimum distance between two adjacent transitions is (d+1) bit cell length. Additionally, for each regular interval, there is a longest pit either after or before the longest unpitted portion. This form is part of a synchronization block. In another example, k=10, d=2 and super block SBi consists of 588 channel bit cells. This super block SBi is
It consists of a synchronization block of 27 (14+3) bit cells and 33 channel blocks. Each channel block has (14+3) channels.
It has a bit cell. It goes without saying that the present invention can be applied to a conversion circuit that converts an analog signal into a digital signal and a playback device. That is, the modulator, the transmission path, such as the optical recording medium, and the demodulator form part of an integrated system.
This system converts, for example, analog information (music, speech) into digital information.
This digital information is recorded on an optical recording medium.
Information recorded on recording media and their copies is
The information recorded on the recording medium can be reproduced by a device suitable for reproducing the information. In this case, this conversion circuit specifically uses an analog/digital converter to convert an analog signal to be recorded (music, speech) into a digital signal with a predetermined pattern (source coding). have Furthermore, in this conversion circuit, the digital signal is converted into a format that allows errors that occur when reading from the recording medium to be corrected in a device that reproduces the signal. An error correction system suitable for such purposes has already been proposed by Sony Corporation (Japanese Patent Application No. 67608/1982). The error-corrected digital signal is then
It is fed to the above-mentioned modulator for conversion into a digital signal suitable for the characteristics of the medium. Additionally, a synchronization pattern is provided, and this signal
considered to be a pattern. The signal obtained in this way is, for example, a laser control signal (NRZ-
M format). By means of this control signal, a spiral information form as a predetermined series of pits and pits can be applied to the recording medium. This recording medium or a copy thereof is read by a device for reproducing the information bits obtained from the recording medium. To achieve this purpose, the device comprises a modulator, a decoder of an error correction system and an analog/digital converter for regenerating a replica of the analog signal supplied to the conversion circuit.
Note that this decoder has already been described in detail.

[Brief explanation of the drawing]

FIG. 1 is a diagram for explaining one embodiment of the binary code conversion method of the present invention, FIG. 2 is a diagram for explaining another embodiment of the binary code conversion method of the present invention, and FIG. 3 is a diagram for explaining another embodiment of the binary code conversion method of the present invention. Figure 1 is a flowchart for explaining an example; Figure 4 is a diagram showing an example of a synchronization block used when demodulating a channel bit sequence; Figure 5 is a diagram showing an example of a decoding device; The figure is a block diagram showing an example of a circuit for detecting a synchronous bit sequence, and FIG. 7 is a diagram showing an example of a frame format of the binary code conversion method of the present invention.

Claims (1)

[Claims] “1” from a data block consisting of 1 m bits
channel bit is d or more consecutive “0”
n 1 channel bits separated by 1 channel bits, and the number of consecutive “0” channel bits is set within k (however, n _{1 >} m)
The information block consisting of the above data block and 1
In the binary code conversion method, a separation block consisting of _n2 channel bits is arranged between each information block, and the channel bit of "1" represents a transition of information. At the connection portion of adjacent information blocks via the separation block, the "1" channel bit is separated by d or more consecutive "0" channel bits, and the number of consecutive "0" channel bits is determined. A binary code conversion method, characterized in that a separation block is selected from a plurality of said separation blocks, up to k, and which reduces the DC unbalance of said information block and separation block which are continuous. .