JPH05176178A - Transmitter for digital picture signal - Google Patents

Abstract

PURPOSE:To reduce memory capacity and also to improve picture quality at the time of vari-speed reproduction by packing coefficient data caused by the coding into a synchronizing block in order from low order DC and AC components toward higher order components. CONSTITUTION:A selector SW in a transmitter for a digital picture signal used for a DCT as high efficient coding selects an output of a quantization circuit 1 when a code is received and selects an output of an area detection circuit 4 in a timing when coordinate data HV are inserted. An output from the SW is fed to a variable length coding circuit 5, code signals from the DCT are packed in a synchronizing block sequentially from a DC component DC and a lower order AC component toward higher order AC components and the result is fed to an FIFO 6. Thus, it is not required for the processing arranging regularly the DC component data with high importance, the circuit configuration is simplified, and since data of the reproduced synchronizing block include DC and AC components at the time of speed reproduction, the picture quality of a reproduced picture is improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital image signal transmission apparatus using DCT as high-efficiency coding, and more particularly to framing of transmission data.

[0002]

2. Description of the Related Art A digital VTR for recording a digital video signal on a magnetic tape by, for example, a rotary head is known. Since the amount of information in digital video signals is large,
High-efficiency coding is often used to compress the amount of transmitted data. Among various high efficiency coding, DC
Practical application of T (Discrete Cosine Transform) is progressing.

In the DCT, an image of one frame is, for example, (8
X8) is converted into a block structure, and this block is subjected to cosine transform processing which is a kind of orthogonal transform. As a result, (8 × 8) coefficient data is generated. Such coefficient data is transmitted after being subjected to variable length coding processing such as run length coding and Huffman coding. At the time of transmission, it is usual to form a sync block to which a block synchronization signal is added for each fixed length of data.

On the receiving side, the data contained in the sync block is subjected to the variable length code decoding, and then the inverse DCT conversion for converting it into the image data is performed. When decoding a variable length code, it is necessary to correctly extract the code corresponding to each coefficient data from the received data. Conventionally, in consideration of the difference in importance that exists between coefficient data, low-order data with high importance for direct current and alternating current, that is, an array that is designed to extract important words as accurately as possible is used. Was.

FIG. 8 shows a sync block as an example of conventional transmission data. The block synchronization signal SYNC is located at the beginning of the sync block, the ID signal and the additional code BA are located after that, and the variable-length encoded coefficient data is located after the additional code. Of these coefficient data, the direct current component (DC) with high importance and the low-order alternating current component (AC0-AC)
2) and the coordinate data HV are arranged at a position with a constant interval Tx from the additional code BA. PT is the parity of the error correction code added to each sync block data.
In FIG. 8, the shaded area means the coefficient data of the other alternating current components filled in the extra gap.

FIG. 9 shows an example of the configuration of a framing circuit that realizes such a data array. Coefficient data DT from a DCT converter (not shown) is supplied to the quantization circuit 31 and the estimator 32. The estimator 32 determines a quantization step for making the data amount in a predetermined period equal to or less than the target value Am. Quantization number QNO indicating this quantization step
Are supplied to the memory 33. The quantization number QNO from the memory 33 is supplied to the quantization circuit 31, and the coefficient data DT
Is quantized. This quantization is requantization, and coefficient data whose number of bits is controlled is generated at the output of the quantization circuit 31. The control of the amount of generated data is a process peculiar to the digital VTR, and is necessary for recording data for a predetermined period (for example, one frame) in one track. However, the DC component is important and is not requantized.

The output of the quantization circuit 31 is the area detection circuit 3
4 and the input terminal of the selector SW1. The area detection circuit 34 detects a range in which significant (non-zero) data exists in the quantized (8 × 8) data, and generates coordinate data HV indicating this range. This coordinate data HV is supplied to the memory 39.

The selector SW1 writes the code for the direct current into the memory 38 through the output terminal a, and outputs the output terminal b.
The code for the alternating current is supplied to the variable length coding circuit 35 through. Of the alternating current codes that have been subjected to run length coding, Huffman coding, etc. by the variable length coding circuit 35, the low order ones are supplied to the memory 40, and the other ones are supplied to the FIFO 36. It

Memories 33, 38, 39, 40 and FI
A predetermined write / read address and a memory control signal are supplied to the FO 36, and the read data from the memories 38, 39 and 40 and the FIFO 36 is supplied to the selector SW2.
Of the input terminals a, b, c, d. The output data of the selector SW2 is supplied to the packing circuit 37, and as shown in FIG. 8, data having an additional code and in which highly important data are regularly arranged is output. Although not included in FIG. 8, in the case of the configuration of FIG. 9,
The quantization numbers read from the memory 33 are also regularly arranged as one of the important words.

[0010]

In a digital VTR, during variable speed reproduction in which the speed of the magnetic tape is higher than that during recording, the reproduction track of the head straddles a plurality of tracks and a plurality of tracks are formed. The data is reproduced in pieces from the. Normally, data in which one sync block is reproduced is treated as valid data, and a reproduced image in variable speed reproduction is constructed. During such variable speed reproduction, although the DC data and the low-order data can be obtained by the conventional data array of FIG. 8, the AC data of the block is mostly included in other blocks. I can't get it.
As a result, only a mosaic-shaped reproduced image can be obtained. This problem is more serious when only the DC component is regularly arranged.

Further, as shown in FIG. 9, there is a problem that a buffer memory for regularly arranging important words is required, the circuit scale is large, and the processing becomes complicated. further,
When an error is detected in a variable length code delimiter other than an important word, there is a problem that this error does not fit within one sync block and is propagated from a previous sync block to a later sync block in terms of time.

Therefore, the present invention has a small circuit scale,
It is an object of the present invention to provide a digital image signal transmission device capable of improving image quality during variable speed reproduction by simple control.

Another object of the present invention is to provide a digital image signal transmission apparatus capable of suppressing error propagation within one sync block.

[0014]

According to the present invention, there is provided a digital image signal transmitting apparatus which compresses and encodes an input digital image signal by DCT and transmits the encoded digital image signal. Coefficient data is packed in the bit direction and the predetermined bit width direction in the order from low order to high order of DC and AC, and a sync block sync signal is added for each fixed amount of data. And a means for transmitting data having a predetermined bit width to which a sync block synchronizing signal is added, and a digital image signal transmitting apparatus. Further, according to the present invention, a pointer indicating the byte position and the bit position in the sync block of the DC coefficient data is added, and a sync block synchronization signal is added for each fixed amount of data for transmission. ..

[0015]

The circuit configuration can be simplified because the process of regularly arranging the data of the DC component having high importance is unnecessary. Also,
Since the DC component and the AC component coefficient data are included in the same sync block, the image quality during variable speed reproduction can be improved.
Furthermore, by adding a pointer, error propagation can be suppressed within the sync block.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows the configuration of a framing circuit according to the present invention. Reference numeral 1 is a quantization circuit to which (8 × 8) coefficient data DT generated by a DCT conversion circuit (not shown) is supplied. This coefficient data is also supplied to the estimator 2.

FIG. 2A shows the (8 × 8) structure of the coefficient data DT. The DC component DC has, for example, 9 bits, and the AC component coefficient data AC0 to AC62 each has 10 bits (sign bit + 9 bits). The 64 coefficient data DT in one block, with the DC component DC at the top,
In the zigzag scanning order of AC0, AC1, AC2, ..., They are arranged in order from the lowest order to the highest order. The order of the AC component increases as the distance from the DC component increases. In the coefficient data of this AC component, hatched AC0 to AC7 are treated as low-order AC components.

In the quantization circuit 1, the DC component in the coefficient data DT is not requantized, but the AC component is requantized. This quantizer step is determined by the estimator 2. In the case of a digital VTR, since processing such as editing is performed in frame units, the amount of data generated per frame must be equal to or less than the target value Am. The amount of data generated by DCT and variable length coding is
Since it changes depending on the pattern to be encoded, a process (buffering process) is performed in which the amount of generated data per predetermined period is set to the target value Am or less. Although the buffering process may be performed for each frame, in this example, the buffering is performed in units of 15 macroblocks.

The macroblock has (8
× 8) is a collection of a plurality of blocks of coefficient data.
For example, the component type (Y: U: V = 4: 1:
In the case of 1) video data, four Y blocks, one U block and one V at the same position in one frame.
A total of 6 blocks including blocks form one macroblock. If the sampling frequency is 13.5 MHz, 1
The frame image is (858 samples x 525 lines), and the valid data in it is (704 samples x 480 lines).
Line). In the case of the component method described above, the total number of blocks in one frame is (704 × 6/4)
It is calculated as × 480 ÷ (8 × 8) = 7920. Therefore, 7920/6 = 1320 is the number of macroblocks in one frame.

The estimator 2 can make the amount of generated data in the buffering period equal to or less than the target value, and determines a quantization step having a value as small as possible. As this method, quantization of coefficient data in a plurality of quantization steps (that is, processing of dividing each code of coefficient data by the quantization step) is performed in parallel, and the resulting data amount is monitored,
The quantization step that satisfies the above conditions is alternatively determined. In this case, the common quantization step is not limited to the coefficient data of all orders of alternating current, and a quantization step corresponding to the order may be used. That is, the coefficient data for the alternating current is divided into a plurality of groups according to the order, and the quantization step is prepared for each of the plurality of groups. Then, when different quantization steps are used, a plurality of sets of quantization steps for a plurality of groups are prepared, quantization is performed by the plurality of sets of quantization steps, and the optimum quantization step is obtained by referring to the result. It is determined.

The quantization step determined by the estimator 2 is represented by a quantization number. This quantization number is written in the memory 3. The quantization number from the memory 3 (or the estimator 2) is sent to the subsequent processing and also supplied to the quantization circuit 1. With this quantization circuit 1,
Requantization is performed in the quantization step in which the AC component corresponds to the quantization number. This requantization may be adapted to the order as in the case of determining the quantization step described above.

The output of the quantizing circuit 1 is supplied to the input terminal a of the selector SW and the area detecting circuit 4. The coordinate data HV from the area detection circuit 4 is supplied to the input terminal b of the selector SW. The area detection circuit 4 detects a range in which significant (that is, non-zero) data exists in the code signal from the quantization circuit 1. A block of (8 × 8) is represented by two-dimensional coordinates (H = 0, 1, ... 7, V = 0,
1, 2 ... 7), and as shown in FIG. 2B, the area detection circuit 4 detects the two-dimensional coordinates (H, V) of the significant code existence range.

The selector SW selects the output of the quantizing circuit 1 at the time of code, and selects the output of the area detecting circuit 4 at the timing of inserting the coordinate data HV. The output of the selector SW is supplied to the variable length coding circuit 5. The output of the variable length coding circuit 5 is supplied to the FIFO 6,
The output of 6 is supplied to the packing circuit 7. In the packing circuit 7, as will be described later, an additional code BA including an address, a pointer indicating the position of the DC component, etc. is added to the DCT code signal. The rate of the input data to the FIFO 6 changes due to the variable length code, but the rate of the output data is made constant. The packing circuit 7 sequentially packs the output data of the FIFO 6 and generates data having a predetermined bit width, for example, a byte width.

In or after the packing circuit 7,
Although not shown, a circuit for adding a block synchronization signal and an ID signal is provided to generate print data having a sync block configuration. The recording data is further processed by shuffling, error correction coding, channel coding, etc., and then supplied to a plurality of rotary heads and recorded on a magnetic tape. As an example, two tracks are simultaneously formed by two rotary heads arranged close to each other, and one frame of data is divided and recorded on ten tracks. It should be noted that the PCM audio signal is error correction coded and recorded together with the video data.
Alternatively, it is recorded in an audio data recording section provided in one track.

FIG. 3A shows the structure of the sync block of this embodiment. A 2-byte ID signal is added after the 2-byte block synchronization signal SYNC. The ID signal is
Video data format (NTSC, PAL, HD, S
D), identification of presence / absence of post-recording, and parity for the ID signal. After the ID signal, 4-byte additional codes BA0, BA1, BA2, BA3 are added. In the data area section after this additional code, the code generated in DCT and the coordinate data HV are arranged. Finally, the parity PT is located.

A product code is used as the error correction code, and the Reed-Solomon code is encoded with respect to the data in the horizontal and vertical directions, respectively. The error correction code in the horizontal direction is called an inner code, and the error correction code in the vertical direction is called an outer code. The inner code is applied to the data included in the data area of one sync block, and the horizontal parity PT is generated. There may be sync blocks that include only vertical parity. During variable speed reproduction, the data cut out as a sync block is treated as valid, and error correction using the inner code is performed. Figure 3C
Shows the structure of the error correction code. The data area of one sync block constitutes one row of the two-dimensional array, and the horizontal parity PT is generated. Vertical parity is generated for the data in each column.

In the DCT code signal, the DC component DC is headed, and the significant AC components are packed in the sync block in order from the low order to the high order. The coordinate data HV is
In this example, it is inserted after the DC component. In the example of FIG. 3, the DC component DC0 is located immediately after the additional code BA3, but the position of the DC component DC is variable because the length of the block code is variable. Preferably, the length of the sync block is defined so that the code of at least one block is included in the data area of one sync block. What is important is that a code corresponding to one block of coefficient data exists in a sync block as a group.

Details of the bit configuration of the additional codes BA0 to BA3 are shown in FIG. 3B. The first two bits (TYPE0, TYPE1) 11 of BA0 are used to identify whether the sync block is video data, audio data, vertical parity data, mixed video / audio data, or the like. The specifications of 8 bits of BA1 and 6 bits of BA0 (denoted by BLKN0 to BLKN13) are as follows.

(BLKN3 to BLKN13) 12: 1 addresses of 1320 macroblocks in a frame (BLKN0 to BLKN2) 13: addresses in macroblocks (Y, Y, Y, Y, U, V)

The definition of the bits of BA2 and BA3 is shown below. (QNO0 to QNO4) 14: Quantization number that defines the quantization step (NEBIT0 to NEBIT2) 15: Distance to the next first DC code DC (number of bits) (NEBYT0 to NEBIT6) 16: Next first Distance to DC code DC (number of bytes) (SHUF) 17: Identification of shuffling mode Shuffling is performed in macroblock units within one frame, and a plurality of modes are adaptive as the shuffling pattern. Used selectively.

In the above-mentioned additional code BA, pointers (NEBIT0 to NEBIT2) that define the position of the DC component
15 and (NEBYT0 to NEBIT6) 16 can cut off the propagation of this error (refresh) when the detection of the delimiter of the variable length code is erroneous. In addition, by this pointer, it is possible to
The start position of block data acquisition can be known.

The generation of the above pointer will be described.
FIG. 4 is a timing chart of signals related to pointer generation. The clock CK is synchronized with the code delimiter of the variable length code. The block pulse BLKP is
It is a pulse generated for every 64 codes in one block. The code is data in which 63 alternating current components AC0 to AC62 are arranged in order, starting with the direct current component DC. Here, the maximum bit length of the code is 17 bits, and AC0 to AC62 have effective bit lengths in the range of 0 to 17 bits. A 5-bit length code LEN indicating this effective bit length is transmitted in synchronization with the code.

FIG. 5 is for explaining the generation of the pointer, and the coordinate data HV is omitted for simplification. The data area length in the sync block is represented by D, and the data bit width (byte in this example) is represented by B. The pointer indicates the distance (the number of bytes NBY and the number of bits NBI) from the beginning of the data area to the code of the first DC component.

In the pointer generation circuit shown in FIG.
Is supplied with the length code LEN, and the output of the adder 21 becomes 1
It is supplied to the flip-flop 22 for clock delay, and the output of the flip-flop 22 is fed back to the adder 21. The output of the flip-flop 22 is also supplied to the decoder 24 and the flip-flop 26. The flip-flop 22 is cleared when the output of the NOR gate 23 is "0". The NOR gate 23 has a clear signal IN
The outputs of C and decoder 24 are provided.

The flip-flop 22 outputs the clear signal INC.
The length code LEN is accumulated after being cleared to zero by. This accumulated result is supplied to the decoder 24, and when the accumulated result reaches (D × B), the decoder 24 generates an output, which clears the flip-flop 22. In this way, modulo (D × 8) addition is realized. A pulse N is obtained by inverting the output of the decoder 24.
It is set to XSY. This pulse NXSY is a timing at which the effective data area length D of the sync block is skipped,
That is, it indicates the timing when the value passed to the next sync block.

The block pulse BLKP after the generation of this pulse NXSY indicates the position of the code DC of the first DC component in the sync block. Controller 25
Gives an enable signal to the flip-flop 26 at the timing of the block pulse BLKP after the pulse NXSY. Immediately before the flip-flop 22 is cleared by the output of the decoder 24, the output of the flip-flop 22 is taken into the flip-flop 26 by the enable signal from the controller 25.

FIG. 7 shows the relationship among the block pulse BLKP, the pulse NXSY, and the contents of the flip-flop 22 described above. The content of the flip-flop 22 is (D × B)
Value 27a, 27 from when the pulse NXSY is generated until the block pulse BLKP is first generated.
, b, 27c, ... Show the position of the code for the first DC component of the sync block. Since the adder 21 flip-flop 22 operates in a binary number, the lower 3 bits of the output of the flip-flop 26 indicate NBI, and this is inserted into the sync block as NEBIT0 to NEBIT2 in the additional code, and the higher order. 7 bits indicate NBY, which are inserted in the sync block as additional codes NEBY0 to NEBY6.

The present invention is not limited to the digital VTR, but can be applied to a disk recording / reproducing apparatus, a case of transmitting a digital image signal through a communication path, and the like.

[0039]

According to the present invention, since one block of coefficient data and the corresponding code are collectively arranged in the sync block, the framing circuit and processing are simple, and the required memory capacity is reduced. it can. Further, at the time of variable speed reproduction, since the reproduced sync block data includes both the direct current component and the alternating current component, the quality of the reproduced image can be improved. Further, according to the present invention, since the pointer indicating the position of the direct current component is added to each sync block, even if the detection of the delimiter of the variable length code is incorrect, the pointer can be used for refreshing and error propagation can be prevented. Can be kept to a minimum.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration for framing in an embodiment of the present invention.

FIG. 2 is a schematic diagram for explaining coefficient data generated by DCT.

FIG. 3 is a schematic diagram for explaining an arrangement of sync blocks of transmission data, a configuration of additional codes, and an error correction code.

FIG. 4 is a timing chart for explaining pointer generation.

FIG. 5 is a schematic diagram for explaining a pointer.

FIG. 6 is a block diagram of an example of a pointer generation circuit.

FIG. 7 is a timing chart for explaining the operation of the pointer generation circuit.

FIG. 8 is a schematic diagram of an example of a conventional data array.

FIG. 9 is a block diagram of a conventional framing circuit.

[Explanation of symbols]

 1 Quantization circuit 2 Estimator of generated data amount 5 Variable length coding circuit 7 Packing circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H04N 7/133 Z 4228-5C

Claims (2)

[Claims] 1. A digital image signal transmitting apparatus, wherein an input digital image signal is compression-encoded by DCT and the encoded digital image signal is transmitted, wherein coefficient data generated by the encoding is DC component, Means for sequentially packing in the bit direction and in the predetermined bit width direction in the order from the low order to the high order of the alternating current component, and adding a sync block synchronization signal for each fixed amount of data, And a means for transmitting the data of the predetermined bit width to which a sync block synchronizing signal is added. 2. A digital image signal transmitting apparatus, wherein an input digital image signal is compression-encoded by DCT and the encoded digital image signal is transmitted, wherein coefficient data generated by the encoding is DC component, In the order from the low-order AC component to the high-order component, the bits are sequentially packed in the bit direction and the predetermined bit width direction, and the byte position and the bit position in the sync block of the DC component coefficient data are indicated. A means for adding a pointer and further for adding a sync block sync signal for each fixed amount of data, and a means for transmitting the data of the predetermined bit width to which the sync block sync signal is added A digital image signal transmission device characterized by the above.