JPH05168039A - Recording encode method for high fidelity television signal - Google Patents

Abstract

PURPOSE:To encode a unit signal (TDM signal) for recording from a high fidelity television signal by controlling reading of plural output ports while using a serial access memory equipped with the plural output ports. CONSTITUTION:Memories 146A and 146B are serial access and two output ports are respectively provided in each memory. Then, write of input data VA and VB is controlled by memory controllers 147A and 147B, and reading of data from the respective output ports is independently controlled. Namely, TDM signals are written in memories 146A and 146B in the order of a luminance signal and a chrominance signal. In the case of reading, the same data are read from two output ports while deviating read timing, color difference signal data are extracted from the preceding output port, luminance signal data are extracted from the other output port, both data are synthesized and therefore, the required TDM signals are obtained.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a TD for recording when recording a high-definition signal on a consumer VTR.
The present invention relates to a method of encoding an M (TIME DIVISION MATRIX) signal.

[0002]

2. Description of the Related Art In a VTR that records and reproduces a high-definition (high-definition television) signal in a wide band and a high frequency band, a signal of a unit time, for example, one frame, is used in order to lower the frequency of the recording signal and narrow the frequency band. Is used for recording by dividing it into a plurality of segments and a plurality of channels.

That is, a high-definition signal is a signal having 1125 horizontal scanning lines per 30 Hz in one frame. In the recording system of the VTR, the high-definition signal includes a luminance signal Y, a blue color difference signal PB and It is input as a baseband signal including a component signal of the red color difference signal PR. Then, the input luminance signal and color difference signal are once A / D converted into digital signals and subjected to time-axis processing and color signal line sequential processing.

Then, the signal is divided into two channels, A and B, and a synchronization signal SYNC, a burst signal SB, etc., a color signal C, and a luminance signal Y are time-divided for each channel, as shown in FIG. TDM (TIME D
IVISION MATRIX) signal is converted into a continuous recording signal of a unit period H ^* . Then, this recording signal is returned to an analog signal, FM-modulated, and recorded on the magnetic tape by the rotary head.

Here, the unit period 1H ^* is set to have a time length which is almost twice as long as one horizontal period of the original high-definition signal by dividing the two channels, and the luminance of one line with the same line number is included in this 1H ^*. The signal and the color signal are time-division multiplexed.

[0006] Then, the high-definition signal of each one frame is converted into the above-mentioned TDM signal as shown in FIG.
As shown in FIG. 10, the rotary head device as shown in FIG.
1 and TA2 and B channel tracks TB1 and TB2
Are alternately formed and recorded as a total of 8 tracks on the magnetic tape.

The rotary head device in the example of FIG. 11 is constructed as follows.

That is, an A channel head 1A having a first azimuth angle and a B channel head 1B having a second azimuth angle different from the first azimuth angle are
1 at the same rotation angle position of the rotary drum 3 in the direction of its rotation axis
It is attached by being offset by the track width. Similarly, the A channel head 2A having the first azimuth angle and the B channel head 2B having the second azimuth angle rotate the rotary drum 3 at a rotation angle position different by 180 ° from the heads 1A and 1B. It is attached by being offset by one track width in the axial direction.

Then, the magnetic tape 4 is obliquely wound around the drum 3 over an angular range of 180 ° + α, and the rotary heads 1A, 1B, 2A and 2B are rotated at a rotational speed of 60 Hz.

On the magnetic tape 4, the rotary heads 1A and 1B and the rotary heads 2A and 2B are alternately arranged in the tape contact sections corresponding to the respective rotation angles of about 180 °.
As shown in FIG. 10, eight diagonal recording tracks are formed per frame to record a high-definition signal.

That is, in one rotation, the rotary head 1A
And 1B contact the tape 4 in the first half of the 180 ° rotation section, the rotary heads 1A and 1B drive the A channel track TA1 and the B channel track TB1.
And the rotary heads 2A and 2B are in contact with the tape 4 in the latter half about 180 ° rotation section.
A channel tracks TA2 and B by A and 2B
The channel tracks TB2 are formed at the same time, and thereafter, this is alternately repeated.

In this case, two rotary heads 1A, 1B,
Alternatively, one segment is composed of two tracks which are simultaneously formed by the rotary heads 2A and 2B, and a video signal for a half field and an audio signal for a half field period related to this video signal are formed in the one segment. To P
The CM-converted signal is recorded in separate recording areas. And 4 tracks TA1, TB1, TA2, TB
2 fields for 1 field, 4 segment SEG1, SEG2,
A video signal and an audio signal of a high-definition signal for one frame are recorded by SEG3 and SEG4.

Then, as shown in FIG. 10, the control signal CTL is recorded at a rate of one per frame on the longitudinal track at the end portion in the width direction of the tape 4, and is used for tracking servo during reproduction. To be done.

FIG. 12 is a block diagram of an example of a recording / reproducing system of a high definition VTR equipped with the rotary head device of FIG.

That is, in the recording system, as shown in FIG. 12, the luminance signal Y of the high-definition signals input through the input terminal 11Y is the low-pass filter 12Y.
Is supplied to the A / D converter 13Y through the A / D converter 13Y, is A / D converted at a sampling frequency f _YCK = 44.55 MHz to be a digital signal, and is supplied to the digital signal processing circuit 14.

Further, the blue color difference signal PB and the red color difference signal PR of the high-definition signal input through the input terminals 11B and 11R are low pass filters 12B and 12R.
Are supplied to the A / D converters 13B and 13R respectively, and at a sampling frequency f _CCK = 11.1375 MHz which is ¼ of the sampling frequency of the video signal.
The signals are D / D converted, converted into digital signals, and supplied to the digital signal processing circuits 34, respectively.

The digital signal processing circuit 14 is provided with a vertical filter for line-sequential processing of color difference signals and a frame memory, and a clock frequency f _TCK = 30.753 MH that is phase locked to the sampling clock of the luminance signal.
Digital signal processing such as time-axis processing and color-difference signal line-sequential processing is performed by the clock of z.
Encoded in the signal. The digital signal processing circuit 14 also performs so-called shuffling processing for rearranging the TDM signal with the original signal according to a predetermined rule.

Further, the digital signal processing circuit 14 is supplied with a reference signal REF of one frame period (33.3 msec) from the terminal 5, and the TDM signal for one frame is synchronized with this reference signal REF from the frame memory. Read out. In this case, the read TDM signal is
It is divided into two channels, A and B. Although not shown, the reference signal REF is recorded as a control signal by a fixed magnetic head at the end of the tape 4 in the width direction.

Then, in the case of this example, the TDM signal is configured in detail as the TDM waveform shown in FIG. That is, the TDM signal is the luminance signal data Y for one line of 1152 samples and the color difference signal data C, 21 of blue or red of 288 samples of the same line as the luminance signal.
Synchronization signal SYNC for samples, burst signal SB for 30 samples, ID data ID1 for 3 samples each,
Including ID2, the total is 1530 samples.
The blanking period of the TDM signal including the synchronization signal SYNC and the burst signal SB is 88 samples. The ID data ID1 and ID2 are segment identification signals (segment I
D), and with 2-bit data ID1 and ID2,
Segment numbers 1 to 4 are represented.

The two-channel data of A and B from the digital signal processing circuit 14 are supplied to the D / A converters 15A and 15B for D / A conversion, and the D / A converters 15A and 15B output the data shown in FIG. As shown in FIG. 13, a TDM waveform signal including ID data ID1 and ID2 as segment identification signals, a color signal C, and a luminance signal Y, such as a synchronization signal SYNC and a burst signal SB, is obtained.

This signal is supplied to the low-pass filter 1 respectively.
Emphasis circuits 17A, 17 through 6A and 16B
B is supplied to B for pre-emphasis processing. Then, the outputs of the emphasis circuits 17A and 17B are supplied to the modulation circuits 18A and 18B and are FM-modulated. Then, the FM-modulated A channel data is supplied to the A channel rotary heads 1A and 2A,
The FM-modulated B-channel data is supplied to the B-channel rotary heads 1B and 2B and recorded on the tape 4 as 4 segments (composed of 8 diagonal tracks) per frame as described above. To be done.

FIG. 14 shows the data content of the recording pattern on the tape formed at this time, particularly in the area of the video signal. In this example, ^{H *} number per track, for example 167.5H ^* (at 1 frame 8 track, 1340H ^*) is a, the video signal area is set to 139h ^* of them. Although not shown, audio data and others are recorded in the remaining areas of each track.

The first 3H in the area of this video signal
^* Is the preamble area of the video signal, followed by 1
36H ^* is a video signal recording area VA. Figure 4
At the H ^* unit of the video signal recording area VA
The numerical value given to the luminance signal data in the DM data is the line number of the original high-definition signal. T for each 1H ^*
Since the color difference signal data and the luminance signal data multiplexed as the DM signal are of the same line, the line numbers are omitted.

In the example of the figure, the recording area of 1040H ^* surrounded by a thick line is the number of effective video lines per frame of the high-definition signal (the number of lines excluding the vertical blanking period, that is, the 41st line of one frame to Total 10 of the 557th line and the 603rd line to the 1120th line
35 lines). In the example shown in the figure, the horizontal line section required for various test signals in the vertical blanking period may be considered to be 1080 lines. A region corresponding to 1080H ^* is provided.

In the preamble area, a CW signal (PLL synchronizing continuous wave signal), a segment synchronizing signal V,
A reference level signal L for applying AGC during reproduction, a ramp signal R for linearity correction, and the like are recorded.

Next, the reproducing system of the high definition VTR of this example will be described. At the time of this reproduction, although not shown, a reproduction control signal C from a fixed magnetic head
The TL and the reference signal REF are phase-compared, and tracking control is performed so that the rotary head correctly scans the recording track based on the phase comparison output and the envelope output of the reproduced video signal. At this time,
The segment identification signal in the reproduced TDM signal is used to enable synchronization in frame units.

In the reproducing system, the reproduced signals from the rotary heads 1A and 2A of the A channel are supplied to the FM demodulation circuit 22A via the reproduction amplifier 21A and FM demodulated, and B
The reproduction signals from the rotary heads 11B and 2B of the channel are supplied to the FM demodulation circuit 22B via the reproduction amplifier 21B and FM demodulated. Then, these FM demodulation circuits 2
The output signals of 2A and 22B are supplied to the de-emphasis circuits 23A and 23B, respectively, and subjected to de-emphasis processing.

This de-emphasis circuit 23A and 2
The output signal of 3B is supplied to the A / D converters 25A and 25B via the low-pass filters 24A and 24B, respectively, converted into a digital signal, and then supplied to the digital signal processing circuit 26 including a frame memory.

In the digital signal processing circuit 26, the TDM signals rearranged at the time of recording are returned to the original order by the de-shuffling process, the TDM signal is converted into the luminance signal, and the color difference signals of blue and red. Processing for synchronizing the blue and red color difference signals is performed. The digital signal processing circuit 26 is supplied with the reference signal REF of the frame cycle from the terminal 5. This reference signal REF
Are synchronized with the reproduction data in frame units by the above-mentioned tracking servo. From the frame memory of the digital signal processing circuit 26, the data of the luminance signal and the color difference signal are read in synchronization with the reference signal REF.

Then, the luminance signal from the digital signal processing circuit 26 is returned to the original analog signal through the D / A converter 27Y and the low pass filter 28Y and is led to the output terminal 29Y. Further, the blue and red color difference signals from the digital signal processing circuit 26 are supplied to the D / A converter 2
7B, 27R and low-pass filters 28B and 28R to restore the original analog signals, which are output to output terminals 29B and 29R, respectively.

By the way, in general, most of the large-capacity, high-speed memories such as field memories and frame memories for processing video data are serial-access memory called FIFO, which writes video data from an arbitrary address, and Unable to read. For this reason, the digital signal processing circuit 14 for performing TDM encoding of the recording system of the high-definition VTR needs to be configured as shown in FIG.

That is, in FIG. 15, 141A is A
A channel frame memory 141B is a B channel frame memory, each of which is a serial access memory.

Then, the A / D converters 13B and 13
The blue and red color difference signals PB and PR (FIGS. 16B and C) converted into digital signals from R are supplied to the vertical filter 14
2 and is subjected to line-sequential processing, and a line-sequential signal PBR (FIG. 16E) is obtained from the vertical filter 142.
The line-sequentialization signal PBR is supplied to the other input terminal b of the switch circuit 143 for dividing into two channels A and B.

The vertical filter 142 is provided with a delay circuit of 1H (H is a horizontal period). Therefore, the line-sequential signal PBR is the original color difference signal PB, as is apparent from FIGS. 16B, 16C and 16E. , PR is delayed by 1H. Further, as shown in FIGS. 9 and 14 described above, T
In the DM signal, the color difference signal is time-division multiplexed in time before the luminance signal. Since the frame memories 141A and 141B are serially accessed, it is necessary to write data in the order that matches the TDM signal at the time of writing, but for that purpose, the luminance signal Y needs to be delayed by 2H.

Therefore, the luminance signal Y (FIG. 16A) converted into a digital signal by the A / D converter 13Y is 2
After being delayed for 2H by the H delay circuit 144, one input end a of the switch circuit 143 is supplied.

The switch circuit 143 is alternately switched to the one input end a side and the other input end b every 1H period by the switching signal SW from the terminal 145. By this switching, from one output end of the switch circuit 143, as shown in FIG. 16F, PB1, Y1, PB3,
.., and a blue color difference signal and a luminance signal of the odd-numbered lines are alternately provided, and a signal Va of the A channel is obtained, and from the other output end of the switch circuit 143, FIG.
As shown in G, PR2, Y2, PR4, Y4, ...
A B-channel signal Vb in which the red color difference signal and the luminance signal of the even-numbered lines are alternately arranged is obtained.

Then, the A channel signal Va is supplied to and written in the frame memory 141A, and the B channel signal Vb is supplied to and written in the frame memory 141B. At this time, the color difference signal is 1 / the luminance signal.
The writing rate is 4.

From the frame memory 141A,
Shuffling causes the TDM to be in the order shown in FIG. 17A.
The signal is read out and the A channel track T is recorded on the tape 4.
It is recorded as A1 and TA2. Also, from the frame memory 141B, similarly, as shown in FIG.
The TDM signals are read out in the order shown in, and the tape 4
Are recorded as B channel tracks TB1 and TB2. In this case, as shown in FIGS. 17C and 17D, the shuffling has lines 1, 2 in segment SEG1, line 3,
4 is performed in segment SEG2, and so on. The line numbers in FIGS. 16 and 17 are for explanation purposes, and are different from the line numbers of the tape pattern shown in FIG.

[0039]

As mentioned above, TD
A high-speed memory used as a frame memory for M encoding is a serial access memory called a FIFO, and therefore, in order to make the color difference signal precede the luminance signal to form the TDM signal, the luminance signal Y 2H
The delay circuit 144 had to delay by two lines.

Therefore, the delay circuit 1 for two lines is conventionally used.
44 is additionally required in addition to the frame memories 141A and 141B, which requires extra space, consumes much power, and is high in cost.

In view of the above points, it is an object of the present invention to provide a method capable of encoding a TDM signal by using only a serial access frame memory (or field memory) without requiring the 2H delay circuit described above. To do.

[0042]

In order to solve the above-mentioned problems, this invention proposes two invention methods. The method of claim 1 corresponds to the reference numerals of the embodiments described later, and The color difference signal is line-sequentialized from the high-definition signal input as the component signal of the signal and the color difference signal, and then the memories 146A and 146B are used to output the luminance signal and the color difference signal of the same line number and the color difference signal to the luminance signal. An encoding method for forming time-division multiplexed recording unit signals for a plurality of channels in a state in which the memory 146A and 146B is a serial access memory and has a plurality of output ports. The recording unit signals are written in the memories 146A and 146B in the order of the luminance signal and the color difference signal. When reading from 46B, to obtain a luminance signal and color difference signals from a separate output port, by joining them, so as to obtain a recording unit signal.

The method of claim 2 is the memory 14
6A and 146B are serial accesses, have a plurality of output ports, can specify a write address for each of a plurality of samples, and can perform reading in a unit of the plurality of samples.
By controlling the write addresses of A and 146B, the color difference signal and the luminance signal are sequentially written in the memories 146A and 146B as recording unit signals, and two output ports 1 and 2 are output from the memories 146A and 146B. The recording unit signals are sequentially read from the output ports 1 and 2, but the read sections of the output ports 1 and 2 are partially overlapped, and the output of one port is changed to the output of the other port at an appropriate point in the overlap period. The output of the recording unit signal is switched so that the time of the joint of the recording unit signals is adjusted.

[0044]

In the method of the present invention, since the luminance signal is supplied to the memory without being delayed, the luminance signal precedes the color difference signal in the input data of the memory.

In the case of the method of the first aspect of the present invention, the data is written in the memory in the same order. The memory has a plurality of output ports and can read data independently. According to the first aspect of the present invention, the same data is read from the two output ports by shifting the read timing. For example, the same data is read out by shifting by 1H ^* .

Then, the color difference signal data is extracted from one output port preceded by the data, the luminance signal data is extracted from the other output port, and the two are combined to obtain the required TDM signal. is there.

Further, in the case of the method of the invention of claim 2,
The memory is a serial access, has a plurality of output ports, can specify a write address for each of a plurality of samples, and can perform the reading in a unit of the plurality of samples. Therefore, the write address is controlled to write the data in the memory with the color difference signal preceding the luminance signal.

Therefore, if this is read from the memory, the data in the order matching the TDM signal can be obtained. However, since the memory can only write and read data for every plural samples, the joint of data in 1H ^* unit, that is, the blanking period of the TDM signal is TDM.
Often does not meet the signal standard.

According to the present invention, as the read output of the memory, the output of the port 1 and the output of the port 2 are alternately obtained every 1H ^* , and the output is read so that the outputs partially overlap at the joint between the ports. To control. Then, by controlling the overlap period, TD
A read data output conforming to the M signal standard can be obtained.

[0050]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the recording / encoding method according to the present invention will be described below with reference to the drawings by exemplifying a case where it is applied to the above-mentioned high definition VTR of FIG.

FIG. 1 is a block diagram of a digital signal processing circuit 14 for carrying out an embodiment of the recording / encoding method according to the present invention. That is, the digital brightness data DY (FIG. 2A) from the A / D converter 13Y is supplied to the one input end a of the switch circuit 143 without delay. Then, the line-sequential color difference signal data PBR (FIG. 2B) from the vertical filter 142 is supplied to the other input terminal b of the switch circuit 143 as in the above-described example.

As described above, the switch circuit 143 is alternately switched to the one input terminal and the other input terminal every 1H by the switching signal SW from the terminal 145. As the data VA of the A channel from the switch circuit 143, the data of the odd-numbered line is obtained as shown in FIG. 2C, but since the luminance signal Y is not delayed, the data of the same line number is the luminance signal. Is obtained prior to the color difference signal data, and does not match the data order of the TDM signal.

Similarly, as the data VB of the B channel of the switch circuit 143, as shown in FIG. 2D, the data of even-numbered lines and the data of the same line number are
The luminance signal is obtained prior to the color difference signal data, and does not match the data order of the TDM signal.

The A channel data VA and the B channel data VB from the switch circuit 143 are supplied to the A channel and B channel video frame memories 146A and 146B, respectively.

In the present invention, the A and B channel video frame memories 146A are provided.
As 146B, a frame memory having a plurality of output ports, in this example, two output ports, an output port 1 and an output port 2, is used. Memory controllers 147A and 147B are provided for the frame memories 146A and 146B. The memory controllers 147A and 147B serve as input data VA and VB to the frame memories 146A and 146B, respectively.
Control is performed, and the reading of data from the output port 1 and the output port 2 is controlled independently.

In this case, the frame memory 146
The read output data from A and 146B are combined data of the data obtained at the two output ports 1 and 2, respectively.

In the present invention, as a method for encoding a TDM signal by changing the writing and reading methods for the frame memories 146A and 146B by the memory controllers 147A and 147B, two methods will be described below. Suggest an example. The main characteristics of the memories 146A and 146B used in this example are as follows.

The write side port is 1 port, while the read side port is 2 ports (output port 1 and output port 2), and these 3 ports are also asynchronous with each other.

Basically, serial access is performed, but random access can be performed only in writing in units of 60 samples (this is called a block) in the row direction. Also,
Random access can be performed both in writing and reading in the column direction only in the direction of increasing the line number.

Both writing and reading can be performed only in block units (60 sample units).

{960 samples (= 60 samples ×
16 blocks) / line} × 360 lines.

[First Method] Referring to FIGS. 3 and 4, writing by the first method, and referring to FIG.
Reading by the method will be described.

In the first method, the luminance signal data and the color difference signal data are written in the order of the data shown in FIGS. 2C and 2D, and the TDM signal is encoded by using the two output ports. Is the way to do so.

That is, FIG. 3 shows a time chart for writing data by the first method, which is an example in the case of writing the data VA of the A channel to the memory 146A. Memory 14 for B channel data VB
Since writing to 6B can be performed in exactly the same manner, the description thereof will be omitted.

Further, in the case of this example, the memories 146A and 146B are provided for two phases, and each phase is assigned to each sample for parallel processing. Therefore, as shown in FIG. 3A, the number of samples that is half the number of samples of the TDM signal shown in FIG. 13 is handled as one phase.

The examples described below are all about one phase. As is clear from FIG. 13, the number of data samples for one phase handled as a TDM signal is 576 samples for luminance signal data and 144 samples for color difference signal data. Then, the interval between the color difference signal data and the luminance signal data is 3 samples, and the blanking period as the TDM signal which is a section before the color difference signal data is 42 samples.

[Description of Writing] Next, writing by the first method will be described. That is, the data VA (FIG. 3A) input to the frame memory 146A receives the sample clock (sampling frequency f of the luminance signal during the high level period of the write enable signal WEN (FIG. 3B).
Writing is performed by _YCK = 44.55 MHz).

In this case, the write address is a serial address, but for the color difference signal data, as shown in FIG. 3B, the memory 146A is set to the write enable state only every one sample period every three samples. Then, the color difference signal data is written in a time-compressed state as shown in FIG.

FIG. 3C shows a write vertical reset signal WVRS. When this is supplied to the frame memory 146A, the line address is reset to 0 and writing is started. Further, FIG. 3D shows a write horizontal reset signal WHRS. When this is supplied to the frame memory 146B, the sample address in the line direction is reset to 0. Further, FIG. 3E shows the write line increment signal WHJP, one pulse of which is the memory 146A.
The line address is incremented by one each time it is supplied to the.

By supplying the respective signals to the frame memory 146A at the timings shown in FIG. 3, the luminance signal data and the color difference signal data are written in the frame memory 146A as shown in FIG. Here, the number of data is 576 + 144 = 720, which is exactly divisible by a block of 60 samples, and at each line address, the luminance signal data of a certain line and the color difference signal data of the same line from the 0th block to the 11th block. It is just packed and written in.

[Description of Reading] Next, reading in the case of the first method will be described. in this case,
The two output ports, port 1 and port 2, are controlled as shown in FIG.

First, the read control for port 1 will be described. That is, when the read vertical reset signal RVRS1 (FIG. 5A) is supplied to the memory 146A, the line address is reset to 0 and reading is started. Then, the read horizontal reset signal R
HRS1 (FIG. 5B) is a pulse of 1H ^* period,
Each time a pulse is supplied to the memory 146A, the sample address in the line direction is reset to 0.

The read line increment signal RHJP1 (FIG. 5C) is the read horizontal reset signal R.
It occurs 1H ^* after the HRS1 is supplied and immediately before the next read horizontal reset signal RHRS1 is generated.
The line address jumps by one line for each pulse. In the case of this example, in order to divide the data for one field into two segments, two lines are jumped for each 1H ^* .

Read clock enable signal RCEN
1 (FIG. 5D) makes it possible to supply the read clock to the frame memory 146A only during the high level period. First, the read horizontal reset signal RH
From RS1 (FIG. 5B), the level becomes high level for 576 sample periods, and the luminance signal data is read. Then, in the next 42 sample periods, the read clock is stopped at the low level, and the horizontal blanking period of the TDM signal is formed. After that, the 144 sample interval becomes high level, and the color difference signal data is read. Then, in the next three sample sections, the read clock is stopped at the low level, and the section between the color difference signal data and the luminance signal data is formed. This is the end of the 1H ^* period, and this is repeated thereafter.

Regarding the port 2, the read vertical reset signal RVRS2 (FIG. 3F), the read horizontal reset signal RHRS2 (FIG. 3G), and the read horizontal increment signal RHJP2 (FIG. 3H) are as shown in the figure. The signal is delayed by 1H ^* period from them. Further, the read clock enable signal RCEN2 (FIG. 3I) is set to be exactly the same as that of the port 1.

Therefore, although it is possible to obtain the luminance signal data and the color difference signal data from the output port 1 at the timing shown in FIG. 3K, the output enable signal OPEN1 (FIG. 3E) of the output port 1 causes the output port 1 to output. 1 is capable of outputting data only in the 144-sample section of the color difference signal data. Actually, the output PO of the output port 1
As T1, the luminance signal data shown by hatching in FIG. 3K cannot be obtained, and the color difference signal data PB1, PB5, PB are obtained.
Only 9, ... Can be obtained.

Further, as shown in FIG. 3L, it is possible to obtain the same luminance signal data and color difference signal data from the output port 2 at a timing delayed by 1H ^{* with} respect to the port 1, but the output of the output port 2 Enable signal OPEN2
(FIG. 3J), the output port 2 is allowed to output data only in the 576 sample sections of the luminance signal data. Actually, the output POT2 of the output port 2 is the color difference shown by hatching in FIG. 3L. No signal data is obtained, but only luminance signal data Y1, Y5, Y9, ... Is obtained.

Therefore, as the read output data from the frame memory 146A, the output POT1 consisting only of the color difference signal data PB1, PB5, PB9, ... From the output port 1 and the luminance signal data Y from the output port 2 are output.
An output MOUT (FIG. 3M) is obtained by combining the output POT2 composed of only 1, Y5, Y9, .... It goes without saying that the output data MOUT is compatible with the format of the TDM signal shown in FIG.

[Second Method] Next, writing by the second method will be described with reference to FIGS. 6 and 7, and reading by the second method will be described with reference to FIG.

This second method takes advantage of the fact that writing can be done randomly in block units (60 samples).

That is, FIG. 6 shows a time chart for writing data by the second method, which is an example of writing A channel data VA to the memory 146A. Since the data VB of the B channel can be written in the memory 146B in exactly the same manner,
The explanation is omitted. Also in the case of this example,
Both the memories 146A and 146B are provided for two phases, and each phase is assigned to each sample and processed in parallel. Similar to the above-described example, all the examples described below are for one phase.

[Description of Writing] Writing by the second method will be described below. In this case, as in the case of the first method, the write enable signal WEN (FIG. 6B), the write vertical reset signal WVRS (FIG. 6C), and the write horizontal reset signal RHRS (FIG. 6D) are stored in the frame memory 146A. , The write line increment signal WHJP (FIG. 6F) is supplied, but unlike the first method, the write horizontal reset signal WHRS is 1H.
For each of the luminance signal data and the color difference signal data,
One pulse stands.

Then, the write start block address is designated in synchronization with the write horizontal reset signal WHRS for every 1H as shown in FIG. 6E. That is, the third (0011) block is designated as the write start address for the luminance signal data, and the 0th (0000) block is designated as the write start address for the color difference signal data. The write line increment signal WHJP has one pulse every 1H ^* period (about 2H), as in the case of the first method.

Therefore, the luminance signal data of the data VA (FIG. 6A) input to the frame memory 146A is written from the third block of the line direction address of the memory 146A, and the color difference signal data is stored in the memory 146.
Writing is performed from the 0th block (first block address) of the address in the line direction of A.

At this time, the write enable signal WEN
Sample clock of the luminance signal in the high level period of (FIG. 6B) (sampling frequency f _YCK = 44.55 MHz)
However, in the case of this second method, as shown in FIG. 6B, since there are 3 samples between the color difference signal data and the luminance signal data, 3 samples before the luminance signal data. Provide a blank period. And
The luminance signal data is written in the memory 146A from the fourth clock.

When writing is carried out in this way, it is possible to write 5 from the 3rd block to the 12th block of the address in the line direction.
Luminance signal data of 76 samples is written, and 21 samples at the end of the 12th block are left. Therefore, as shown in FIG. 6B, the write enable signal WEN is
It is at a high level for 21 samples longer than the end of the luminance signal data, and these 21 samples are in the memory 146.
A is blank.

In the case of this second method, the 0th
From the block to the second block, 144 samples of color difference signal data are written so as to be exactly packed. For this reason,
As shown in FIG. 6B, the write enable signal WEN
Of 180-144 = 36 samples can be additionally written to the color difference signal data, and the 36 samples are blankly written.

The write control signal as described above is applied to the memory 1
By supplying the data to the memory 46A, the color difference signal data of a certain line can be written in the memory 146A in advance of the luminance signal data of the same line at each line address, as shown in FIG.

[Description of Reading] Next, reading in the case of the second method will be described with reference to FIG. In this case, when the data written in the frame memory as shown in FIG. 7 is serially read as it is, 21 samples of blank writing data at the end of the luminance signal data and 36 samples of blank writing data at the beginning of the color difference signal data are read. And 57 samples, which does not match 42 samples of the blanking period of the TDM signal. Therefore, in the second method, the two output ports 1 and 2 are used so that the blanking period has a length of 42 samples as follows.

First, a pulse is output as the read reset signal RVRS1 (FIG. 8A) for the port 1, and reading can be started. At the same time, a pulse is generated as the first read horizontal reset signal RHRS1 (FIG. 9B), the sample address in the line direction is reset to 0, and the color difference signal data PB from the 0th block of the 0th line is reset.
1 and the reading of the luminance signal data Y1 are started (see FIG. 8E).
reference).

Next, at the time point 15 samples before the last data (21-sample portion of blank writing) of the data of the 0th line from the port 1, the read vertical reset signal RVRS2 (FIG. 8G) for the port 2 is read. ), The pulse rises, and the read start possible state for port 2 is set. This read vertical reset signal RVR
Before S2 rises, two pulses are generated as the read line increment signal RHJP2 (FIG. 8I), and the read line address at the port 2 at this time is the second line.

Then, the read vertical reset signal RVR
First read horizontal reset signal RHR in synchronization with S2
A pulse is generated as S2 (FIG. 8H), the sample address in the line direction is reset to 0, and the color difference signal data PB5 and the luminance signal data Y from the 0th block of the second line.
5 is read (see FIG. 8F).

Port 2 read vertical reset signal RV
Since the pulse as RS2 is generated by overlapping the read data of port 1 by 15 samples,
The end portion of the read data of port 1 and the start portion of the read data of port 2 overlap each other for a period of 15 samples. Due to this overlap period,
The period from the end of the luminance data from the port 1 to the beginning color difference signal data of the port 2 is 36 + 21-15 = 4.
This corresponds to 2 samples, which matches the blanking period of the TDM signal.

Next, at the time point 15 samples before the last data (21-sample portion of blank writing) of the data of the second line from the port 2, the read horizontal reset signal RHRS1 for the port 1 (see FIG. 8B). ), The pulse rises again and the read line address for port 1 is reset to zero.

This read horizontal reset signal RVRS1
4 pulses are generated as the read line increment signal RHJP1 (FIG. 8C) before rising, and the read line address at the output port 1 at this time is the 4th line, and the color difference from the 0th block of the 4th line. The reading of the signal data PB9 and the luminance signal data Y9 starts (see FIG. 8E).

As described above, the end portion of the read data of the port 2 and the start portion of the read data of the port 1 overlap each other for a period of 15 samples. Therefore, the period from the end of the luminance data from the port 2 to the beginning color difference signal data of the port 1 is 42 samples, which matches the horizontal blanking period of the TDM signal.

Similarly, the read data of the port 1 and the read data of the port 2 are read at the beginning and the end thereof in a state of overlapping for a period of 15 samples.

In this case, also for port 2, the read line increment signal RHJP2 (FIG. 8I) has four pulses so that the line address jumps by four lines from the second read horizontal reset signal RHRS2. It occurs similarly to 1.

Since there is an overlap period,
After reading the data from one line address from the port 1 or port 2, the read clock is stopped by 30 clocks until the start of reading the data of the next line address.

Then, the output port 1 becomes capable of outputting data by the read output enable signal OPEN1 (FIG. 8D) in the period of only the color difference signal data and the luminance signal data excluding the blank portion of the read data. , Output port 2 also has read output enable signal OP
By EN2 (FIG. 8J), data can be output during the period of only the color difference signal data and the luminance signal data, excluding the blank portion of the read data. Therefore, memory 1
As the output data of 46A, as shown in FIG. 8K, the target TDM signal is obtained.

Although the frame memory is used as the video memory in the above example, it may be a field memory.

[0102]

As described above, according to the present invention, a serial access memory having a plurality of output ports is used as a video memory, and by controlling the reading of the plurality of output ports, the other It is possible to encode a recording signal, that is, a TDM signal from a high-definition signal without providing a separate memory in. Therefore, the delay circuit for the 2H period, which is required in the past, is not required, which simplifies the configuration and helps reduce the cost.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a main part of a high-definition VTR for executing a method according to the present invention.

FIG. 2 is a time chart for explaining the operation of FIG.

FIG. 3 is a time chart for explaining a memory writing method of an embodiment of the first method according to the present invention.

FIG. 4 is a diagram showing data contents of a memory in which data is written by the method of FIG.

FIG. 5 is a time chart for explaining a memory reading method according to an embodiment of the first method of the present invention.

FIG. 6 is a time chart for explaining a memory writing method of an embodiment of a second method according to the present invention.

7 is a diagram showing data contents of a memory in which data is written by the method of FIG.

FIG. 8 is a time chart for explaining a memory reading method according to an embodiment of the second method of the present invention.

FIG. 9 is a diagram for explaining a recording TDM signal of a high-definition signal.

FIG. 10 is a diagram showing a tape pattern recorded by a high-definition VTR.

FIG. 11 is a diagram showing an example of a rotary head device used in a high-definition VTR.

FIG. 12 is a block diagram of an embodiment of a recording / reproducing system of a high definition VTR.

FIG. 13 is a diagram showing an example of a detailed format of a TDM signal.

FIG. 14 is a diagram for explaining a video data recording area of a tape pattern.

FIG. 15 is a block diagram for explaining a main part of a conventional recording encoding method.

FIG. 16 is a time chart for explaining a conventional recording encoding method.

FIG. 17 is a diagram for explaining recorded data of a high-definition signal.

[Description of symbols] 11Y luminance signal input terminal 11B blue color difference signal input terminal 11R red color difference signal input terminal 13Y luminance signal A / D converter 13B blue color difference signal A / D converter 13R red color difference signal A / D converter 14 Digital signal processing circuit for performing TDM encoding 141 2H delay circuit 142 Vertical filter for line sequentialization 143 Switch circuit for dividing into 2 channels 146A A channel frame memory 146B B channel frame memory 147A A channel memory controller 147B B channel memory controller

Claims (2)

[Claims] 1. A high-definition signal input as a component signal of a luminance signal and a color-difference signal is line-sequentialized for the color-difference signal, and then a memory is used to generate a luminance signal and a color-difference signal having the same line number. Is an encoding method for forming a plurality of channels of recording unit signals that are time-division-multiplexed in a state of inserting in front of a luminance signal, wherein the memory is serial access and has a plurality of output ports. In the memory, each recording unit signal is written in order of a luminance signal and a color difference signal, and in reading from the memory, a luminance signal and a color difference signal are obtained from separate output ports, and by connecting them, A recording / encoding method of a high-definition signal for obtaining the recording unit signal. 2. A high-definition signal input as a component signal of a luminance signal and a color-difference signal is line-sequentialized for the color-difference signal, and then a memory is used to obtain the luminance signal and the color-difference signal of the same line number. Is a serial access, the memory has a plurality of output ports and a plurality of samples A writing address can be specified for each, and the reading of a plurality of sample units is performed. By controlling the writing address of the memory, each recording unit signal is divided into a color difference signal and a luminance signal in this order. Writing to the memory, and sequentially reading the recording unit signal from the two output ports from the memory However, with the read section of each output port partially overlapped, the output of one port is switched to the output of the other port at an appropriate point in the overlap period so that the unit signal for recording is changed. A high-definition signal recording / encoding method that adjusts the time of joints.