JP3185806B2 - Hi-Vision signal recording encoding method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a recording TD for recording a Hi-Vision signal on a consumer VTR.
The present invention relates to a method of encoding an M (TIME DIVISION MATRIX) signal.

[0002]

2. Description of the Related Art In a VTR for recording and reproducing a high-definition (high-definition television) signal in a wide band and a high frequency band, a signal of a unit time, for example, one frame, is required to lower the frequency of the recording signal and narrow the frequency band. Is divided into a plurality of segments and a plurality of channels for recording.

[0003] That is, a high-vision signal is a signal having 1125 horizontal scanning lines per 30 Hz per frame. In the VTR recording system, the high-vision signal includes a luminance signal Y, a blue color difference signal PB and a blue color difference signal PB. It is input as a baseband signal including a component signal of the red color difference signal PR. The input luminance signal and color difference signal are once A / D converted to digital signals, and the time axis processing, the color signals are subjected to line sequential processing, and the like.

[0004] Then, the signal is divided into two channels A and B, and a synchronization signal SYNC, a burst signal SB, etc., a color signal C, and a luminance signal Y are time-divided as shown in FIG. TDM (TIME D
The signal is converted into a continuous recording signal of a unit period H ^* signal called an IVISION MATRIX signal. Then, the recording signal is returned to an analog signal, FM-modulated, and recorded on a magnetic tape by a rotating head.

[0005] Here, the unit period 1H ^* has a time length approximately twice as long as one horizontal period of the original Hi-Vision signal by dividing into two channels, and the luminance of one line having the same line number is included in this 1H ^*. The signal and the chrominance signal are time-division multiplexed.

FIG. 11 shows an example in which the HDTV signal of each frame is converted into the TDM signal as described above.
As shown in FIG. 10, the A channel track TA on the tape 4 is
1 and TA2 and B channel tracks TB1 and TB2
Are alternately formed and recorded on the magnetic tape as a total of eight tracks.

[0007] The rotary head device of the example of FIG. 11 is configured as follows.

That is, an A channel head 1A having a first azimuth angle and a B channel head 1B having a second azimuth angle different from the first azimuth angle are:
1 at the same rotation angle position of the rotating drum 3
It is shifted by the track width. Similarly, the A-channel head 2A having the first azimuth angle and the B-channel head 2B having the second azimuth angle rotate the rotating drum 3 at a rotation angle different from the heads 1A and 1B by 180 °. They are mounted offset by one track width in the axial direction.

Then, the magnetic tape 4 is wound obliquely around the drum 3 over an angular range of 180 ° + α, and the rotary heads 1A, 1B, 2A, 2B are rotated at a rotation speed of 60 Hz.

Then, on the magnetic tape 4, the rotary heads 1A and 1B and the rotary heads 2A and 2B alternately rotate the tape in the tape contact section of about 180 ° rotation angle.
As shown in FIG. 10, eight oblique recording tracks are formed per frame, and a high-definition signal is recorded.

That is, during one rotation, the rotary head 1A
1A and 1B are rotated by about 180 ° in the first half in which the tapes 4 and 1B come into contact with the tape 4 by the rotary heads 1A and 1B.
Are formed at the same time, and the rotary heads 2A and 2B are rotated by about 180 ° in the latter half of the rotation section where they come into contact with the tape 4.
A channel tracks TA2 and B by A and 2B
The channel tracks TB2 are formed at the same time, and thereafter, this is repeated alternately.

In this case, two rotary heads 1A, 1B,
Alternatively, one segment is composed of two tracks formed simultaneously by the rotary heads 2A and 2B, and the one segment includes a video signal for one half field and an audio signal for one half field period related to the video signal. To P
The CM-converted signal is recorded separately from the recording area. And four tracks TA1, TB1, TA2, TB
2 for 1 field, and 4 segments SEG1, SEG2,
SEG3 and SEG4 record a video signal and an audio signal of a high-definition signal for one frame.

As shown in FIG. 10, a control signal CTL is recorded on a longitudinal track at an end portion in the width direction of the tape 4 at a rate of one per frame, and is used for a tracking servo or the like during reproduction. Is done.

FIG. 12 is a block diagram of an example of a recording / reproducing system of a high-definition VTR provided with the rotary head device of FIG.

That is, in the recording system, as shown in FIG. 12, the luminance signal Y of the Hi-Vision signal input through the input terminal 11Y is a low-pass filter 12Y.
Is supplied to the A / D converter 13Y through the A / D converter, is A / D converted at a sampling frequency f _YCK = 44.55 MHz, is converted into a digital signal, and is supplied to the digital signal processing circuit 14.

The blue color difference signal PB and the red color difference signal PR of the Hi-Vision signal input through the input terminals 11B and 11R are supplied to the low-pass filters 12B and 12R.
Through each supplied to an A / D converter 13B and 13R, A in 1/4 of the sampling frequency f _CCK = 11.1375MHz sampling frequency of the video signal
The digital signals are converted into digital signals and supplied to the digital signal processing circuit 14 , respectively.

The digital signal processing circuit 14 includes a vertical filter and a frame memory for line-sequential processing of a color difference signal, and has a clock frequency f _TCK = 30.755 MHz phase-locked to a sampling clock of a luminance signal.
The digital signal processing such as the time axis processing and the line-sequential processing of the color difference signal is performed by the clock of z.
Encoded into a signal. The digital signal processing circuit 14 also performs a so-called shuffling process of rearranging the TDM signal with the original signal according to a predetermined rule.

The digital signal processing circuit 14 is supplied with a reference signal REF of one frame period (33.3 msec) from the terminal 5, and the TDM signal of one frame is synchronized with the reference signal REF from the frame memory. Read out. In this case, the read TDM signal is
It is divided into two channels A and B. Although not shown, the reference signal REF is recorded as a control signal by a fixed magnetic head at the end of the tape 4 in the width direction.

In the case of this example, the TDM signal has a detailed TDM waveform shown in FIG. That is, the TDM signal is composed of luminance signal data Y for one line of 1152 samples and blue or red color difference signal data C and 21 of 288 samples on the same line as the luminance signal.
The synchronization signal SYNC for the samples, the burst signal SB for 30 samples, and the ID data ID1,
A total of 1530 samples including ID2 is included.
The blanking period of the TDM signal including the synchronization signal SYNC, the burst signal SB, and the like is for 88 samples. The ID data ID1, ID2 is a segment identification signal (segment I
D), and by using data ID1 and ID2 for 2 bits,
Segment numbers 1 to 4 are shown.

The data of the two channels A and B from the digital signal processing circuit 14 are supplied to D / A converters 15A and 15B and D / A-converted, and the D / A converters 15A and 15B As shown in FIG. 13, a signal having a TDM waveform including ID data ID1 and ID2, a color signal C, and a luminance signal Y as segment identification signals, such as a synchronization signal SYNC and a burst signal SB, is obtained.

This signal is supplied to the low-pass filter 1
Emphasis circuits 17A, 17A through 6A and 16B
B, and a pre-emphasis process is performed. Then, the outputs of the emphasis circuits 17A and 17B are supplied to modulation circuits 18A and 18B, and are FM-modulated. Then, the FM-modulated A-channel data is supplied to the A-channel rotary heads 1A and 2A,
Further, the B-channel data subjected to the FM modulation is supplied to the B-channel rotary heads 1B and 2B, and recorded on the tape 4 as four segments (consisting of eight oblique tracks) for one frame as described above. Is done.

FIG. 14 shows the data content of the recording pattern on the tape formed at this time, particularly the area of the video signal area. In this example, ^{H *} number per track, for example 167.5H ^* (at 1 frame 8 track, 1340H ^*) is a, the video signal area is set to 139h ^* of them. Although not shown, audio data and others are recorded in the remaining area of each track.

In the area of the video signal, the first 3H
^* Is the preamble area of the video signal, and 1
36H ^* is a video signal recording area VA. FIG.
, The T of each H ^* unit of the video signal recording area VA
The numerical value given to the luminance signal data in the DM data is the line number of the original Hi-Vision signal. T for each 1H ^*
Since the chrominance signal data and the luminance signal data multiplexed as the DM signal are on the same line, their line numbers are omitted.

In the example of the figure, the recording area of 1040H ^* surrounded by a thick line is the number of effective video lines per frame of the Hi-Vision signal (the number of lines excluding the vertical blanking period, ie, the 41st line to the 41st line of one frame). Line 557 and lines 603 to 1120 total 10
35 lines). In the example shown in the figure, there is a possibility of 1080 lines in consideration of a horizontal line section necessary for various test signals and the like in the vertical blanking period. A region corresponding to 1080H ^* is provided.

In the preamble area, a CW signal (continuous wave signal for PLL synchronization), a segment synchronization signal V,
A reference level signal L for applying AGC during reproduction, a ramp signal R for linearity correction, and the like are recorded.

Next, the reproduction system of the high definition VTR of this example will be described. At the time of this reproduction, although not shown, a reproduction control signal C from a fixed magnetic head is provided.
The TL and the reference signal REF are compared in phase, and tracking control is performed based on the phase comparison output and the envelope output of the reproduced video signal so that the rotating head can correctly scan the recording track. In this case,
Using the segment identification signal in the reproduced TDM signal, synchronization can be achieved in frame units.

In the reproduction system, reproduction signals from the A-channel rotary heads 1A and 2A are supplied to an FM demodulation circuit 22A via a reproduction amplifier 21A and are FM-demodulated.
Reproduction signals from the rotary heads 11B and 2B of the channels are supplied to an FM demodulation circuit 22B via a reproduction amplifier 21B and are subjected to FM demodulation. And these FM demodulation circuits 2
The output signals of 2A and 22B are supplied to de-emphasis circuits 23A and 23B, respectively, and are subjected to de-emphasis processing, respectively.

The de-emphasis circuits 23A and 23A
The output signal of 3B is supplied to A / D converters 25A and 25B via low-pass filters 24A and 24B, respectively, is converted into a digital signal, and then is supplied to a digital signal processing circuit 26 having a frame memory.

The digital signal processing circuit 26 performs a de-shuffling process for returning the TDM signals rearranged at the time of recording to the original order, a TDM decoding process for converting the TDM signals into luminance signals, blue and red color difference signals, and furthermore, Processing for synchronizing the blue and red color difference signals is performed. The digital signal processing circuit 26 is supplied with a reference signal REF of a frame period from the terminal 5. This reference signal REF
Are synchronized with the reproduction data in frame units by the tracking servo described above. From the frame memory of the digital signal processing circuit 26, data of the luminance signal and the color difference signal is read out in synchronization with the reference signal REF.

Then, the luminance signal from the digital signal processing circuit 26 is returned to the original analog signal through the D / A converter 27Y and the low-pass filter 28Y, and is led out to the output terminal 29Y. The blue and red color difference signals from the digital signal processing circuit 26 are supplied to the D / A converter 2.
7B, 27R and the low-pass filters 28B and 28R return to the original analog signals, and are led to output terminals 29B and 29R, respectively.

Generally, most large-capacity, high-speed memories such as a field memory and a frame memory for processing video data are of serial access called FIFO, and write video data from an arbitrary address. Cannot read. For this reason, the digital signal processing circuit 14 for performing the TDM encoding of the recording system of the Hi-Vision VTR had to be configured as shown in FIG.

That is, in FIG. 15, 141A is A
A frame memory for channel 141B is a frame memory for channel B, each of which is composed of a serial access memory.

The A / D converters 13B and 13
The blue and red color difference signals PB and PR (FIGS. 16B and 16C) converted into digital signals from R
2 and is subjected to line-sequencing processing, and a line-sequential signal PBR (FIG. 16E) is obtained from the vertical filter 142.
This line-sequentialized signal PBR is supplied to the other input terminal b of the switch circuit 143 for dividing into two channels A and B.

The vertical filter 142 has a delay circuit of 1H (H is a horizontal cycle), so that the line-sequentialized signal PBR is converted to the original color difference signal PB, as is apparent from FIGS. , PR are delayed by 1H. As shown in FIGS. 9 and 14, T
In the DM signal, the color difference signal is time-division multiplexed before the luminance signal in time. Since the frame memories 141A and 141B perform serial access, it is necessary to write data in an order that matches the TDM signal at the time of writing. For this purpose, the luminance signal Y needs to be delayed by 2H.

Therefore, the luminance signal Y (FIG. 16A) converted into a digital signal by the A / D converter 13Y is 2
After being delayed by 2H period by the H delay circuit 144, one input terminal a of the switch circuit 143 is supplied.

The switch circuit 143 is alternately switched between one input terminal a and the other input terminal b every 1 H period by a switching signal SW from the terminal 145. By this switching, as shown in FIG. 16F, PB1, Y1, PB3 and PB3 are output from one output terminal of the switch circuit 143.
Y3,... And the A-channel signal Va in which the blue color difference signal and the luminance signal of the odd-numbered line are alternately obtained. Further, from the other output terminal of the switch circuit 143, FIG.
As shown in G, PR2, Y2, PR4, Y4,.
The signal Vb of the B channel in which the red color difference signal and the luminance signal of the even-numbered line alternately are obtained.

The signal Va of the A channel is supplied to the frame memory 141A and written therein, and the signal Vb of the B channel is supplied to the frame memory 141B and written therein. At this time, the color difference signal is 1 /
4 is written at a write rate of 4.

Then, from the frame memory 141A,
The TDM is shuffled in the order shown in FIG. 17A.
The signal is read out, and the A channel track T is recorded on the tape 4.
A1 and TA2 are recorded. Similarly, from the frame memory 141B, shuffling is performed as shown in FIG.
The TDM signals are read out in the order shown in FIG.
Are recorded as B channel tracks TB1 and TB2. In this case, as shown in FIG. 17C and FIG.
4 is performed in segment SEG2, and so on. The line numbers in FIGS. 16 and 17 are for explanation, and are different from the line numbers of the tape pattern shown in FIG.

[0039]

As described above, the TD
Since the high-speed memory used as the frame memory for M-encoding is a serial access called FIFO, the luminance signal Y is used to make the color difference signal precede the luminance signal to form a TDM signal. 2H
It was necessary to delay by two lines by the delay circuit 144.

For this reason, conventionally, the delay circuit 1 for two lines
44, the frame memory 141A, a extra required in addition to 141B, as well as requires an extra space, the more power consumption, also has a disadvantage that becomes costly.

In view of the above, it is an object of the present invention to provide a method capable of encoding a TDM signal using only a serial access frame memory (or field memory) without requiring the above-described 2H delay circuit. I do.

[0042]

In order to solve the above-mentioned problems, the present invention proposes two invention methods, and the method of claim 1 is a method which can be applied to the case where reference numerals in the following embodiments correspond to each other. After a high-vision signal input as a component signal of a signal and a color difference signal is converted to a line-sequential color difference signal, the memories 146A and 146B are used to convert a luminance signal and a color difference signal of the same line number into a luminance signal. Wherein the memory 146A and 146B are serial access, and use a memory having a plurality of output ports, wherein the memory 146A and 146B are memories having a plurality of output ports. The memories 146A and 146B store the luminance signal and the color difference of the same line number as the unit signals for recording.
Signals are written in the order of a luminance signal and a color difference signal, and when reading from the memories 146A and 146B, the luminance signal and the color difference signal are obtained from separate output ports.
By connecting them, a unit signal for recording is obtained.

The method according to claim 2, wherein the memory 14
6A and 146B are serial accesses having a plurality of output ports, capable of specifying a write address for each of a plurality of samples, and performing reading in units of the plurality of samples.
The write addresses of A and 146B are controlled to write in the memories 146A and 146B in the order of a color difference signal and a luminance signal for each recording unit signal, and two output ports 1 and 2 are output from the memories 146A and 146B. From the output port 1 and the output port 1 and the output port 2 at a suitable time during the overlap period. , So that the timing of the joint of the recording unit signals is adjusted.

[0044]

In the method according to the present invention, since the luminance signal is supplied to the memory without delay, the luminance signal precedes the color difference signal in the input data of the memory.

In the case of the method according to the first aspect of the present invention, the data is written in the memory in the same order. The memory has a plurality of output ports, from which data can be read independently. According to the first aspect of the present invention, the same data is read from the two output ports while shifting the read timing. For example, the same data is read out by shifting by 1H ^* .

Then, the color difference signal data is extracted from one of the output ports preceding the data, the luminance signal data is extracted from the other output port, and the two are combined to obtain a required TDM signal. is there.

In the case of the method according to the second aspect of the present invention,
The memory is a serial access, has a plurality of output ports, is capable of specifying a write address for each of a plurality of samples, and performs reading in units of the plurality of samples. Therefore, data is written to the memory in a state where the write address is controlled and the color difference signal precedes the luminance signal.

Therefore, if this is read from the memory, data in the order matching the TDM signal can be obtained. However, since the memory can only write and read data for a plurality of samples, the joint of 1H ^* unit data, that is, the blanking period of the TDM signal is TDM.
In many cases, it does not conform to the signal standard.

According to the present invention, the output of the port 1 and the output of the port 2 are alternately obtained every 1H ^* as the read output of the memory, and the read is performed so that some outputs overlap at the joint of both ports. Control. Then, by controlling the overlap period, TD
A read data output conforming to the M signal standard can be obtained.

[0050]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a recording and encoding method according to the present invention will be described below with reference to the drawings, taking as an example a case where the recording and encoding method is applied to the aforementioned high definition VTR of FIG.

FIG. 1 is a block diagram of a digital signal processing circuit 14 for executing an embodiment of the recording encoding method according to the present invention. That is, the digital luminance data DY (FIG. 2A) from the A / D converter 13Y is supplied to one input terminal a of the switch circuit 143 without delay. Then, the line-sequential color difference signal data PBR (FIG. 2B) from the vertical filter 142 is supplied to the other input terminal b of the switch circuit 143 in the same manner as in the above-described example.

As described above, this switch circuit 143 is alternately switched to one input terminal and the other input terminal every 1 H by the switching signal SW from the terminal 145. As the data VA of the A channel from the switch circuit 143, data of an odd-numbered line is obtained as shown in FIG. 2C. However, since the luminance signal Y is not delayed, the data of the same line number is Are obtained prior to the color difference signal data, and do not match the data order of the TDM signal.

Similarly, as the data VB of the B channel of the switch circuit 143, as shown in FIG. 2D, the data of the even-numbered line and the data of the same line number are:
The luminance signal is obtained prior to the color difference signal data, and does not match the data order of the TDM signal.

A-channel data VA and B-channel data VB from the switch circuit 143 are supplied to A-channel and B-channel video frame memories 146A and 146B, respectively.

In the present invention, the A and B channel video frame memories 146A
And 146B, a frame memory having a plurality of output ports, in this example, two output ports, output port 1 and output port 2, is used. Memory controllers 147A and 147B are provided for the frame memories 146A and 146B. The memory controllers 147A and 147B respectively input data VA and VB to the frame memories 146A and 146B.
And the reading of data from the output port 1 and the output port 2 is independently controlled.

In this case, the frame memory 146
The output data read out from A and 146B is the combined data of the data obtained at the two output ports 1 and 2, respectively.

In the present invention, as described below, there are two methods for encoding a TDM signal by changing the manner in which the memory controllers 147A and 147B write and read the frame memories 146A and 146B. Suggest an example. The main features of the memories 146A and 146B used in this example are as follows.

The port on the writing side is one port, while the port on the reading side is two ports (output port 1 and output port 2), and these three ports are asynchronous with each other.

Basically, serial access is performed, but random access can be performed only in writing in the row direction in units of 60 samples (this is called a block). Also,
In the column direction, random access can be performed at the time of writing and reading only in the direction of increasing the line number.

Both writing and reading can be performed only in block units (60 sample units).

｛960 samples (= 60 samples ×
16 blocks) / line｝ × 360 lines.

[First Method] The writing by the first method will be described with reference to FIGS. 3 and 4, and the first method will be described with reference to FIG.
Will be described.

In the first method, the writing of the luminance signal data and the chrominance signal data is performed in the order of the data shown in FIGS. 2C and 2D, and the reading is encoded using two output ports to encode the TDM signal. The way to do it.

That is, FIG. 3 shows a time chart for writing data according to the first method, and is an example in the case of writing data VA of the A channel to the memory 146A. Memory 14 for B channel data VB
Since writing to 6B can be performed in exactly the same manner, description thereof is omitted.

In the case of this example, the memories 146A and 146B are provided for each of two phases, and are assigned to each phase for each sample to perform processing in parallel. Therefore, as shown in FIG. 3A, one-half of the number of samples of the TDM signal shown in FIG. 13 is handled in one phase.

The examples described below all relate to one phase. As is clear from FIG. 13, the number of data samples for one phase handled as a TDM signal is 576 for luminance signal data and 144 for chrominance signal data. The interval between the chrominance signal data and the luminance signal data is 3 samples, and the blanking period as a TDM signal, which is the section before the chrominance signal data, is 42 samples.

[Description of Writing] Next, writing by the first method will be described. That is, the data VA (FIG. 3A) input to the frame memory 146A is applied to the sample clock (sampling frequency f) of the luminance signal during the high level period of the write enable signal WEN (FIG. 3B).
Writing is performed according to ( _YCK = 44.55 MHz).

In this case, the write address is a serial address. For the color difference signal data, as shown in FIG. 3B, the memory 146A is set to the write enable state for every three samples for one sample period. The color difference signal data is written in a time-compressed state as shown in FIG.

FIG. 3C shows a write vertical reset signal WVRS. When the write vertical reset signal WVRS is supplied to the frame memory 146A, the line address is reset to 0 and writing starts. FIG. 3D shows a write horizontal reset signal WHRS. When this signal is supplied to the frame memory 146B, the sample address in the line direction is reset to 0. FIG. 3E shows a write line increment signal WHJP, one pulse of which is stored in the memory 146A.
, The line address is increased by one each time it is supplied.

By supplying each signal to the frame memory 146A at the timing shown in FIG. 3, the luminance signal data and the color difference signal data are written into the frame memory 146A as shown in FIG. Here, the number of data is 576 + 144 = 720, which is exactly divisible by a block of 60 samples. Each line address includes the luminance signal data of a certain line and the color difference signal data of the same line from the 0th block to the 11th block. Is just packed and written.

[Explanation of Reading] Next, reading in the case of the first method will be described. in this case,
The two output ports, port 1 and port 2, are controlled as shown in FIG.

First, the read control for the port 1 will be described. That is, when the read vertical reset signal RVRS1 (FIG. 5A) is supplied to the memory 146A, the line address is reset to 0, and the reading starts. Then, the read horizontal reset signal R
HRS1 (FIG. 5B) is a pulse of 1H ^* period,
Each time a pulse is supplied to the memory 146A, the sample address in the line direction is reset to zero.

The read line increment signal RHJP1 (FIG. 5C) is the read horizontal reset signal R
1H ^{* has} passed since HRS1 was supplied, and it was generated immediately before the next readout horizontal reset signal RHRS1 was generated,
The line address jumps by one line for each pulse. In the case of this example, in order to distribute the data for one field into two segments, two lines are jumped every 1H ^* .

Read clock enable signal RCEN
1 (FIG. 5D) enables the supply of the read clock to the frame memory 146A only when this is the high level period. First, the read horizontal reset signal RH
The level becomes high for 576 sample sections from the time of RS1 (FIG. 5B), and the luminance signal data is read. Then, the signal becomes low level for the next 42 sample periods, the read clock is stopped, and a horizontal blanking period of the TDM signal is formed. Thereafter, the 144 sample section becomes high level, and the color difference signal data is read. Then, in the next three sample sections, the read clock stops at the low level, and a section between the color difference signal data and the luminance signal data is formed. This is the end of the 1H ^* period, and this is repeated hereafter.

As for the port 2, the read vertical reset signal RVRS2 (FIG. 3F), the read horizontal reset signal RHRS2 (FIG. 3G), and the read horizontal increment signal RHJP2 (FIG. The signal is delayed by 1H ^* period from those. The read clock enable signal RCEN2 (FIG. 3I) is completely equal to that of the port 1.

Therefore, the luminance signal data and the color difference signal data can be obtained from the output port 1 at the timing shown in FIG. 3K. However, the output enable signal OPEN1 (FIG. 3E) of the output port 1 causes the output port 1 to output. 1 indicates that data can be output only in the 144 sample section of the color difference signal data.
As T1, the luminance signal data indicated by oblique lines in FIG. 3K cannot be obtained, and the color difference signal data PB1, PB5, PB
9, ... only.

As shown in FIG. 3L, the same luminance signal data and color difference signal data can be obtained from the output port 2 at a timing delayed by 1H ^{* with} respect to the port 1. Enable signal OPEN2
According to (FIG. 3J), the output port 2 can output data only in the 576 sample period of the luminance signal data. In fact, as the output POT2 of the output port 2, the color difference indicated by hatching in FIG. No signal data is obtained, and only luminance signal data Y1, Y5, Y9,... Are obtained.

Therefore, as output data read out from the frame memory 146A, output POT1 consisting of only the color difference signal data PB1, PB5, PB9,... From the output port 1 and luminance signal data Y from the output port 2
An output MOUT (FIG. 3M) is obtained by combining the output POT2 consisting only of 1, Y5, Y9,. It goes without saying that the output data MOUT conforms to the format of the TDM signal in FIG.

[Second Method] Next, the writing by the second method will be described with reference to FIGS. 6 and 7, and the reading by the second method will be described with reference to FIG.

This second method utilizes the fact that writing can be performed randomly in block units (60 samples).

That is, FIG. 6 shows a time chart for writing data according to the second method, which is an example in the case of writing data VA of the A channel to the memory 146A. Since the writing of the B channel data VB to the memory 146B can be performed in exactly the same manner,
The description is omitted. Also, in this case,
Both memories 146A and 146B are provided for two phases, and are assigned to each phase for each sample to perform processing in parallel. As in the previous example, all the examples described below are for one phase.

[Explanation of Writing] Next, writing by the second method will be described. In this case, the write enable signal WEN (FIG. 6B), the write vertical reset signal WVRS (FIG. 6C), and the write horizontal reset signal RHRS (FIG. 6D) are stored in the frame memory 146A as in the case of the first method. , The write line increment signal WHJP (FIG. 6F) is supplied, but unlike the first method, the write horizontal reset signal WHRS is 1H
Every, that is, for each of the luminance signal data and the color difference signal data,
One pulse rises.

Then, a write start block address is designated as shown in FIG. 6E in synchronization with the write horizontal reset signal WHRS for each 1H. That is, for the luminance signal data, the third (0011) block is specified as a write start address, and for the color difference signal data, the 0 (0000) block is specified as a write start address. Note that the write line increment signal WHJP has one pulse every 1H ^* period (about 2H) as in the case of the first method.

Therefore, of the data VA (FIG. 6A) input to the frame memory 146A, the luminance signal data is written from the third block of the memory 146A at the address in the line direction, and the color difference signal data is stored in the memory 146A.
Writing is performed from the 0th block (initial block address) of the address in the line direction of A.

At this time, the write enable signal WEN
The sample clock of the luminance signal (sampling frequency f _YCK = 44.55 MHz) in the high level period of FIG. 6B.
In the case of the second method, as shown in FIG. 6B, there are three samples between the chrominance signal data and the luminance signal data. There will be a blank writing period. And
The luminance signal data is written to the memory 146A from the fourth clock.

When writing is performed in this manner, 5 addresses are stored from the third block to the twelfth block of the address in the line direction.
76 samples of luminance signal data are written, leaving 21 samples at the end of the twelfth block. Therefore, as shown in FIG. 6B, the write enable signal WEN is
The luminance signal data is at a high level longer by 21 samples than the end of the luminance signal data.
A is written blank.

In the case of the second method, the 0th
From the block to the second block, color difference signal data of 144 samples is written so as to be exactly packed. For this reason,
As shown in FIG. 6B, the write enable signal WEN
Is assumed to be capable of writing extra 180-144 = 36 samples for the color difference signal data, and the 36 samples are blank-written.

The above write control signal is transmitted to the memory 1
By supplying the data to the memory 46A, it is possible to perform writing to the memory 146A in a state where the color difference signal data of a certain line precedes the luminance signal data of the same line at each line address, as shown in FIG.

[Explanation of Reading] Next, reading in the case of the second method will be described with reference to FIG. In this case, if the data written in the frame memory as shown in FIG. 7 is read out serially as it is, the blank write data of the last 21 samples of the luminance signal data and the blank write data of the first 36 samples of the color difference signal data are obtained. And 57 samples, which does not match 42 samples in the blanking period of the TDM signal. Therefore, in the second method, the length of the blanking period is set to 42 samples in the following manner by using two output ports 1 and 2.

First, a pulse is raised as a read reset signal RVRS1 (FIG. 8A) for port 1, and reading can be started. At the same time, a pulse rises as the first read horizontal reset signal RHRS1 (FIG. 9B), the sample address in the line direction is reset to 0, and the color difference signal data PB from the 0th block on the 0th line is reset.
1 and the luminance signal data Y1 start to be read (FIG. 8E).
reference).

Next, at a point 15 samples before the last data of the data of the 0th line from port 1 (the portion of 21 samples of blank writing), the read vertical reset signal RVRS2 for port 2 (FIG. 8G) ), The pulse rises, and the port 2 is ready to start reading. This read vertical reset signal RVR
Before S2 rises, two pulses are generated as the read line increment signal RHJP2 (FIG. 8I), and the read line address at port 2 at this time is the second line.

Then, the read vertical reset signal RVR
First read horizontal reset signal RHR in synchronization with S2
A pulse rises as S2 (FIG. 8H), the sample address in the line direction is reset to 0, and the chrominance signal data PB5 and the luminance signal data Y from the 0th block on the second line.
5 starts reading (see FIG. 8F).

Port 2 read vertical reset signal RV
Since the pulse as RS2 overlaps with the read data of port 1 by 15 samples and is generated,
The end portion of the port 1 read data and the start portion of the port 2 read data overlap for a period of 15 samples. Due to this overlap period,
The period from the end of the luminance data from port 1 to the color difference signal data at the beginning of port 2 is 36 + 21-15 = 4
This corresponds to two samples, which matches the blanking period of the TDM signal.

Next, at a point 15 samples before the last data (portion of 21 samples of blank writing) of the data of the second line from the port 2, the read horizontal reset signal RHRS1 for the port 1 (FIG. 8B) ), The pulse rises again, and the address of the read line for port 1 is reset to 0.

This read horizontal reset signal RVRS1
Before rising, four pulses are generated as the read line increment signal RHJP1 (FIG. 8C). At this time, the read line address at the output port 1 is the fourth line, and the color difference from the 0th block of the fourth line is obtained. Reading of the signal data PB9 and the luminance signal data Y9 starts (see FIG. 8E).

As described above, the end of the port 2 read data and the start of the port 1 read data overlap for a period of 15 samples. Therefore, the period from the end of the luminance data from port 2 to the color difference signal data at the beginning of port 1 is also 42 samples, which matches the horizontal blanking period of the TDM signal.

Similarly, the read data of the port 1 and the read data of the port 2 are read at the beginning and the end thereof in such a manner that they overlap each other for a period of 15 samples.

In this case, also for port 2, the read line increment signal RHJP2 (FIG. 8I) has four pulses from the second read horizontal reset signal RHRS2 so that the line address jumps every four lines. Occurs similarly to 1.

Also, due to the existence of the overlap period,
After reading data from one line address from port 1 or port 2, the read clock is stopped for 30 clocks until the start of reading data of the next line address.

The output port 1 can output data in response to the read output enable signal OPEN1 (FIG. 8D) during a period of only the color difference signal data and the luminance signal data except for the blank portion of the read data. , Output port 2 also outputs read output enable signal OP
EN2 (FIG. 8J) enables data output in a period of only the color difference signal data and the luminance signal data, excluding the blank portion of the read data. Therefore, memory 1
As the output data of 46A, as shown in FIG. 8K, a target TDM signal is obtained.

Although the frame memory is used as the video memory in the above example, a field memory may be used.

[0102]

As described above, according to the present invention, by using a serial access memory having a plurality of output ports as a video memory and controlling the reading of these plurality of output ports, , A recording signal, that is, a TDM signal can be encoded from a Hi-Vision signal without providing a separate memory. For this reason, the conventionally required delay circuit for the 2H period is not required, which simplifies the configuration and contributes to cost reduction.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of a main part of a high definition VTR for performing a method according to the present invention.

FIG. 2 is a time chart for explaining the operation of FIG. 1;

FIG. 3 is a time chart for explaining a memory writing method according to an embodiment of the first method according to the present invention;

FIG. 4 is a diagram showing data contents of a memory to which data is written by the method of FIG. 3;

FIG. 5 is a time chart for explaining a memory read method according to one embodiment of the first method according to the present invention;

FIG. 6 is a time chart for explaining a memory writing method according to an embodiment of the second method according to the present invention;

FIG. 7 is a diagram showing data contents of a memory to which data is written by the method of FIG. 6;

FIG. 8 is a time chart for explaining a memory read method according to an embodiment of the second method according to the present invention;

FIG. 9 is a diagram for explaining a TDM signal for recording a high-definition signal.

FIG. 10 is a diagram showing a tape pattern recorded by a high definition VTR.

FIG. 11 is a diagram showing an example of a rotary head device used for a high definition VTR.

FIG. 12 is a block diagram of an embodiment of a recording / reproducing system of a high definition VTR.

FIG. 13 is a diagram illustrating an example of a detailed format of a TDM signal.

FIG. 14 is a diagram for explaining a video data recording area of a tape pattern.

FIG. 15 is a block diagram for explaining a main part of a conventional recording and encoding method.

FIG. 16 is a time chart for explaining a conventional recording encoding method.

FIG. 17 is a diagram for explaining recording data of a Hi-Vision signal.

[Explanation of symbols]

 11Y luminance signal input terminal 11B blue color difference signal input terminal 11R red color difference signal input terminal 13Y luminance signal A / D converter 13B blue color difference signal A / D converter 13R red color difference signal A / D converter 14 Digital signal processing circuit for performing TDM encoding 141 Delay circuit for 2H 142 Vertical filter for line sequentialization 143 Switch circuit for dividing into two channels 146A Frame memory for A channel 146B Frame memory for B channel 147A Memory for A channel Controller 147B B channel memory controller

Claims (2)

(57) [Claims] 1. A high-vision signal input as a component signal of a luminance signal and a color difference signal, the color difference signal is line-sequentialized, and then the luminance signal and the color difference signal of the same line number are converted into a color difference signal using a memory. A time-division multiplexed recording unit signal for a plurality of channels in a state of being inserted before a luminance signal, wherein the memory is a serial access and has a plurality of output ports, in the memory as the recording unit signal component, the same
A luminance signal and a color difference signal of a line number are written in the order of a luminance signal and a color difference signal, and in reading from the memory, a luminance signal and a color difference signal are obtained from separate output ports, and by connecting them, the A recording encoding method for a high-definition signal in which a unit signal for recording is obtained. 2. A high-vision signal input as a component signal of a luminance signal and a chrominance signal is line-sequentially converted into a chrominance signal, and then a luminance signal and a chrominance signal having the same line number are converted into a chrominance signal using a memory. A time-division multiplexed recording unit signal for a plurality of channels in a state of being inserted before a luminance signal, wherein the memory is a serial access, has a plurality of output ports, and has a plurality of samples. It is assumed that a write address can be specified every time, and that the read operation in the unit of a plurality of samples is performed.The write address of the memory is controlled, and a color difference signal and a luminance signal are arranged in the order of each recording unit signal. Writing to the memory, and sequentially reading the recording unit signal from two output ports from the memory. However, in a state where the read section of each output port partially overlaps, at an appropriate time during the overlap period, the output of one port is switched to the output of the other port, so that the recording unit signal is output. A method of recording and encoding a high-definition signal in which the joints are timed.