JPH05165659A - Microprocessor - Google Patents

Abstract

PURPOSE:To make the number of two-word instructions 4-fold by providing a command managing part between a command decode circuit and a parity check circuit. CONSTITUTION:When a command code is a one-word instruction, a command managing part 10 issues the instruction of parity check to a parity check circuit 24. The parity check circuit 24 receives the instruction, reads one word from a command buffer circuit 23 and executes the parity check while defining the read one-word command code from a least significant bit to the 2nd bit designated in advance as a parity bit. When no parity error is recognized, the execution of the command is stopped and when the parity error is not detected, this command is executed. On the other hand, when the command code is a two-word instruction, the command managing part 10 does not issue the instruction of the parity check since no parity bit exists in the 1st word.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor, and more particularly to a microprocessor using 1-word and 2-word instructions.

[0002]

2. Description of the Related Art It is important to increase the number of instructions per unit number of words in order to realize a highly functional microprocessor. For example, in a microprocessor that executes only one word, if two parity bits are used in one word, the number of instructions is 2 ¹³ . If only one bit of one word is used as the parity bit, the number of instructions is 2 ¹⁴ . Therefore, if two parity bits are used and only one bit is used,
If only one parity bit is used, the number of instructions will double. However, it is dangerous to eliminate the parity bit in terms of reliability.

Next, a conventional microprocessor will be described with reference to the drawings.

FIG. 3 is a block diagram for explaining the operation of a conventional microprocessor.

In FIG. 3, a microprocessor b2 of a conventional example has a program counter 20 for designating an execution address of a program, a command data code circuit b21 for decoding a microcode and distributing it into a data code and a command code, and a command decoding circuit b21. Data buffer circuit 22 for storing the data code from command buffer circuit 23, command buffer circuit 23 for storing the command code from command decode circuit b21, and command buffer circuit 2
3 and a parity check circuit 24 that performs a parity check on the command code. The control memory 30 is connected to the parity check circuit 24.

Next, the operation of the conventional microprocessor will be described with reference to FIG.

The 1-word instruction used in the command code is the least significant bit and the bit before that, that is,
Two bits are the parity bits. For the first and second words of the two-word instruction, the address issued by the program counter 20 is transmitted to the control memory 30 through the address bus. The control memory 30 outputs the previously stored microcode from the designated address to the data bus. The microcode is decoded by the command decode circuit b21 through the data bus. The command decoding circuit b2 determines whether it is a command code or a data code by looking at the bit that determines the command in the microcode.
1 recognizes. If the microcode is a data code, the command decoding circuit b21 sends the microcode, that is, the data code, to the data buffer circuit 22.
Write in. When the microcode is a command code, the command decode circuit b21 writes the microcode, that is, the command code, in the command buffer circuit 23, and then instructs the parity check circuit 24 to perform a parity check. If the command code is a 1-word instruction, then the program counter 20
Since the command code is included in the microcode when is counted up, the command code is written in the command buffer circuit 23 by the command decoding circuit b21 as in the case of the first word. After that, the command decoding circuit b21 gives a parity check instruction to the parity check circuit 24.

[0008]

The above-described conventional microprocessor capable of executing 1-word and 2-word instructions performs a parity check on both the first word and the second word at the time of the 2-word instruction. Since there is a parity bit, the number of instructions is small, and there is a disadvantage in that it cannot be highly functional.

Further, in order to make the number of instructions the same, a three-word instruction is required, and there is a drawback that the processing time increases accordingly.

An object of the present invention is that, when the command code is a 1-word instruction, the command management unit 10 issues a parity check instruction to the parity check circuit 24, and the parity check circuit 24 causes the command buffer circuit 23 to operate. 1 word is read, and from the read command code, the least significant bit to 2 bits are used as parity bits to perform a parity check. On the other hand, if the command code is a 2 word instruction, there is no parity bit in the 1st word. Therefore, the command management unit 10 does not issue a parity check instruction, and the command management unit 10 is provided between the command decode circuit a11 and the parity check circuit 24 to execute 1-word and 2-word instructions, and to execute 2-word instructions. Remove the parity bit in the first word, By using it as a command code recognition bit, the above drawbacks can be solved, and the number of 2-word instructions can be quadrupled as compared with the one that used 2 parity bits in the first word of a 2-word instruction. Accordingly, it is to provide a microprocessor capable of achieving higher functionality.

[0011]

A microprocessor of the present invention decodes a program counter for designating an execution address of a program, a microcode stored at an address indicated by the program counter, and distributes it to a data code and a command code. A command decoding circuit, a data buffer circuit for storing the data code from the command decoding circuit, a command buffer circuit for storing the command code from the command decoding circuit, and a command management section for storing information about commands from the command buffer circuit. When the command code is a 1-word instruction, it is possible to execute a 1-word instruction having a 1-word command code and a 2-word instruction having a 2-word command code. , When the first word of a two-word instruction has become a instruction code.

[0012]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram for explaining the operation of the microprocessor of one embodiment of the present invention, and FIG. 2 is a diagram showing the contents of the command code of the microprocessor of this embodiment.

Here, the same symbols are used for the same components as those in the section of the prior art.

In FIG. 1, a microprocessor b1 of the present embodiment has a program counter 20 for designating an execution address of a program, a command decoding circuit 11 for decoding a microcode and distributing it into a data code and a command code, and a command decoding circuit 11 Data buffer circuit 22 for storing the data code from the command decoding circuit 11, the command buffer circuit 23 for storing the command code from the command decoding circuit 11, and the command management unit 10 for storing information related to the command from the command buffer circuit 23.
And the control memory 30 is connected.

More specifically, a program counter 20 for designating an execution address of a program and a control memory 30 storing microcode are connected by an address bus, and the control memory 30 and a command decoding circuit are connected by a data bus. 11 and 11 are connected. The data buffer circuit 22, the command buffer circuit 23, and the command management unit 10 are connected to the command decoding circuit 11. The parity check circuit 24 is connected to the command buffer circuit 23 and the command management unit 10.

Next, the operation of the microprocessor of this embodiment will be described with reference to the drawings.

Here, in FIG. 2, the command code of this embodiment is such that, in the case of the 1-word instruction 310, the least significant 2 bits are the parity bits, and in the case of the 2-word instruction,
There is no parity bit in the first word 320, and the least significant 2 bits are the parity bit 3 only in the second word 321.
Shall be 02.

1 and 2, the address issued from the program counter 20 is transmitted to the control memory 30 through the address bus. The control memory 30 outputs the prestored microcode to the data bus from the designated address. The microcode is decoded by the command decoding circuit 11 through the data bus. The command code circuit 11 recognizes whether it is a command code or a data code by observing a bit for discriminating a command in the microcode. When the microcode is a data code, the command decoding circuit 11 writes the microcode, that is, the data code, in the data buffer circuit 22. When the microcode is a command code, the command decoding circuit 11 analyzes the microcode, that is, the command code, and determines whether there is a next command code, that is, a two-word instruction, or next. Is there no command?
The command decoding circuit 11 checks whether the instruction is a 1-word instruction and sends the information to the command management unit 10.

When the command code is a 1-word instruction, the command management unit 10 causes the parity check circuit 24
, And issues a parity check instruction. The parity check circuit 24 receives an instruction from the command management unit 10 and reads one word from the command buffer circuit 23. The parity check circuit 24 performs the parity check by using the least significant bit to the second bit, which is specified in advance, as the parity bit in the read one-word command code. When the parity check circuit 24 recognizes a parity error, the execution of the command is stopped. If no parity error is detected by the parity check circuit 24, this command is executed.

On the other hand, when the command code is a 2-word instruction, the parity bit does not exist in the first word, so the command management unit 10 does not issue a parity check instruction.

The program counter 20 counts up every specified time and issues the next address to the control memory 30. The control memory 30 outputs the prestored microcode from the designated address to the data bus. The microcode data is decoded by the command decoding circuit 11 through the data bus. The command decoding circuit 11 determines the microcode, but since the command management unit 10 has information that the first word of the two-word instruction is read, the command buffer is used as the command code of the second word of the two-word instruction. Write to the circuit 23. At this time, at the same time, the command management unit 10 is instructed that the command has been established as a 2-word command. In response to this, the command management unit 10 instructs the parity check circuit 24 to perform a parity check for two words. Upon receiving the instruction, the parity check circuit 24 reads the 2-word command code from the command buffer circuit 23 and performs parity check using the least significant bit to the second bit of the second word as parity bits. When the parity check circuit 24 recognizes a parity error, the execution of the command is stopped. If the parity check circuit 24 does not detect a parity error, the 2-word instruction will be executed.

[0023]

As described above, in the microprocessor of the present invention, the command management unit is provided between the command decoding circuit and the parity check circuit so that the 1-word and 2-word instructions can be executed and the 2-word instruction can be executed. By eliminating the parity bit in the first word and using it as a command code recognition bit accordingly, the number of instructions in the two-word instruction is four times as large as that in the two-word instruction that used two bits of the parity bit in the first word. Therefore, there is an effect that higher functionality can be achieved accordingly.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating an operation of a microprocessor according to an exemplary embodiment of the present invention.

FIG. 2 is a diagram showing the contents of a command code of the microprocessor of this embodiment.

FIG. 3 is a block diagram for explaining the operation of a conventional microprocessor.

[Explanation of symbols]

 1 Microprocessor a 2 Microprocessor b 10 Command Management Unit 11 Command Decode Circuit a 20 Program Counter 21 Command Decode Circuit b 22 Data Buffer Circuit 23 Command Buffer Circuit 24 Parity Check Circuit 30 Control Memory 301 Parity Bit 302 Parity Bit 310 1 Word Instruction 320 2nd word instruction 1st word 321 2word instruction 2nd word

Claims (1)

[Claims] 1. A program counter for instructing an execution address of a program, a command decode circuit for decoding a microcode stored at an address indicated by the program counter and distributing it to a data code and a command code, and the command decode circuit. A data buffer circuit for storing a data code of the command code, a command buffer circuit for storing a command code from the command decode circuit, and a command management section for storing information about a command from the command buffer circuit. When it is possible to execute a 1-word instruction consisting of 1 word and a 2-word instruction consisting of 2 words of the command code, when the command code is a 1-word instruction, the bit functioning as parity is a 2-word instruction. of Microprocessor characterized by being an instruction code when the first word.