JPH04137138A - Information processor - Google Patents

Abstract

PURPOSE:To perform the same high-speed processing as execution of an instruction which does not have plural complementary codes by providing a means for switching between effective complementary codes and ineffective complementary codes. CONSTITUTION:When the instruction set to an instruction register 1 has not complementary codes, a field V of an operation code decoder 3 is '0', and a selector 5 outputs a field B of this decoder 3. When this instruction has complementary codes, the field V of the address corresponding to the instruction in the operation code decoder 3 is '1', and the selector 5 outputs the output of a complementary code decoder 4. Consequently, it is unnecessary to indicate memory access or exceptional detection by a microprogram thereafter because the output of the complementary code decoder 4 is given as control information of the field B even in the case of the instruction having complementary codes.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides an instruction word that includes an operation code that indicates the operation to be performed by the instruction and, in some cases, a complementary code that specifies a more detailed operation. command word,
The present invention relates to an information processing apparatus having an operation code decoder that is executed and configured by a plurality of fields indexed by operation codes and having various control functions.

[Conventional technology]

Conventionally, this type of information processing device uses an operation code (
A memory decoder called an operation code decoder (hereinafter referred to as an operation code decoder) is provided to execute the operation specified by the operation code (hereinafter referred to as an operation code).The operation code decoder indexed by the operation code in the instruction register that holds the instruction word is It consists of a field that controls address generation, a field that controls memory access, a field that controls exception detection, a field that controls microprogram startup, etc., and contains information in advance to provide optimal control for each instruction. is written. On the other hand, in addition to the usual instruction word in which one operation is assigned to one opcode, instructions such as input/output instructions, stack manipulation instructions, control instructions, etc. are grouped together and one opcode is assigned to each instruction group, for example. In the case of a group of input/output instructions, detailed types such as input instructions, output instructions, and input/output device initialization instructions are specified by a complementary code provided in the instruction word.

[Problem to be solved by the invention]

When executing instructions with multiple complementary codes in such conventional information processing devices, even if the instructions are assigned to the same opcode, the memory access, presence or absence of exception detection, type, etc. will differ depending on the complementary code. The operation code decoder does not perform memory access or exception detection, but only starts the microprogram, and the activated microprogram identifies the complementary code and performs memory access and exception detection appropriate for each instruction. Giving instructions and carrying out orders. For this reason, instructions having a plurality of complementary codes have the drawbacks of slow execution speed and increased microprogram capacity.

[Means to solve the problem]

In order to eliminate the above drawbacks, the information processing apparatus of the present invention includes a V field indicating that the instruction has a complementary code and a C field used as index control information when there are multiple instructions having the complementary code. An operation code decoder having an operation code decoder, all or part of the bits in which an operation code and conjunctive code may exist in an instruction register that holds an instruction word, and bits in the C field of the operation code decoder are input, and an encoding corresponding to the input is performed. an encoding means for generating an output, a complementary code decoder used when there is a complementary code in an instruction word according to V field information outputted by the operation code decoder, the operation code decoder and the complementary code decoder; It has means for switching each of the outputs of the fields that control the same control object included in both of the fields between cases where the complementary code is valid and cases where the complementary code is not valid.

The information processing device of the present invention also includes an operation code decoder used when there is no complementary code, an operation code of an instruction register that holds instruction words, and all or all of the complementary codes when there are multiple complementary codes. , an encoding means for inputting and encoding some bits, and a complementary field indexed by the output of the encoding means, which consists of fields having the same function as some fields of the opcode decoder.
A code decoder compares the operation code with a predetermined instruction to determine the validity of the complementary code, and outputs an output of a field commonly included in both the operation code decoder and the complementary code decoder. It has means for switching between cases where it is effective and cases where it is not.

〔Example〕

Next, the present invention will be explained with reference to the drawings. FIG. 1 is a block diagram showing a first embodiment of the present invention, which is composed of an instruction register 1, an encoder 2, an operation code decoder 3, a complementary code decoder 4, and a selector 5. FIG. 2 is a diagram showing an example of the format of an instruction word handled in the embodiment shown in FIG. A complementary code exists in bits 16 to 19. In FIG. 1, the operation code decoder 3 is a memory decoder that indexes the operation code held in the instruction register 1 supplied via the signal line 101 as an address. The control words stored in the opcode decoder are broadly divided into A, B, V, and C.
Field 4 is used to start the microprogram and perform other controls.

Field B controls memory access and exception detection. Field V is 1 bit, and "0°" is written for a control word indexed by an opcode that does not have a complementary code, and "pa1" is written for a control word that has a complementary code and corresponds to an opcode. . If there are multiple instructions with complementary codes, field C is numbered by the number of instructions. In the embodiment, a case where there are 5 instructions is shown, and they are 3 bits from 'oooo' to '100', and the write length is set to indicate a fault. complementary
The code decoder 4 is a memory decoder that indexes the encoded output output from the encoder 2 as an address via a signal line 201, and is composed of fields that control memory access and exception detection, similar to field B of the operation code decoder 3. . The selector 5 is connected to the signal line 20
If the control signal given by 2 is “0”, the signal line 204
If the control signal is 1'', the output of field B of the complementary code decoder 4 on the signal line 205 is selected. The last 8 bits of the 12 bits of the given instruction word ccl (complementary code 1) and cc2 (complementary code 2) and 3 bits given via the signal line 207, a total of 11 bits, are encoded into 8 bits. This circuit outputs the signal to the signal line 201.

FIG. 3 is a diagram showing an example of a detailed logic circuit of the encoder 2, including an AND circuit 21, an OR circuit 22, 23, 24.
It is composed of. As shown in FIG. 3, if there are 5 instructions with complementary codes in the signal line 207 sent from field C of the operation code decoder 3 in the embodiment, "'o o o" to ""100"
In FIG. 3, three signal lines 207 are sent out. For example, an instruction with a complementary code such as the operation code "93 '" as shown in FIG.
Assuming that ``93'' is indexed, the signal line sent from field C of the operation code decoder 3 corresponding to ``93'' is ``o''.
o o'', the latter 4 bits (bits 12 to 15) of the complementary code 1 of the instruction word and the 204 bits of the complementary code (bits 16 to 19) are input.For example, if the complementary code 1 is ``''
CA” and complementary code 2 is “4*’”
In this case, the encoded output is "14" and the address "1" of the complementary code decoder 4 in FIG.
4' field B is output. Control information such as memory access and exception detection for instructions with complementary codes is written in advance at the addresses determined in FIG. 7 of the complementary code decoder 4. In FIG. 1, instruction register 1 is set.

If the received instruction has a complementary code, the field ■ of the opcode decoder 3 will be °'0.
The selector 5 outputs field B of the opcode decoder 3. Also, if the instruction in instruction register 1 has a complementary code, the field ■ of the address corresponding to the instruction in opcode decoder 3 will be "1".
The selector 5 outputs the complementary code decoder 4.

Therefore, even if the instruction has a complementary code, the control information in field B is given as the output of the complementary code decoder 4, so there is no need to instruct memory access or exception detection later in the microprogram.

FIG. 4 is a block diagram showing a second embodiment of the present invention.

It is composed of an instruction register 1, an encoder 20, an opcode decoder 31, a complementary code decoder 4, a selector 5, and an instruction detection circuit 6 for multiple complementary code target instructions. As in the first embodiment, the format of the instruction word handled by the information processing device of this embodiment is as shown in FIG. A complementary code exists between bits 8 to 15 or bits 16 to 19. In Fig. 4, operation code decoder 3
Reference numeral 1 denotes a memory decoder that indexes the operation code held in the instruction register 1 supplied via the signal line 101 as an address. The control word stored in the operation code decoder 31 is roughly divided into 82 fields A, where field A controls starting the microprogram and other controls, and field B controls exception detection in memory access. . Combimentary code decoder 4 is a memory decoder that indexes the encoded output output from encoder 21 as an address via signal line 201, and is field B of opcode decoder 31.
Similarly, it consists of fields that control exception detection for memory access. The instruction detection circuit 6 for instructions subject to multiple complementary codes compares the opcode sent via the signal line 101 with the opcode of the instruction a subject to multiple complementary codes sent via the signal line 103, and detects the multiple complementary codes. If the instruction is a complementary code target instruction, "1" is sent out via the output signal line 202 of the instruction detection circuit 6. For example, when the opcode of multiple complementary code target instruction a is given as "93", the opcode "9" is sent to the signal line 101.
When a command “B” occurs, as shown in Figure 6,
This indicates that complementary codes ccl and cc2 are included. Therefore, the control needs to be a complementary code. The selector 5 selects the output of field B of the operation code decoder 31 on the signal line 204 if the control signal given through the signal line 202 is 0'0'', and selects the output from the field B of the operational code decoder 31 on the signal line 204, and selects the output on the signal line 205 when the control signal is ``1''.
Field B of complementary code decoder 4 of
Select the output of The encoder 20 receives the command word ccl (complementary) supplied via the signal line 102.
code 1) and cc2 (complementary code 2)
) is a circuit that encodes the latter 8 of the 12 bits into 5 bits and applies the encoded data to the signal line 201.

FIG. 5 is a diagram showing an example of a detailed logic circuit of the encoder 20, including an AND circuit 21, an OR circuit 22.23.2.
It is composed of 4. As shown in FIG. 5, the latter 4 bits (hit 12
15) and complementary code 2, 4 hits (
If bits 16 to 19) are input, for example, if complementary code 1 is CA'' and complementary code 2 or 4*, the encoded output will be 14'' and address 14 of complementary code decoder 4 in FIG. '' field B is pressed. Control information such as memory access and exception detection for multiple complementary code target instructions is written in advance to the address determined in FIG. 6 of the complementary code decoder 4. 4, if the instruction set in the instruction register 1 is not a multiple complementary code target instruction, the output of the instruction detection circuit 6 is "0'" and the selector 5 outputs the field 30 of the operation code decoder 30.
If the instruction in the instruction register 1 is a multiple complementary code target instruction, the output from the instruction detection circuit 6 is ``1'' and the field B of the complementary code encoder 4 is output.
is output by the selector 5. Therefore, even if the instructions are for multiple complementary codes, the control information in field B is given the pressure of the complementary code decoder 4, so there is no need to instruct memory access or exception detection later by the microprogram.

〔Effect of the invention〕

As described above, the present invention enables high-speed processing even when executing an instruction that is subject to multiple complementary codes, using information stored in a complementary code decoder with a small capacity, as well as when executing an instruction that does not have multiple complementary codes. There is an effect that it can be done.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention;
3 is a detailed logic circuit diagram of the encoder 2 in FIG. 1, and FIG. 4 is a diagram explaining an example of the format of an instruction processed in the embodiment shown in FIG. A block diagram showing an embodiment, FIG. 5 is the encoder 20 in FIG.
6 is a diagram showing a list of instructions having multiple complementary codes among the instructions processed in each embodiment, and FIG. 7 is a detailed logic circuit diagram of the encoder circuit 2 shown in FIGS. 3 and 5. , 20 is a diagram showing the correspondence between input and output. 1...Instruction register, 2,20...Encoder, 3,30...Operation code decoder,
4... Complementary code decoder, 5
... Selector, 6... Command detection circuit, 21.
・・・・・・Logic product circuit, 22.23.24・・・・・・
OR circuit.

Claims (1)

[Scope of Claims] 1. An operation code that specifies the type of operation to be executed by the instruction and has a predetermined bit length, and the operation code further specifies the details of the operation and is determined by the operation code. A plurality of control words, each word composed of a plurality of fields each controlling a predetermined control object, are stored in bit positions in the instruction word, each word having a complementary code having a predetermined bit length. In an information processing device having an operation code decoder that is indexed by the operation code of an instruction register that holds an instruction word, when there is a V field indicating that the instruction has a complementary code and there are multiple instructions having this complementary code. C used as its index control information
an operation code decoder for decoding an operation code having a field; all or some bits in which an operation code and complementary code of an instruction register holding the instruction word may exist; and bits of a C field of the operation code decoder; an encoding means for generating an encoded output corresponding to the input, and a complementary code to be used when the complementary code is included in the instruction word according to the V field information output by the operation code decoder. a decoder, and means for switching each output of a field that controls the same control object included in both the operation code decoder and the complementary code decoder between cases where the complementary code is valid and cases where the complementary code is not valid. An information processing device characterized by: 2. It has an operation code that specifies the type of operation to be executed by the instruction and has a fixed bit length. Depending on the operation code, the details of the operation are further specified and the bit position within the instruction word defined by the operation code is specified. an instruction register that stores a plurality of control words each of which is composed of a plurality of fields for executing an instruction word having a complementary code having a fixed bit length, each controlling a fixed control object, and holding the instruction word; In an information processing device having an operation code decoder that is indexed by the operation code, the operation code decoder is used when the complementary code is not present, and the operation code and complementary code of the instruction register holding the instruction word are provided. an encoding means that inputs all or some bits in which a code may exist and generates an encoded output corresponding to the input; a complementary code decoder used when the complementary code is included in the instruction word; Comparing the operation code with a predetermined command to determine the validity of the complementary code, and outputting a field for controlling the same control target included in both the operation code decoder and the complementary decoder. An information processing device comprising means for switching each of the complementary codes between cases where the complementary code is valid and cases where the complementary code is not valid.