JPH05152542A - Storage device and its addressing method - Google Patents

Abstract

PURPOSE:To access a plurality of bit addresses with a minimum number of accessing. CONSTITUTION:A memory array posseses a plurality of memory cells storing bit data respectively. A storage device is accessed at a unit of a word of a specified number of bits. A plurality of addressing means 10 consist of word lines and bit lines which are different in direction respectively. On the other hand, the means 10 have mutually at least different part of connections of the word lines and the bit lines to respective memory cell. Therefore, more than are addressing systems are available that can be accessed at a specified number of bits unit, so that a plurality of bit addresses to be accessed can be accessed with a minimum number of accessings.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention selects a plurality of memory cells, each of which stores bit data, by an addressing means mainly composed of word lines and bit lines having different directions, and selects them in word units of a predetermined number of bits. The present invention relates to a storage device to be accessed, and more particularly, to a storage device and an addressing method for the storage device, in which a multi-bit address to be accessed can be accessed with a smaller number of accesses.

[0002]

2. Description of the Related Art In recent years, progress in semiconductor integrated circuits, such as improvement in integration and development of various design techniques, has been extremely remarkable. Also, with the progress of such semiconductor integrated circuits, digital circuit technology has come to be used in various information processing fields.

In some cases, analog circuits have been used in the past, such as control of machines and various kinds of signal processing, but have been converted into digital circuits. On the other hand, the information processing field of figures and images is a field that has been developed along with the progress of digital circuit technology.

In digital circuit technology, CPU (ce
In addition to active hardware that performs calculations and data processing, such as ntral processing unit), technology for storage devices that store data and digitized information during calculations and processing is also an important factor. There is.

For example, in the signal processing and the image processing, a large amount of data is often handled during the processing, and
The number of accesses to the data being processed tends to increase. Therefore, in the digital processing device that performs these processes, the configuration and performance of the storage device itself and the method of using the storage device have a great influence on the performance of the entire digital processing device.

The method of classifying the storage device includes classification such as presence / absence of volatility and whether the operation is dynamic or static. Moreover, according to the classification according to the access form to a plurality of memory cells in the storage device, RAM (random
access memory) and sequential access memory.

In the RAM, there is one that accesses an arbitrary address in units of a predetermined number of bits. Specifically, it is a storage device in which a plurality of memory cells respectively storing bit data are selected by addressing means mainly composed of word lines and bit lines having different directions, and accessed in word units of a predetermined number of bits. ..

Hereinafter, such a storage device will be referred to as a word access storage device. Further, an address in word units in the word access storage device is hereinafter referred to as a word address. Addresses for all bits that are not restricted to word units are hereinafter referred to as bit addresses.

[0009]

However, in the word access storage device, when a plurality of bit addresses are accessed, if these bit addresses are different words (different word addresses), the storage device is Had to access multiple times.

FIG. 18 is a memory map of an example of the image processing storage device.

In FIG. 18, there is shown a memory map of 4 bits per word, 4 × 16 = 64 words. Further, this image processing storage device is accessed in units of words separated by solid lines, which has 4 bits separated by broken lines.

The allocation order of word addresses and bit addresses in this memory map is as shown in FIG. That is, in FIG. 18, the word address is assigned such that the upper leftmost address is the word address “0” and the lowermost right address is the word address “63”. Regarding allocation of bit addresses, the upper leftmost address is the bit address “0” and the lowermost right address is the bit address “255”.

In the image processing storage device as shown in FIG. 18, the number of times of access when accessing a total of four bit addresses varies depending on the mutual relationship between the respective bit addresses accessed.

For example, in access to a total of four bit addresses having a relationship as shown by the symbol W1 in FIG. 18, all bit addresses can be accessed by one word access. On the other hand, with respect to a total of four bit addresses having a mutual positional relationship as shown by symbol W2 in FIG. 18, a total of four word accesses are performed despite the fact that these bit addresses are adjacent. There must be.

In the image processing storage device, even in the word access storage device, a bit address may be assigned to each pixel of the image to be processed. or,
By accessing such bit address allocation in word units, data of a plurality of pixels are simultaneously accessed to improve throughput.

However, the number of accesses increases with respect to the multi-bit addresses having the mutual relationship as shown by the symbol W2 in FIG.

In image processing, there are many cases in which a plurality of adjacent pixels are collectively handled. In such processing, as shown in FIG.
There are relatively many accesses as indicated by reference numeral W2, and therefore, the number of accesses becomes a bottleneck in shortening the processing time.

Therefore, conventionally, in order to solve such a problem, it is necessary to use a memory chip capable of operating at a higher speed, and there has been a problem in terms of cost.

The present invention has been made to solve the above-mentioned conventional problems, and provides a storage device that can access a multi-bit address to be accessed with a smaller number of accesses and an addressing method therefor. To aim.

[0020]

According to the present invention, a plurality of memory cells, each of which stores bit data, are selected by addressing means mainly composed of word lines and bit lines having different directions, and a predetermined number of words are selected. A memory device accessed in units includes at least two types of addressing means in which at least a part of the word line or the bit line has a different correspondence to each memory cell, and the plurality of memory cells are selected. The above problem is achieved by using a plurality of address systems. In addition, this invention of this application is hereafter called 1st invention.

By sharing at least a part of the input / output ports of the plurality of address designating means, the above-mentioned problems are achieved and the number of input / output and the number of output buffers of the storage device are reduced. It is a thing.

Further, the number of the address designating means is two, and the address allocation of one of the address designating means is
For address allocation of the other address specifying means,
By having an orthogonal relationship, the above-mentioned subject was achieved.

Further, at least a part of the wiring of the word line or the bit line is shared by the different addressing means, thereby achieving the above-mentioned object, and
This is intended to improve the degree of integration.

Furthermore, by providing the same number of bits as one word, it is possible to simultaneously access a plurality of words in units of the number of bits, which has achieved the above object.

Further, according to the present invention, in the addressing method for the storage device, selection of an addressing means to be used, row addressing of K bits and column addressing of L bits are performed to perform the row processing. The object is achieved by simultaneously accessing adjacent m-bit addresses in the direction according to the selection of the addressing means, including addresses specified by the addressing and the column addressing. is there. In addition, this invention of the present application,
Hereinafter, this is called the second invention.

[0026]

In a memory device having a plurality of memory cells for respectively storing bit data, a predetermined bit address is selected and accessed by addressing means mainly composed of word lines and bit lines having different directions. Further, the word access storage device is also accessed by specifying the word address by the addressing means mainly including the word line and the bit line having different directions. Some such word access storage devices also allow bit address selection by addressing means mainly for word lines and bit lines having different directions.

Hereinafter, the address designating means mainly composed of word lines and bit lines having different directions will be simply referred to as address designating means.

The first invention of the present application is provided with at least two kinds of such addressing means.

That is, at least two types of addressing means are provided, in which at least some of the word lines or bit lines have different correspondences to the respective memory cells. Such a plurality of address designating means are configured corresponding to the mutual relationship of a plurality of bit addresses that are simultaneously accessed to the storage device. For example, the correspondence of the word line and the bit line to each memory cell is determined according to the mutual relation of a plurality of bit addresses that are simultaneously accessed.

Therefore, according to the present invention, the multi-bit address to be accessed can be accessed with a smaller number of accesses.

For example, a first line in which a word line or a bit line is associated with each memory cell so that simultaneous access (word access) to a plurality of interrelated bit addresses as shown by the symbol W1 in FIG. 18 can be performed. Address designating means and second address designating means in which word lines and bit lines are associated with respective memory cells so as to enable simultaneous access (word access) to a plurality of interrelated bit addresses as indicated by symbol W2. And prepare for.

In such a case, it is possible to solve the problem described above with reference to FIG. 18 that the number of accesses increases when accessing the multi-bit address indicated by the symbol W2. That is, all the bit addresses can be accessed with one word access even for the multiple-bit address with the code W2.

FIG. 1 is a block diagram showing the gist of the present invention.

In FIG. 1, the memory array 30 is
It is an array of a plurality of memory cells that respectively store bit data. In the first invention of the present application, a plurality of addressing means 10 are provided for such a memory array 30.

A word address for accessing the memory cells in the memory array 30 in word units is input to the address designating means 10. Further, the address designating means 10 selects the memory cells in the memory array 30 in units of words of a predetermined number of bits in accordance with the address input. The selected memory cell is externally accessed via the addressing means 10.

A plurality of such addressing means 10
The correspondence of at least some of the word lines or bit lines to each memory cell differs between the addressing means 10.

Therefore, when a plurality of different bit addresses in the memory array 30 are accessed at the same time, it is attempted to access them by using one of the address designating means 10 capable of accessing a larger number of these bit addresses at the same time. The multi-bit address to be accessed can be accessed with a smaller number of accesses.

The second invention of the present application is an addressing method for the first aspect of the first invention. This addressing method will be described in detail in the second addressing method of the embodiment described later.

[0039]

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a block diagram of the first embodiment of the present invention.

In FIG. 2, reference numerals 10 and 30 correspond to the same reference numerals in FIG.

In the first embodiment, a plurality of address designating means 10 are housed in the address designating circuit 12.

In the address designating circuit 12, at least a part of the input / output ports with respect to the outside of the storage device of the first embodiment of each of the plurality of address designating means 10 stored therein is shared. That is, in the address designating circuit of the first embodiment, for any of the plurality of address designating means 10, the address input or the like designated by the reference sign F1 or the sign F
A means for selectively connecting external access (input / output word data) indicated by 2 is provided.

This selectively connecting means is, for example, an address converter or the like for the address input F1 and a multiplexer or the like for the external access F2.

According to such a first embodiment, the first
It is possible to reduce the number of inputs / outputs and the number of input / output buffers of the storage device of the embodiment. For example, when the memory device is a semiconductor memory device housed in a predetermined package, it is possible to reduce the number of frame pins on the package and downsize the package.

FIG. 3 is a block diagram of the second embodiment of the present invention.

The 2 ^M word storage device 3 shown in FIG.
Is a storage device capable of simultaneously accessing a total of 2 ^M words of 8 bits per word.

The eight storage devices 1 in total included in the 2 ^M word storage device 3 may be the storage devices of the first embodiment. Alternatively, it may be the storage device of the third to sixth embodiments of the present invention described later, and may be any storage device that can simultaneously access 2 ^M bit addresses as words.

In the second embodiment shown in FIG. 3, 2 ^M
Storage device 1 capable of simultaneously accessing individual bit addresses
By providing only the number of bits constituting one word (8 bits / word in the second embodiment), a plurality of words (2 ^M words) having the bit number can be simultaneously accessed. That is, a total of 2 ^M words of 8-bit words can be simultaneously accessed.

FIG. 4 is a block diagram of the third to sixth embodiments of the present invention.

The third embodiment of the present invention uses the memory cell of FIG. 7 as the memory cell of the memory array 30 of FIG. 4 (connection is as shown in FIG. 6). The fourth embodiment uses the memory cell of FIG. 9 (the connection is shown in FIG. 8).
As of). The fifth embodiment uses the memory cell of FIG. 11 (connection is as shown in FIG. 10). The sixth embodiment uses the memory cell of FIG. 13 (connection is as shown in FIG. 12).

In these embodiments shown in FIG. 4, the number of address designating means is two, and the address allocation of one of the address designating means is relative to the address allocation of the other address designating means. , Are in an orthogonal relationship.

Hereinafter, these two address designating means will be referred to as the first address designating means and the second address designating means, respectively.

That is, the first addressing means mainly comprises a decoder 14a, a multiplexer 16a, a word line relating to the decoder 14a, and the multiplexer 1a.
6a and the bit line for 6a. The second addressing means mainly includes a decoder 14b,
It is composed of a multiplexer 16b, a word line for the decoder 14b, and a bit line for the multiplexer 16b.

The upper input address AH and the lower input address AL input to the memory device of this embodiment are the decoders 14a, 14b and the multiplexers 16a, 16b.
Are translated and distributed using the address translator 18.

When converting and distributing the address of the address converter 18, the address system selection signal AS input to the storage device is used.

Further, this embodiment (third to sixth embodiments).
The multiplexer 17 included in the multiplexer 17 has output data DH from the multiplexer 16a according to the horizontal access selection AH and the vertical access selection AV from the address converter 18, or a multiplexer having an orthogonal relationship with the output data DH. One of the output data DV from 16b is selected and output as the output data D of the storage device.

FIG. 5 is a circuit diagram of an address converter used in the third to sixth embodiments.

The address translator shown in FIG. 5 is used as the address translator 18 of the storage device shown in FIG.

The address converter 1 shown in FIG.
8 inputs the address system selection signal AS, the high-order input address AH, and the low-order input address AL, which are input by the storage device of this embodiment.

The address converter 18 also outputs a lateral access selection AH from the address system selection signal AS via the buffer 52. A vertical access selection AV is output from the address system selection signal AS via the inverter 50.

The horizontal access selection AH is the first access
When accessing using the addressing means, the H state is set. On the other hand, the vertical access selection AV is the second access
When accessing using the addressing means, the H state is set.

The address converter 18 shown in FIG. 5 directly outputs the upper input address AH and the lower input address AL to form a horizontal access word address AWH and a vertical access word address AWV.

Further, the number of bits of the upper input address AH is set to LH, and the number of bits of the lower input address AL is set to LH.
Letting L be M and the number of bits (number of bits per word) that are simultaneously accessed in the storage device be M, the address converter 18 uses the vertical access bit address ABV and the horizontal access word as follows. The address ABH is output.

That is, the address converter 18 outputs the upper (LH-M) bits of the upper input address AH as the vertical direction access bit address ABV.
Further, the address converter 18 is configured to detect the lower input address A
The upper (LL-M) bits of L are output as a horizontal access bit address ABH.

The horizontal access selection AH is made up of the decoder 14a and the multiplier 16a shown in FIG.
And the multiplexer 17 are used. The vertical access selection AV is used by the decoder 14b, the multiplexer 16b, and the multiplexer 17 shown in FIG.

The horizontal access word address AW
H is used in the decoder 14a. The vertical access bit address ABV is used by the multiplexer 16b. The vertical access word address AWV is used by the decoder 14b. The horizontal access word address ABH is used by the multiplexer 16a.

FIG. 6 is a schematic connection diagram of a decoder, a multiplexer and each memory cell in the third embodiment.

In FIG. 6, the decoders 14a and 14b described above with reference to FIG. 4 and the multiplexer 16a are used.
, 16b, and a part of each is schematically illustrated. Further, FIG. 6 shows one memory cell 32 among the plurality of memory cells each storing bit data in the memory array 30 of FIG.

The memory cell 32 shown in FIG.
Is the i-th memory cell from the left and the j-th memory cell from the top among the plurality of memory cells arranged on the matrix of the memory array 30.

In FIG. 6, the first addressing means is a decoder 14a, a multiplexer 16a, a word line HWj, and a bit line pair HBi- (HBi bar). The second addressing means includes a decoder 14b, a multiplexer 16b, a word line VWi, and a bit line pair V.
Bj- (VBj bar).

Each of the word lines HWj and VWi is connected to the output of the output buffer inside the decoder 14a or 14b. Also, the bit line pair H
Bi- (HBi bar) and VBj- (VBj bar) are connected using bidirectional buffers provided inside the multiplexer 16a or 16b, respectively. This bidirectional buffer is formed by connecting the inputs and outputs of two tristate buffers to each other, and the signal transmission direction can be selected according to the write access or read access of data in the memory device of the embodiment. There is.

FIG. 7 is a circuit diagram of a memory cell used in the third embodiment.

The memory cell shown in FIG. 7 is shown by reference numeral 32 in FIG. Further, the word lines HWj and VWi of FIG. 7 and the bit line pair HBi- (HBi
6) and VBj- (VBj bar) are connected to those having the same reference numerals in FIG.

In the memory cell shown in FIG. 7, bit data is held by a total of two inverters 50.

When the memory cell is selected during the access by the first addressing means, both N-channel MOS transistors TN31 and TN32 are turned on. On the other hand, at the time of access by the second addressing means, when this memory cell is selected, both N-channel MOS transistors TN33 and TN34 are turned on.

FIG. 8 is a schematic connection diagram of the decoder, multiplexer and each memory cell in the fourth embodiment.

In the fourth embodiment, as is clear from comparison between FIG. 8 and FIG. 6, the decoder 14b,
The connection between the word line VWi, the multiplexer 16a, the bit line pair HBi- (HBi bar), and the memory cell 32 related thereto is the same as in the third embodiment.

In the fourth embodiment shown in FIG. 8, unlike the third embodiment, the bit line pair VBj-
(VBj bar) and the word line HWj use the same wiring.

Each word line HWj output from the decoder 14a of the fourth embodiment is two word lines independent for each memory cell. That is, two tristate buffers are provided in the decoder 14a for each memory cell, and the output of each tristate buffer is connected to the corresponding word line HWj. These tri-state buffers are the second
It becomes high impedance when accessed by the addressing means.

On the other hand, the multiplexer 16b is provided with two bidirectional buffers for each bit line pair VBj- (VBj bar). This bidirectional buffer provided in the multiplexer 16b is used when accessing by the second addressing means, and the memory cell 32 side is in a high impedance state when accessing by the first addressing means.

FIG. 9 is a circuit diagram of a memory cell used in the fourth embodiment.

In FIG. 9, bit line pair HBi--
The (HBi bar) is connected to the multiplexer 16a, and the word line VWi is connected to the decoder 14b shown in FIG. Also, the word line HWj and the bit line VBj in FIG.
, The word line HWj and the bit line (V
The shared Bj bar) is connected to the decoder 14a and the multiplexer 16b shown in FIG.

When the memory cell shown in FIG. 9 is selected at the time of access by the first addressing means in the fourth embodiment, the total of four N-channel MOS transistors TN41 to TN44 will be changed. Is also turned on.
On the other hand, when the memory cell shown in FIG. 9 is selected at the time of access by the second addressing means, a total of 2 N cells are selected.
Both channel MOS transistors TN45 and TN46 are turned on.

As described above, according to the fourth embodiment, the number of word lines and bit lines can be reduced as compared with the third embodiment.

FIG. 10 is a schematic connection diagram of a decoder, a multiplexer and each memory cell in the fifth embodiment.

In the fifth embodiment, a decoder 14a, a total of two word lines HWj, a multiplexer 16b,
The connection between the bit line pair VBj- (VBj bar) and the memory cell 32 related thereto is almost the same as that in the fourth embodiment, as is apparent from comparison between FIG. 10 and FIG.

In the fifth embodiment, in particular, the bit line pair HBi- (HBi bar) and the word line VWi use a common wiring, as compared with the fourth embodiment.

The decoder 14b of the fifth embodiment has a total of two outputs to the word line VWi for each memory cell. The output to the word line VWi is a tri-state buffer output, which is used only at the time of access by the second address designating means, and has a high impedance at the time of access by the first address designating means. It becomes a state.

The input / output to / from the bit line pair HBi- (HBi bar) of the multiplexer 16a of this embodiment is a bidirectional buffer using a tristate buffer. The bidirectional buffer is used only when the memory cell 32 is selected by the first addressing means,
When accessing with the addressing means, the memory cell 32
The side becomes high impedance.

FIG. 11 is a circuit diagram of a memory cell used in the fifth embodiment.

The wiring in which the word line HWj and the bit line (VBj bar) are shared and the wiring in which the word line HWj and the bit line VBj are shared in FIG. 11 are respectively shown in FIG. It is connected to the decoder 14a and the multiplexer 16b. Further, the wiring shown in FIG. 11 in which the bit line HBi and the word line VWi are shared and the wiring in which the bit line (HBi bar) and the word line VWi are shared are respectively the decoder of FIG. 1
4b and the multiplexer 16a.

When the memory cell of the fifth embodiment is selected by using the first addressing means, all four N-channel MOS transistors TN51 to TN54 are turned on. On the other hand, when selected by the second addressing means, a total of four N-channel MOS transistors TN5 are selected.
All of 5 to TN58 are turned on.

As described above, according to the fifth embodiment, as is clear from the comparison between FIGS. 10 and 8, the number of word lines and bit lines can be reduced as compared with the fourth embodiment. it can.

FIG. 12 is a schematic connection diagram of a decoder, a multiplexer and each memory cell in the sixth embodiment.

The memory cell 32 used in the memory array of the sixth embodiment is a DRAM (dynamic random access).
memory) memory cells are used.

As shown in FIG. 12, the decoder 14
a and 14b output to the word lines HWj and VWi, respectively. For output to these word lines HWj and VWi, an ordinary buffer is used. Further, the multiplexers 16a and 16b are connected to the bit lines HBi and V, respectively.
Input / output to / from Bj. These bit lines HBi, VB
Bi-directional buffers using a total of two tri-state buffers are used for input and output to and from j.

FIG. 13 is a circuit diagram of a memory cell used in the sixth embodiment.

The word line HWj shown in FIG. 13 is
12 is connected to the decoder 14a, and the bit line HBi of FIG. 13 is connected to the multiplexer 16a of FIG. The word line VWi of FIG. 13 is connected to the decoder 14b of FIG. 12, and the bit line VBj of FIG. 13 is connected to the multiplexer 16b of FIG.

In the sixth embodiment, when the memory cell shown in FIG. 13 is selected by the first addressing means, the N channel MOS transistor TN61 is turned on. On the other hand, when the memory cell shown in FIG. 13 is selected by the second addressing means, the N channel MOS
The transistor TN62 is turned on.

In FIG. 13, reference character C is a storage capacity.

As described above, even in the memory device using the DRAM memory cell, according to the sixth embodiment, the present invention is applied to the multi-bit address to be accessed, and the number of times of access is reduced. Can be accessed at.

FIG. 14 is a memory map showing the first addressing method used in the embodiment of the present invention.

This first address designating method uses the address i
By designating the central address F3 designated by the address j and the address j, access is performed in word units of a predetermined number of bits centering on the central address F3. For example, in the case of vertical access, the central address F
This is to access a word having an address i centered at 3 and a total of 2 ^M bits of addresses (j -2 ^M-1 +1) to (j +2 ^M-1 ). On the other hand, at the time of horizontal access, the address j is centered on the central address F3 and the address (i-M / 2
A total of 2 ^M bits of +1) to (i + M / 2) are accessed in word units.

In the first address designating method, the central address F3 (that is, the address of the address i and the address j) is designated for access, but for example, in the case of vertical access, the address is designated. The word may be accessed so that the word having a bit number of 2 ^M is on the upper side of the position, or may be accessed on the lower side. Alternatively, in the lateral access, the word having the number of bits M may be in the left direction or the right direction with respect to the addressed position. The direction of the plurality of bits with respect to the designated address may be any form convenient for the field in which the storage device is used.

FIG. 15 is a memory map showing a lateral access in the second addressing method used in the embodiment of the present invention.

On the other hand, FIG. 16 is a memory map showing vertical access in the second addressing method.

As shown in FIGS. 15 and 16,
In the second addressing method to which the second invention of the present application is applied, a combination of bit addresses to be used as a word at the time of horizontal access is determined in advance. Also, the combination of bit addresses used as words during vertical access is determined in advance.

Even in this second addressing method, the arrangement of each bit is the same as in FIG. That is, horizontal 2 ^L2 bits (pixel) × vertical 2 ^L1 bit (pixel).

FIG. 17 is a data configuration diagram of an address used in the second address designating method.

As shown in FIG. 17A, the second
The external input address in the addressing method is the upper address AH and the lower address AL.

In addition to the upper address AH and the lower address AL, the address system selection AS is also input.
The address system selection AS is an input to the storage device for specifying whether to perform horizontal access or vertical access.

The upper address AH and the lower address A
L has a bit length of L1 and L2, respectively.

Further, as shown in FIG. 17B,
At the time of horizontal access, the upper address AH and part of the lower address AL are used. The lower address AL used at this time is the lower M bits of the input one, but the lower M bits are truncated, and the total bit length is (L2
-M) bits.

When the value of the lower address AL is i and the value of the upper address AH is j, the value of the lower address AL becomes (i / ^2M ) in the lateral access (see FIG. 15). Also, the value of the address used is (j x 2
^(LM) + i / ^2M ).

On the other hand, as shown in FIG. 17C, the lower address AL and a part of the upper address AH are used in the vertical access. The upper address AH used at this time has the lower M bits truncated, and has a total bit length of (LM) bits. Further, as for the address used in this vertical access, the lower address AL becomes the upper address, and the upper address A
Part of H becomes the lower address.

The value of the lower address of the address used in this vertical access is (j / ^2M ). or,
The value of the address used is (i × 2 ^(LM) + j /
2 ^M ).

According to the second address designating method as described above, the same address input can be performed in both the horizontal access and the vertical access.

In the sixth embodiment, the bit length of the upper input address AH and the bit length of the lower input address AL are assumed to be L1 and L2, respectively, but this is the same (L
The same effect can be obtained with 1 = L2). That is,
Both the bit length of the upper input address AH and the bit length of the lower input address AL may be longer than the word length (the number of bits addressed simultaneously) M.

Also, by using (2 ^K ) ² storage devices of this second addressing method, (2 ^{(L1 + K)} × 2
^{(L2 + K)} ) An image memory of pixels can be constructed.

In the second address designating method, an upper-order input address AH having an address length L1 and a lower-order input address AL having a bit length L2 and an address having a total bit length of L1 + L2 and a 1-bit address system selection signal AS are used. Is applied, an address is given to each of a plurality of memory cells that store bit data regardless of the number of bits (word length) M simultaneously accessed in the storage device and the arrangement direction thereof.

In the conventional memory device that accesses in word units having a predetermined number of bits of 2 ^M , addresses are specified in word units, so the total bit length of addresses input to the memory device is (L1 + L2-M) bits. Is.

The second address designating method can also be realized by the address converter 18 shown in FIG.

[0124]

As described above, according to the present invention, it is possible to obtain an excellent effect that a multi-bit address to be accessed can be accessed with a smaller number of accesses.

[Brief description of drawings]

FIG. 1 is a block diagram showing the gist of the present invention.

FIG. 2 is a block diagram of a first embodiment of the present invention.

FIG. 3 is a block diagram of a second embodiment of the present invention.

FIG. 4 is a block diagram of a third embodiment to a sixth embodiment of the present invention.

FIG. 5 is a circuit diagram of an address converter used in the third to sixth embodiments.

FIG. 6 is a schematic connection diagram of a decoder, a multiplexer, and each memory cell in the third embodiment.

FIG. 7 is a circuit diagram of a memory cell used in the third embodiment.

FIG. 8 is a schematic connection diagram of a decoder, a multiplexer, and each memory cell in the fourth embodiment.

FIG. 9 is a circuit diagram of a memory cell used in the fourth embodiment.

FIG. 10 is a schematic connection diagram of a decoder, a multiplexer, and each memory cell in the fifth embodiment.

FIG. 11 is a circuit diagram of a memory cell used in the fifth embodiment.

FIG. 12 is a schematic connection diagram of a decoder, a multiplexer, and each memory cell in the sixth embodiment.

FIG. 13 is a circuit diagram of a memory cell used in the sixth embodiment.

FIG. 14 is a first view used in an embodiment of the present invention.
It is a memory map which shows an addressing method.

FIG. 15 is a second view used in an embodiment of the present invention.
It is a memory map which shows a lateral access by an addressing method.

FIG. 16 is a memory map showing a vertical access in the second addressing method.

FIG. 17 is a data configuration diagram of addresses used in the second addressing method.

FIG. 18 is a memory map of an example of a storage device for image processing.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Storage device, 3 ... M word storage device, 10 ... Addressing means, 12 ... Addressing circuit, 14a, 14b ... Decoder, 16a, 16b ... Multiplexer, 17 ... Second multiplexer, 18 ... Address converter, 30 ... memory array, 32 ... cell, 50 ... inverter, 52 ... buffer, AH ... upper input address, AL ... lower input address, AS ... address system selection signal, AH ... horizontal access selection, AV ... vertical access selection, AB , ABH, ABV ... Bit address, AW, AWH, AWV ... Word address, C ... Storage capacity, HBi, HBi bar, VBj, VBj bar ... Bit line, HWj, VWi ... Word line, D, D1 to D8, DH, DV ... Output data, BD1, BD2, BD3 ... BDM ... External output data, LH ... Upper input The number of address lines, LL ... the number of lower input address lines, M ... the number of the output data.

Claims (6)

[Claims] 1. A storage device in which a plurality of memory cells for respectively storing bit data are selected by an addressing means mainly composed of word lines and bit lines having different directions and accessed in word units of a predetermined number of bits, At least two types of addressing means having different correspondences to each memory cell of at least a part of the word line or the bit line are provided, and a plurality of address systems for selecting the plurality of memory cells are provided. A storage device characterized by. 2. The storage device according to claim 1, wherein at least some of the input / output ports of the plurality of addressing means are shared. 3. The address assigning means according to claim 1, wherein the number of the address assigning means is two, and the address assignment of one of the address assigning means is orthogonal to the address assignment of the other address assigning means. Storage device characterized by becoming. 4. The wiring according to claim 1, wherein at least a part of the word line or the bit line is
A storage device which is shared by different addressing means. 5. A storage device comprising the storage device according to any one of claims 1 to 4 for the number of bits forming one word. 6. The addressing method for a storage device according to claim 3, wherein the addressing means to be used is selected, the L1 bit row address is designated, and the L2 bit column address is designated, and the row address is designated. An address designating method, comprising: simultaneously accessing adjacent 2 ^M- bit addresses in a direction according to the selection of the addressing means, including addresses designated by designation and column addressing.