JPS6318227B2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a storage device, and by accessing a large amount of data in parallel, data can be written and read efficiently, and only specific bits can be arbitrarily written without affecting surrounding bits. The purpose of the present invention is to provide a storage device in which data can be written.

Image memories that digitize images and write the information in a storage device have been known in the past, but in such image memories, one pixel is divided into red (R), green (G), and blue. (B) Light 3
3 bits of primary colors (when each primary color is binarized), N bits (when ^2N gradations are set for black and white), or N x 3 bits (when ^2N gradations are set for each primary color) ), etc., and many bits are required. In addition, considering the resolution of the pixels themselves, the screen size is 256 x 256 to 1024.
It is divided into a large number of pixels such as ×1024. Therefore, the amount of data in the image memory becomes extremely large.

For example, if the screen is divided into 256 x 256 pixels, R,
Considering an image memory that binarizes the three primary colors G and B, normal memory is structured in bytes, so 256 x 256 (= 65536 bits) is equivalent to 8k bytes, and for example, addresses 0 to 8191. are assigned as access addresses for red (R) data, addresses 8192-16383 for green (G) data, and addresses 16384-24575 for blue (B) data. Therefore, 8 pixels of 1 color correspond to 1 address, and 3 pixels of R, G, and B
All data of eight pixels will be expressed by a combination of two addresses. It is also assumed that the above 256×256 pixels are allocated on the memory as shown in FIG. In other words, take 8 bits horizontally from the top left,
This is regarded as 1 byte, and a horizontal line is displayed using a total of 32 bytes.

When attempting to write certain image data to the above image memory, calculate which address of the 8K bytes from the pixel position and which bit within that address, and write "1" to that bit. ” or “0” (to three R, G, B image addresses), one pixel of data can be written, so by writing data three times to three R, G, and B addresses, Data for 8 pixels can be stored. However, these 8 pixels are in one row horizontally, and when writing a single vertical line, only one of the 8 pixels is valid, and the remaining 7 pixels are unrelated to the image that is currently being written. . Therefore, if you store the remaining 7 pixels as all "0", the previously written image will be erased, and if you store them as "1", all will be written (color Therefore, when writing a single vertical line, first read out 8 pixels of data, create data by replacing only the bits of the pixels you want to newly write to the old data, and then write the data. You have to take steps to write it down. For this reason, in the worst case, conventional image memory requires three readouts (R, G,
(1 time each for B) and 3 writes (1 time each for R, G, B)
The problem was that it took a lot of time.

Conversely, if you want to know the contents of a pixel at a certain position, you need to read it three times, once each for R, G, and B, and check 24 (=8 x 3) bits after reading. Therefore, data such as color information of the target pixel had to be determined.

In this way, with conventional image memory that allocates 256 x 256 x 3 bits to a total of 24 kbytes of memory, a total of 6 memory accesses are required: 3 times for reading, and 3 times for writing after 3 times of reading. However, they required logical operations and were inefficient.

In addition, as other conventional storage devices, 256 x 256 x 3
There was also an image memory that allocated 64k words of memory, with each word consisting of 3 bits (1 bit each for R, G, and B). According to this image memory, 1
Since the address is 1 pixel, it is possible to write only the data of the target pixel regardless of the pixels surrounding the target pixel, and moreover, in one write, R, G, B
Each bit can be stored. Furthermore, when reading, all data can be read in one read.

However, according to this conventional image memory, data for only 3 pixels can be read out even if the data is read out 3 times (with the conventional image memory described above, data for 8 pixels can be read out in 3 times). When rewriting the data, the conventional image memory mentioned above only requires accessing 24k words, but this conventional image memory requires accessing 65k words, which has the disadvantage of taking a long time to access. It was hot. Additionally, if this image memory can also be used as central processing unit (CPU) memory, 64k words means a 16-bit address, thus occupying the entire 16-bit address space of a normal CPU. There was a drawback.

The present invention eliminates the above-mentioned drawbacks,
One embodiment will be described below with reference to FIGS. 2 and 3.

FIG. 2 is a block system diagram of an embodiment in which the storage device according to the present invention is used as an image memory.
FIG. 3 shows a circuit diagram of an embodiment of a main part of a storage device according to the present invention. In FIG. 2, reference numeral 1 denotes a book having a logic circuit group (none of which is shown) to which storage modules 2a, 2b, and 2c of predetermined bits are connected, and further includes a data conversion circuit and an AND circuit, which will be described later, on the readout output side. This image memory 1 is an example of a storage device according to the invention, and the image memory 1 further includes a select register 3 and a data register 24.

5 is the central processing unit (CPU), and data bus 6
A read timing signal RD, a store instruction timing signal WR, and an address designation signal are appropriately supplied to the storage modules 2a, 2b, and 2c through the memory modules 2a, 2b, and 2c. Furthermore, the data register 24 is supplied with an auxiliary data signal for writing data into or reading data from predetermined bits of the storage modules 2a, 2b, and 2c.

Here, the one-pixel one-address method (a method in which the target pixel data can be written regardless of other pixels, and all the pixel data can be loaded in one readout) is preferable for data processing. In order to access many pixels with a small number of instructions, the 1-address multiple pixel method is preferable. The present invention is not based on any of these methods,
This is a storage device that combines the advantages of both types.

Now, to explain the case where the present invention is applied to an R, G, and B image memory of 256×256 pixels, the storage modules 2a, 2b, and 2c are each
For R and G, consisting of 8k bytes x 8 bits
The same address designation signal is supplied from the CPU 5 to the 13-bit address line of each 8k byte. That is,
One piece of color information is determined by data at the same address in each of the storage modules 2a, 2b, and 2c. In addition, a module select signal is supplied from the select register 3 to the three storage modules 2a, 2b, and 2c through three independent buses, and only when this module select signal is "1", the storage module is It becomes possible to write to and read from. Furthermore, three auxiliary data signals are supplied from the data register 4 to the storage modules 2a, 2b, and 2c via three independent buses, and these auxiliary data signals are referenced when writing and reading the storage modules. The data will be These six signals in total can be easily changed by a program.

The pixel data read out from the storage modules 2a, 2b, and 2c is supplied to the CPU 5, and after being subjected to predetermined signal processing by the signal processing circuit 7, is monitored by the monitor receiver 8.

Next, the operation of the present invention apparatus will be explained in more detail with reference to the circuit diagram of the main part of the present invention apparatus shown in FIG. The circuit shown in FIG. 3 shows a logic circuit group having one of the storage modules 2a, 2b, and 2c shown in FIG. 2, a data conversion circuit, and an AND circuit. In FIG. 3, 9 ₁ to 9 ₈ are random access memories (RAM) formed into ICs, each having a storage capacity of 8 kbytes x 1 bit, and each having an independent store instruction timing signal input terminal WR, It has a chip select terminal CS, a data input terminal DI, and a data output terminal DO. Further, 10 is a read timing signal RD input terminal, 11 is a decoder output signal input terminal for the upper 3 bits of the CPU 5, 12 is a module select signal input terminal from the select register 3, and 13 is an auxiliary data signal input terminal from the data register 4. It is. The input terminals 11 and 12 are connected to one input terminal of an AND gate 15 via an AND gate 14, and are also connected to chip select terminals CS of RAMs ₉₁ to ₉₈ . Above input terminal 1
The input signal of No. 1 is "1" during the write or read operation of the storage module No. 1, and therefore the module select signal input to the input terminal 12 is "1".
When , this storage module is selected.
RAM _{9 1} to 9 ₈ are enabled for writing or reading operations, and on the other hand, when the module select signal is “0”, RAM _{9 1} to 9 ₈ cannot be written or read regardless of the timing signals WR and RD. Operation is prohibited.

First, to explain the write operation, the input auxiliary data signals of the storage modules 2a, 2b, and 2c are set to "1" or "0" depending on the color information to be written. For example, when writing white, all the auxiliary data signals are set to "1", and when writing yellow, only the auxiliary data signals applied to the R and G storage modules 2a and 2b are set to "1". When writing blue, only the auxiliary data signal applied to the B storage module 2c is set to "1" and the others are set to "0". Therefore, when the circuit shown in the third figure is the R storage module 2a, the RAM is connected to the input terminal 13.
The auxiliary data signal supplied to each data input terminal DI of 9 ₁ to 9 ₈ becomes "1" when writing white, yellow, magenta, red, etc.

On the other hand, the module select signal outputted from the select register 3 selects a storage module to perform a write operation when it is "1". Therefore, when a module select signal of "1" is applied to all of the memory modules 2a, 2b, and 2c, all of them can perform a write operation, and if it is desired to rewrite only the red memory contents (the rest When the green and blue memory contents are not changed)
In this case, only the module select signal supplied to the R storage module 2a becomes "1".

Furthermore, the pixel to be written is designated using a 13-bit address designation signal and an 8-bit data line. That is, a desired byte from the 1st byte to the 8192nd byte, that is, the condensed bits of the desired 8 pixels, is specified using a 13-bit addressing signal, and the 8 bits corresponding to the specified 8 pixels are written. The bit position you wish to insert is “1”
Then, a total of 8 bits of data D ₀ are set to "0" in the bit positions that are not desired to be written (not changed).
~ _D7 is stored at the address specified by the 13-bit addressing signal. In the circuit shown in FIG. 3, the data D ₀ to D ₇ and the timing signal WR of the store command are supplied to AND gates 16 ₁ to 16 ₈ , respectively, and the logical AND is performed here, thereby determining the data D to be stored. The timing signal WR of the store instruction is taken out only from the AND gate to which the data of the " _{1 "} bit among the RAMs ₉₁ to 98 is input, and is applied to the input terminal WR of the corresponding RAM among the RAMs 91 to ₉₈ . At this time, the auxiliary data signal supplied from the input terminal 13 to the data input terminal DI is written into the RAM.

In this way, it is not only possible to write data to all 8 bits representing a set of 8 pixels at a desired position, but also to write data to bits corresponding to 1 to 7 specific pixels without affecting the bits of surrounding pixels. Color information data can be written with a single store command. To write color information data for the entire screen,
This is possible with an 8k word store instruction (however,
(When they are all the same color) According to this embodiment,
By performing parallel access, a maximum of 24 bits (=3×8) of data can be written with one store instruction, and therefore, in this case, the access time is 1/3 that of the conventional device.

According to this embodiment, as described above, the storage modules 2a, 2b, and 2c can specify arbitrary addresses using the same address designation signal, but these are the same addresses, and color information of one desired pixel can be specified. is obtained by a combination of three pieces of data respectively written to the same address of these three storage modules. However, by setting only one bit of both the module select signal and write data to “1” and the rest to “0”, 256
It is also possible to write data to only one arbitrary bit of x256 x 3 bits.

In other words, during a write operation, the
Using the storage device with the configuration shown in the figure, selective writing in bit units is performed using the above write data, so when writing data for which information such as color, shading, audio level, etc. When writing data divided into categories, such as by color, shading, or audio level, a maximum of 1
Since it is possible to write data with a number of bits equal to (number of storage modules) x (number of bits of specified address) in one cycle, data input and transfer can be performed at higher speed than with conventional devices, and moreover, it can be done in parallel. Storing data with a smaller number of bits than the maximum number of bits that can be stored in a bit can be specified and written independently without changing the remaining bits, so that a particular bit can be stored without affecting the surrounding bits. Since data can be written to the memory and there is no need to switch modes in word units or bit units, the circuit configuration is simple. In the case of writing, the auxiliary address signal can be set only once, and then the auxiliary address signal can be set only once. Faster operation is possible compared to those that require updating.

Next, the read operation will be explained. In this embodiment, two modes of read are possible. 1st
The mode specifies the color to be read out, and the pixel data of the specified color is read out as "1".
Pixel data of colors other than the specified color are read out as "0". In the second mode, as with conventional reading, one of R, G, and B is designated and data of the designated color is read out from the storage module. Note that by combining these first and second modes, it is possible to read out partially specified colors (for example, colors whose constituent elements are yellow (yellow, white)).
) can also be read out.

The color designation read operation described above is performed as follows. First, a specified color is set in the data register 4, and the module select signals supplied from the select register 3 to the storage modules 2a, 2b, 2c are all set to "1" in principle. then 13
A set of eight pixels is designated by a bit addressing signal and the pixel data is read out. The pixel corresponding to the "1" bit in the read data is the same pixel as the designated color. It should be noted that among the above three module select signals, for example, R
When the module select signal supplied to the memory modules 2a and 2b for B and G is "1" and the module select signal supplied to the B memory module 2c is "0", only R and G must match. If this is the case, it will be "1", and B will not be checked, allowing readout using the specified color of the portion.

On the other hand, the reading operation of the storage module for each color is performed as follows. First, the output auxiliary data signal of data register 4 is set to "1",
Only the module select signal supplied to the storage module of the designated color is set to "1", and the other two module select signals are set to "0". Next, a set of 8 pixels is specified using a 13-bit addressing signal and the pixel data is read out. These read pixel data are the data of the storage module of the specified color. Note that if the auxiliary data signal is set to "0", data can be read out with negative logic (data "1" and "0" are opposite to the above).

The above read operation is performed as follows. RAMs 9 ₁ to 9 ₈ shown in the third diagram are AND gates 14
When the module select signal is “1”,
A total of 8 bits of data corresponding to the designated address is output to each data output terminal DO. This 8-bit output data is supplied to the corresponding 2-input exclusive OR circuits 17 ₁ to 17 ₈ , where it is exclusive ORed with the auxiliary data signal from the input terminal 13 and converted into data. 2-input NAND gate 18 ₁ ~ 1
8 is supplied to one input terminal of ₈ , respectively.

The other input terminals of the NAND gates 18 ₁ to 18 ₈ are supplied with the output signal of the AND gate 15 which receives the read timing signal RD from the input terminal 10 and the module select signal from the AND gate 14, respectively. Therefore, NAND gate 1
Each output data D ₀ to D ₇ of 8 ₁ to 18 ₈ has a module select signal of “1” and is stored in RAM _{9 1} to 9 _{8 .}
When the read data and the auxiliary data signal match, it becomes "1", and when they do not match, it becomes "0". Also, when the module select signal is “0”
Each output data D ₀ ~ of NAND gates 18 ₁ ~ 18 ₈
All _D7 's become "1".

Here, the output sides of the other two storage modules also have exclusive OR circuits 17 ₁ to 17 for data conversion.
17 ₈ and NAND gates 18 ₁ to _{18 8} are mounted, respectively.
Since the outputs of ₁₈₈ are open collector outputs and are all connected to the same data bus, wired AND is performed on this data bus, and the outputs of the three storage modules 2a, 2b, and 2c are all "1".
Data of "1" is read only when this is the case. That is, the output terminal of the NAND gate ₁₈₁ corresponds to the NAND gate ₁₈₁ provided on the readout output side of the other two storage modules.
If it is wired and connected to the output terminal of the gate and all three storage modules are selected by the module select signal,
A “ ₁ ” is output only when the outputs of these three NAND gates containing 181 are all “1” (this indicates that the read data and auxiliary data match in each of the three storage modules). This is one of the eight pixels at the specified address.
This becomes pixel read data. Similarly, other
The NAND gates 18 ₂ to 18 ₈ and the corresponding NAND gates provided on the read output sides of the other two storage modules are wired and connected.

In this way, the three storage modules 2a, 2
Of the total 24 (=3×8) data read from the three storage modules 2a, 2b,
Since the three read data of each corresponding bit of 2c match the auxiliary data, read data of "1" is extracted only for the bit for which the output of the NAND gate is "1". Further, when any one of the three NAND gate outputs of the corresponding bits of the three storage modules 2a, 2b, and 2c is "0", the read data of that bit becomes "0".

In addition, 18 ₁ to 18 ₈ or equivalent NANDs provided on the readout output side of the storage module to which a module select signal of “0” is supplied.
As mentioned above, the output of the gate is “1”, so even if it is wired and connected,
It is unrelated to the AND function and is provided on the readout output side of the selected storage module.
Only the output of the NAND gate is related to this AND function. In this way, in conventional storage devices, when trying to read only the data of a pixel of a certain color among the 8 pixels, it is possible to read out the data of a pixel of a certain color three times (or In contrast, in this embodiment, the three output auxiliary data signals of the data register 4 are used to select the color to be read (for example, when the color is white, all of the colors are “1”, R for yellow,
The input auxiliary data signal of each storage module 2a, 2b of G is set to "1", and the input auxiliary data signal of 2c is set to "0"), and by reading out the storage module only once, the color specification readout can be performed immediately. data can be obtained.

When accessing by color using the above storage device, all 8 pixels (8 pixels) are read or written once.
x 3 = 24 bits), and when access is not by color, the same access as before is possible by controlling the module select signal, and in addition, it is possible to access data in the same manner as before by controlling the module select signal. (Other pixels and other bits of that pixel)
It is also possible to write it independently.

Note that although the above embodiments have been described with respect to R, G, and B image memories, the present invention can be similarly applied to N-bit grayscale image memories by simply accessing them not by color but by gradation. . The same applies to color or monochrome grayscale image memory. Furthermore, in the above embodiment, the auxiliary data signal from the data register 4 is used as a 1-bit common signal for one storage module, but the signal is not limited to this and can be used as 2 or more bits for each storage module.
It may also be allocated to RAM. Further, the number of storage modules does not need to be three, and it goes without saying that it may be configured with a plurality of storage modules depending on the usage and purpose.

In addition to image memory, the present invention also applies to devices that require 2 or more bits of data for one element,
For example, it can be applied as a digital memory for audio.

As described above, in the storage device of the present invention, one information content is determined by a combination of data at corresponding bit positions in a data string stored at the same address, and the same address is simultaneously specified. a plurality of storage modules configured to provide a plurality of storage modules; an auxiliary data storage circuit that supplies independent auxiliary data signals to each of the storage modules; and a 1-bit selection information storage circuit that supplies a signal, and the module select signal is "1" and the content of read data for each bit of each storage module and the content of the auxiliary data signal are A data conversion circuit that outputs a signal of "1" to a common single bus only when they match is provided for each storage module, and all the module select signals supplied are "1". When the outputs of the data conversion circuits of the data conversion circuits of the storage modules at bit positions common to the storage modules are all "1", the read data at the bit positions is set as "1", and , when any one or more of the outputs of the data conversion circuit at a common bit position is "0", the read data at that bit position is set to "0", and the module select signal supplied is "0". Since a logic circuit group is provided that sets the output of the data conversion circuit of the storage module to "1," when determining the stored data of the storage module by specifying color, shading, or audio level, it can be done with a single read operation. , applications that operate on colors, such as changing one color to another but leaving the remaining colors as they are, are possible with minimal memory access, and the judgment result of the data stored in the storage module described above is possible. The operation of outputting the data to a common single bus and the operation of retrieving the contents of any storage module can be performed automatically without the need for special signals such as mode switching signals, and is particularly suitable for application to image memory. It has many features such as:

[Brief explanation of the drawing]

Fig. 1 is a diagram schematically showing the correspondence between pixel positions and memory addresses, Fig. 2 is a block system diagram showing an embodiment of the storage device according to the present invention used as an image memory, and Fig. 3 is a diagram schematically showing the correspondence between pixel positions and memory addresses. 1 is a circuit diagram showing an embodiment of a main part of a storage device according to the present invention; FIG. DESCRIPTION OF SYMBOLS 1...Storage device, 2a, 2b, 2c...Storage module, 3...Select register, 4...Data register, ₉₁ to ₉₈ ...IC-based RAM, 10...Read timing signal input terminal, 11...Decoder output signal input Terminal, 12...Module selector signal input terminal, 13...Auxiliary data signal input terminal, 17 ₁
~17 ₈ ...Exclusive OR circuit for data conversion.

Claims (1)

[Claims] 1. A plurality of storage modules configured such that one information content is determined by a combination of data at corresponding bit positions in a data string stored at the same address, and the same address is specified simultaneously. , an auxiliary data storage circuit that supplies mutually independent auxiliary data signals to each of the separate storage modules, and a 1-bit selection information storage circuit that supplies mutually independent module select signals to each of the separate storage modules. The module select signal is "1" and is set to "1" only when the contents of the read data for each bit of each storage module and the contents of the auxiliary data signal respectively match. A data conversion circuit for outputting a signal to a common single bus is provided for each storage module, and the output of the data conversion circuit of all storage modules to which the module select signal supplied is "1" is provided. When the outputs of the data conversion circuits at the common bit positions among the storage modules are all "1", the read data at the bit positions is set to "1", and the outputs of the data conversion circuits at the common bit positions are set to "1". It has an AND circuit that sets the read data at the bit position to "0" when any one or more of the outputs is "0", and the data of the storage module to which the module select signal supplied is "0". A storage device comprising a logic circuit group that sets the output of a conversion circuit to "1".