JPH05129635A - Field effect transistor and production thereof - Google Patents

Field effect transistor and production thereof

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Publication number
JPH05129635A
JPH05129635A JP28836691A JP28836691A JPH05129635A JP H05129635 A JPH05129635 A JP H05129635A JP 28836691 A JP28836691 A JP 28836691A JP 28836691 A JP28836691 A JP 28836691A JP H05129635 A JPH05129635 A JP H05129635A
Authority
JP
Japan
Prior art keywords
channel
layer
effect transistor
field effect
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP28836691A
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Japanese (ja)
Inventor
Hiroyuki Eto
浩幸 江藤
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Hitachi Ltd
Original Assignee
Hitachi Ltd
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Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP28836691A priority Critical patent/JPH05129635A/en
Publication of JPH05129635A publication Critical patent/JPH05129635A/en
Pending legal-status Critical Current

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  • Recrystallisation Techniques (AREA)

Abstract

PURPOSE:To provide a high-gain n-type field effect transistor which uses Ge as a channel with improved channel electronic mobility and production thereof. CONSTITUTION:An n-type field effect transistor shown by the figure 1 is provided with a distortion modified Ge/Sn buffer layer 2 and an Si1-xGex layer 3 on a Ge (110) or Ge (111) substrate 1. The transistor is provided with a Ge channel layer 4 and a modulating dope n-Si1-xGex layer 5, which are lattice- aligned with the buffer layer and to which tensile strain is applied, and an Si layer 6. Then, an Si oxide film 7, source and drain areas 8 and 9, a gate electrode 11 and source and drain electrodes 10 and 12 are formed. Thus, the mobility is improved compared with the bulk by permitting the <1-10> direction of Ge to which tensile strain is applied in a direction parallel to the (110) plane to be the channel direction or by permitting Ge to which tensile strain is applied in a direction parallel to the (111) plane to be the channel.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、Geをチャネルとする電
界効果型トランジスタに関し、高利得のn型電界効果型
トランジスタとその製造方法を提供するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor having Ge as a channel, and provides a high gain n-type field effect transistor and a method of manufacturing the same.

【0002】[0002]

【従来の技術】Geをチャネルとするn型電界効果型トラ
ンジスタ(FET)を高利得化するための構造として、n-
SiGe/Geヘテロ構造を有する変調ドープ電界効果型トラ
ンジスタ(MODFET)が知られている(R. People. :
Phys. Rev. B34,2508 (1986))。このトランジスタにつ
いて、図4を用いて説明する。
2. Description of the Related Art As a structure for increasing the gain of an n-type field effect transistor (FET) having a channel of Ge, n-
A modulation-doped field effect transistor (MODFET) having a SiGe / Ge heterostructure is known (R. People .:
Phys. Rev. B34 , 2508 (1986)). This transistor will be described with reference to FIG.

【0003】図4に模式的に示した従来のMODFET
は、Ge(001)基板13上に形成されたn型の変調ドープS
i0.15Ge0.85層14、及びソース,ドレイン電極15,
17、ゲート電極16から構成される。本構造におい
て、電子はn-SiGe層から供給され、n-SiGe/Ge界面のGe
側が電子の走行するチャネルとなるため、電子は不純物
散乱を受けず、2次元的に高移動度で走行することが可
能である。
A conventional MODFET schematically shown in FIG.
Is an n-type modulation doped S formed on the Ge (001) substrate 13.
i 0.15 Ge 0.85 layer 14, source and drain electrodes 15,
17 and a gate electrode 16. In this structure, electrons are supplied from the n-SiGe layer and the Ge at the n-SiGe / Ge interface
Since the side serves as a channel through which electrons travel, the electrons can travel two-dimensionally with high mobility without being subjected to impurity scattering.

【0004】[0004]

【発明が解決しようとする課題】上述のGe(001)をチャ
ネルとするMODFETでは、電子移動度の理想的な最
大値はバルクと同じ約3900cm2/Vsであり、それ以上増加
させることは物理的に不可能であった。
In the above-mentioned MODFET using Ge (001) as a channel, the ideal maximum electron mobility is about 3900 cm 2 / Vs, which is the same as that of the bulk, and increasing it further is physical. Was impossible.

【0005】本発明の目的は、チャネルとなるGeの電子
構造を変えることにより、バルクよりも高い移動度を得
ることができ、ひいては相互コンダクタンス(gm)の大き
な高利得の電界効果型トランジスタを得ることにある。
また、さらにその製造方法を提供することにある。
An object of the present invention is to provide a high-gain field-effect transistor which can obtain a mobility higher than that of a bulk by changing the electronic structure of Ge serving as a channel and thus has a large transconductance (g m ). To get.
Moreover, it is providing the manufacturing method further.

【0006】[0006]

【課題を解決するための手段】上記目的は、変調ドープ
構造において、(110)面に平行な方向に引っ張り歪みを
受けたGeの<1-10>方向をチャネル方向とするか、あるい
は、(111)面に平行な方向に引っ張り歪みを受けたGeを
チャネルとすることによって達成される。
[Means for Solving the Problems] The above-mentioned object is to make the channel direction be the <1-10> direction of Ge that has been subjected to tensile strain in the direction parallel to the (110) plane in the modulation-doped structure, or This is achieved by using Ge strained in the direction parallel to the (111) plane as a channel.

【0007】またその製造方法としては、Geチャネルの
面方向に平行な引っ張り歪みを受けさせるために、Geよ
りも大きな格子定数を有する単結晶バッファー層を形成
し、バッファー層に格子整合させてGeを歪み成長させ
る。ここでは、バッファー層としてGe基板上に形成した
GeとSnからなる超格子層を用いる。
As a method of manufacturing the same, a single crystal buffer layer having a lattice constant larger than that of Ge is formed in order to receive tensile strain parallel to the surface direction of the Ge channel, and the Ge layer is lattice-matched to the buffer layer. Grow strain. Here, the buffer layer was formed on the Ge substrate.
A superlattice layer consisting of Ge and Sn is used.

【0008】[0008]

【作用】まず、(110)面に平行な方向に引っ張り歪みを
受けた歪みGe(110)層の伝導帯の底付近のエネルギー図
を図2に示す。図2に示したように、引っ張り歪みのた
め伝導帯の底の8重縮退が解け、電子は<01-1>、<0-11>、
<10-1>及び<-101>方向の4つのバレイ(図中の斜線部分)
に局在する。ここで、<-h-k-l>は、<hkl>と逆方向を表
す。これらの電子は、<1-10>チャネル方向では、バルク
の有効質量me(≒0.12m0:m0は真空中の電子質量)よりも
軽い有効質量mt(≒0.082m0)を有している。変調ドープ
構造のように、不純物散乱がなくフォノン散乱のみによ
って電子の移動度が決まる場合、移動度は電子の有効質
量の(-5/2)乗に比例する。従って、歪みGe(110)をチャ
ネルとするMODFETでは、電子移動度を最大10000c
m2/Vsまで増加させることが可能となる。
First, FIG. 2 shows an energy diagram in the vicinity of the bottom of the conduction band of the strained Ge (110) layer which is subjected to tensile strain in the direction parallel to the (110) plane. As shown in Fig. 2, due to tensile strain, the 8-fold degeneracy at the bottom of the conduction band is released, and the electrons are <01-1>, <0-11>,
Four valleys in <10-1> and <-101> directions (hatched areas in the figure)
Localized to. Here, <-hkl> indicates the opposite direction to <hkl>. These electrons, <1-10> in the channel direction, the effective mass of bulk m e (≒ 0.12m 0: m 0 is electron mass in vacuum) have a lighter effective mass m t (≒ 0.082m 0) than is doing. When the electron mobility is determined only by phonon scattering without impurity scattering as in the modulation-doped structure, the mobility is proportional to the effective mass of the electron to the (-5/2) th power. Therefore, in a MODFET using strained Ge (110) as a channel, the maximum electron mobility is 10000c.
It is possible to increase up to m 2 / Vs.

【0009】同様に、(111)面に平行な方向に引っ張り
歪みを受けた歪みGe(111)層の伝導帯の底付近のエネル
ギー図を図3に示す。図3に示したように、引っ張り歪
みのため伝導帯の底の8重縮退が解け、電子は<111>及
び<-1-1-1>方向の2つのバレイ(図中の斜線部分)に局在
する。これらのバレイの電子は、(111)面に平行な方向
では有効質量mtを有しているため、(110)面と同様に移
動度を増加させることが可能となる。
Similarly, FIG. 3 shows an energy diagram in the vicinity of the bottom of the conduction band of the strained Ge (111) layer subjected to tensile strain in the direction parallel to the (111) plane. As shown in Fig. 3, due to tensile strain, the 8-fold degeneracy at the bottom of the conduction band is released, and the electrons are divided into two valleys in the <111> and <-1-1-1> directions (hatched areas in the figure). Localize. The electrons of these valleys have an effective mass m t in the direction parallel to the (111) plane, so that the mobility can be increased similarly to the (110) plane.

【0010】以上に述べたような作用によって、歪みGe
(110)チャネルもしくは歪みGe(111)チャネルにおいて、
有効質量を減少させて高移動度、即ち高利得の電界効果
型トランジスタを実現することが可能となる。
Due to the action as described above, the strain Ge
In the (110) channel or strained Ge (111) channel,
It is possible to reduce the effective mass and realize a field effect transistor having high mobility, that is, high gain.

【0011】[0011]

【実施例】以下、図1を用いてMOS型のMODFET
を作製した例について述べる。
EXAMPLE A MOS type MODFET will be described below with reference to FIG.
An example of manufacturing the will be described.

【0012】Geチャネルの面方向に平行な引っ張り歪み
を受けさせるために、Geよりも大きな格子定数を有する
単結晶バッファー層を形成し、バッファー層に格子整合
させてGeを歪み成長させる。ここでは、バッファー層と
してGe基板上に形成したGeとSnからなる超格子層を用い
た例について説明する。
In order to receive tensile strain parallel to the surface direction of the Ge channel, a single crystal buffer layer having a lattice constant larger than that of Ge is formed, and lattice-matched with the buffer layer to grow Ge strained. Here, an example in which a superlattice layer made of Ge and Sn formed on a Ge substrate is used as the buffer layer will be described.

【0013】まず、10Ω・cmのp-Ge(110)基板1を化学処
理した後、分子線成長(Molecular Beam Epitaxy;MB
E)装置内に導入し、基板表面を清浄化する。次に、以
下の手順によって歪み緩和したGe/Sn超格子を形成す
る。基板温度を95℃に設定した後、基板にSnの分子線を
照射して約0.01nm/sの堆積速度でSn原子層を1層形成す
る。Snの表面偏析を押えるために、基板温度を50℃に下
げて約0.01nm/sの堆積速度でGe原子層を8層形成した
後、結晶性を向上させるために、基板温度を230℃に上
げてGe原子層を12層形成する。以上の手順を繰り返し
て、約0.5μmのGe20/Sn1超格子層からなるバッファー層
2を形成する。ここで、Ge20/Sn1超格子層を0.5μmと厚
く形成すると、Ge基板とバッファー層との格子定数差に
よる歪みは緩和され、バッファー層の格子定数はGe20層
とSn1層のほぼ平均の格子定数となり、これはGeの格子
定数に比べて約0.8%大きい。従って、このバッファー層
に格子整合してGe層を歪み成長させると、0.8%の引っ張
り歪みを受ける。
First, after chemically treating the 10 Ω · cm p-Ge (110) substrate 1, molecular beam epitaxy (MB) is performed.
E) It is introduced into the apparatus and the substrate surface is cleaned. Next, a strain-relaxed Ge / Sn superlattice is formed by the following procedure. After setting the substrate temperature to 95 ° C., the substrate is irradiated with a Sn molecular beam to form one Sn atomic layer at a deposition rate of about 0.01 nm / s. In order to suppress the surface segregation of Sn, the substrate temperature was lowered to 50 ° C and eight Ge atomic layers were formed at a deposition rate of about 0.01 nm / s. Then, the substrate temperature was raised to 230 ° C to improve the crystallinity. 12 layers of Ge atomic layers are formed. The above procedure is repeated to form the buffer layer 2 consisting of a Ge 20 / Sn 1 superlattice layer of about 0.5 μm. Here, when the Ge 20 / Sn 1 superlattice layer is formed as thick as 0.5 μm, the strain due to the difference in lattice constant between the Ge substrate and the buffer layer is relaxed, and the lattice constant of the buffer layer is almost the same as that of the Ge 20 layer and the Sn 1 layer. It becomes a lattice constant, which is about 0.8% larger than that of Ge. Therefore, when the Ge layer is strain-grown by lattice matching with this buffer layer, 0.8% tensile strain is applied.

【0014】ここで、本実施例では、バッファー層とし
て、チャネルのGeよりもバンドギャップの小さなGe/Sn
超格子層を用いたため、バッファー層上に電子閉じ込め
のバリア層として、バンドギャップの大きな膜厚10nmの
x=0.85なるSi1-xGex層3を形成した。その上に、チャネ
ルとなる膜厚10nmのGe層4を形成した。さらに、電子供
給層として、層の膜厚方向中央部に1X1012(1/cm2)のSb
を原子層ドープしたx=0.85なる膜厚20nmの変調ドープSi
1-xGex層5を成長温度400℃で歪み成長の条件下で順次
形成した。さらに、1nmのSi層6を形成した。この様に
して作製したヘテロ構造をMBE装置から取り出し、化
学気相成長法によって膜厚12nmのSi酸化膜7を形成し、
既知の手法を用いて、<1-10>方向をチャネル方向とし
て、ソース,ドレイン領域8,9及びゲート電極11、
ソース,ドレイン電極10,12を形成し、電界効果型
トランジスタを作製した。
Here, in this embodiment, as the buffer layer, Ge / Sn having a band gap smaller than that of the channel Ge is used.
Since a superlattice layer is used, a large bandgap thickness of 10 nm is used as a barrier layer for electron confinement on the buffer layer.
A Si 1-x Ge x layer 3 with x = 0.85 was formed. A 10 nm-thickness Ge layer 4 serving as a channel was formed thereon. Furthermore, as an electron supply layer, 1 × 10 12 (1 / cm 2 )
Atomic layer doped x = 0.85 with 20 nm thickness of modulation-doped Si
Were sequentially formed under the conditions of strain grown at a growth temperature 400 ° C. The 1-x Ge x layer 5. Further, a 1 nm Si layer 6 was formed. The heterostructure thus produced is taken out from the MBE apparatus, and a Si oxide film 7 having a film thickness of 12 nm is formed by chemical vapor deposition.
Using the known method, with the <1-10> direction as the channel direction, the source / drain regions 8 and 9 and the gate electrode 11,
The source and drain electrodes 10 and 12 were formed, and a field effect transistor was produced.

【0015】上記のようにして作製したMODFETに
おいて、移動度は8000cm2/Vsであり、相互コンダクタン
スは実行チャネル長0.5μmの素子で400mS/mmと良好な値
を示した。
In the MODFET manufactured as described above, the mobility was 8000 cm 2 / Vs, and the transconductance of the device having the effective channel length of 0.5 μm was 400 mS / mm, which was a good value.

【0016】さらに、Ge(111)基板上に同様の方法で作
成したMODFETにおいても、移動度は7500cm2/Vs、
相互コンダクタンスは350mS/mmと良好な値を示した。
Further, in the MODFET formed on the Ge (111) substrate by the same method, the mobility is 7500 cm 2 / Vs,
The transconductance showed a good value of 350 mS / mm.

【0017】[0017]

【発明の効果】本発明によれば、n-Si1-xGex/Ge変調ド
ープ構造において、(110)面に平行な方向に引っ張り歪
みを受けたGeの<1-10>方向をチャネル方向とするか、あ
るいは、(111)面に平行な方向に引っ張り歪みを受けたG
eをチャネルとすることによって、移動度をバルクより
も高めることができ、高利得のn型電界効果型トランジ
スタを得ることが可能となる。
According to the present invention, the n-Si 1-x Ge x / Ge modulation doped structure, channel <1-10> direction of Ge that received a tensile strain in a direction parallel to (110) plane Direction, or G that has undergone tensile strain in the direction parallel to the (111) plane
By using e as a channel, the mobility can be increased more than that of the bulk, and a high gain n-type field effect transistor can be obtained.

【図面の簡単な説明】[Brief description of drawings]

【図1】実施例1を説明するための断面図FIG. 1 is a sectional view for explaining a first embodiment.

【図2】歪みGe(110)層の伝導帯の底付近のエネルギー
Figure 2: Energy diagram near the bottom of the conduction band of strained Ge (110) layer

【図3】歪みGe(111)層の伝導帯の底付近のエネルギー
[Fig. 3] Energy diagram near the bottom of the conduction band of the strained Ge (111) layer

【図4】従来の技術を説明するための断面図FIG. 4 is a cross-sectional view for explaining a conventional technique.

【符号の説明】[Explanation of symbols]

1…Ge(110)又はGe(111)基板 2…Ge/Snバッファー
層 3…Si1-xGex層 4…歪みGeチャネル層 5…n-Si1-xGex変調ドープ
層 6…Si層 7…Si酸化膜 8,9…ソース,ドレイン領域 10,12…ソース,ドレイン電極 11…ゲート
電極 13…Ge(001)基板 14…n-Si1-xGex変調ド
ープ層 15,17…ソース,ドレイン電極 16…ゲート
電極
1 ... Ge (110) or Ge (111) substrate 2 ... Ge / Sn buffer layer 3 ... Si 1-x Ge x layer 4 ... strained Ge channel layer 5 ... n-Si 1-x Ge x modulation doped layer 6 ... Si Layer 7 ... Si oxide film 8, 9 ... Source / drain region 10, 12 ... Source / drain electrode 11 ... Gate electrode 13 ... Ge (001) substrate 14 ... n-Si 1-x Ge x modulation doped layer 15, 17 ... Source / drain electrode 16 ... Gate electrode

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】変調ドープn-Si1-xGex/Ge界面のGe側をチ
ャネルとする電界効果型トランジスタにおいて、(110)
面に平行な方向に引っ張り歪みを受けた上記Geの<1-10>
方向をチャネル方向とするか、もしくは、(111)面に平
行な方向に引っ張り歪みを受けた上記Geをチャネルとす
ることを特徴とする電界効果型トランジスタ。
1. A field-effect transistor having a channel on the Ge side of a modulation-doped n-Si 1-x Ge x / Ge interface, wherein (110)
<1-10> of the above Ge that has undergone tensile strain in the direction parallel to the plane
A field effect transistor, wherein the direction is a channel direction, or the Ge strained in the direction parallel to the (111) plane is used as a channel.
【請求項2】請求項1記載の電界効果型トランジスタに
おいて、GeとSnからなるバッファー層上に上記チャネル
を形成したことを特徴とする電界効果型トランジスタ。
2. The field effect transistor according to claim 1, wherein the channel is formed on a buffer layer made of Ge and Sn.
【請求項3】変調ドープn-Si1-xGex/Ge界面のGe側をチ
ャネルとする電界効果型トランジスタの製造方法におい
て、 上記チャネルのGeよりも大きな格子定数を有する単結晶
層を形成する第1の工程と、 上記第1の工程以降に、上記単結晶層に格子整合させて
上記Geを歪み成長させる第2の工程と、 上記第2の工程以降に上記歪み成長させた上記Geを上記
チャネルとし、ソース及びドレインを形成し、かつ上記
チャネルの上にゲート電極を形成することを特徴とする
電界効果型トランジスタの製造方法。
3. A method for manufacturing a field effect transistor having a channel on the Ge side of a modulation-doped n-Si 1-x Ge x / Ge interface, wherein a single crystal layer having a lattice constant larger than Ge of the channel is formed. A second step of strain-growing the Ge by lattice matching with the single crystal layer after the first step, and the strain-grown Ge after the second step. Is used as the channel, a source and a drain are formed, and a gate electrode is formed on the channel.
【請求項4】p-Ge(110)基板の主表面上に、Snの分子線
を照射してSn原子層を形成しその上にGe原子層を形成す
ることを少なくとも2回以上繰り返し、GeとSnからなる
超格子層を形成する第1の工程と、 上記第1の工程以降に上記チャネルとなるGe原子層を上
記超格子層より上に形成する第2の工程と、 上記第2の工程以降に上記チャネルの方向が上記チャネ
ルとなる上記Ge原子層の(1-10)方向となるようにソー
ス及びドレイン領域を形成し、かつ上記チャネルとなる
上記Ge原子層の上にゲート電極を形成する第3の工程と
を具備することを特徴とする電界効果型トランジスタの
製造方法。
4. The main surface of a p-Ge (110) substrate is irradiated with a Sn molecular beam to form a Sn atomic layer, and the Ge atomic layer is formed thereon at least twice. A first step of forming a superlattice layer of Sn and Sn, a second step of forming a Ge atomic layer to be the channel above the superlattice layer after the first step, and the second step of After the process, the source and drain regions are formed so that the direction of the channel becomes the (1-10) direction of the Ge atomic layer that becomes the channel, and a gate electrode is formed on the Ge atomic layer that becomes the channel. And a third step of forming the field effect transistor.
【請求項5】請求項4に記載の電界効果型トランジスタ
の製造方法において、 上記第2の工程以降上記第3の工程以前に上記超格子層
上と上記チャネルとなる上記Ge原子層に挾まれるように
上記超格子層よりもバンドギャップの大きなSiとGeから
なるSiGe層を形成することを特徴とする電界効果型トラ
ンジスタの製造方法。
5. The method of manufacturing a field effect transistor according to claim 4, wherein the Ge atomic layer serving as the channel and the superlattice layer is sandwiched between the second step and the third step. As described above, a method for manufacturing a field effect transistor, comprising forming a SiGe layer made of Si and Ge having a band gap larger than that of the superlattice layer.
【請求項6】請求項4又は請求項5の何れかに記載の電
界効果型トランジスタの製造方法において、 SiとGeからなり、かつ膜厚方向中央部にSbを原子層ドー
プした電子供給層を上記チャネルとなる上記Ge原子層上
に接してかつ上記ゲート電極より下に形成することを特
徴とする電界効果型トランジスタの製造方法。
6. The method of manufacturing a field effect transistor according to claim 4, further comprising an electron supply layer which is made of Si and Ge and which is atomically doped with Sb at a central portion in a film thickness direction. A method for manufacturing a field effect transistor, which is formed in contact with the Ge atomic layer to be the channel and below the gate electrode.
JP28836691A 1991-11-05 1991-11-05 Field effect transistor and production thereof Pending JPH05129635A (en)

Priority Applications (1)

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JP28836691A JPH05129635A (en) 1991-11-05 1991-11-05 Field effect transistor and production thereof

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Application Number Priority Date Filing Date Title
JP28836691A JPH05129635A (en) 1991-11-05 1991-11-05 Field effect transistor and production thereof

Publications (1)

Publication Number Publication Date
JPH05129635A true JPH05129635A (en) 1993-05-25

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5977560A (en) * 1994-10-24 1999-11-02 Micron Technology, Inc. Thin film transistor constructions with polycrystalline silicon-germanium alloy doped with carbon in the channel region
US6258664B1 (en) 1999-02-16 2001-07-10 Micron Technology, Inc. Methods of forming silicon-comprising materials having roughened outer surfaces, and methods of forming capacitor constructions
US6498359B2 (en) * 2000-05-22 2002-12-24 Max-Planck-Gesellschaft Zur Foerderung Der Wissenschaften E.V. Field-effect transistor based on embedded cluster structures and process for its production
JP2008288395A (en) * 2007-05-17 2008-11-27 Univ Nagoya Method of manufacturing tensile-strained germanium thin film, tensile-strained germanium thin film, and multilayer film structure
JP2009272504A (en) * 2008-05-09 2009-11-19 Univ Nagoya Multilayer film structure and forming method thereof
US11362182B2 (en) 2020-04-29 2022-06-14 Samsung Electronics Co., Ltd. Semiconductor device including superlattice pattern

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5977560A (en) * 1994-10-24 1999-11-02 Micron Technology, Inc. Thin film transistor constructions with polycrystalline silicon-germanium alloy doped with carbon in the channel region
US5985703A (en) * 1994-10-24 1999-11-16 Banerjee; Sanjay Method of making thin film transistors
US6320202B1 (en) 1994-10-24 2001-11-20 Micron Technology, Inc. Bottom-gated thin film transistors comprising germanium in a channel region
US6258664B1 (en) 1999-02-16 2001-07-10 Micron Technology, Inc. Methods of forming silicon-comprising materials having roughened outer surfaces, and methods of forming capacitor constructions
US6498359B2 (en) * 2000-05-22 2002-12-24 Max-Planck-Gesellschaft Zur Foerderung Der Wissenschaften E.V. Field-effect transistor based on embedded cluster structures and process for its production
US6872625B2 (en) 2000-05-22 2005-03-29 Max-Planck-Gesellschaft Zur Foerderung Der Wissenschaften E.V. Field-effect transistor based on embedded cluster structures and process for its production
JP2008288395A (en) * 2007-05-17 2008-11-27 Univ Nagoya Method of manufacturing tensile-strained germanium thin film, tensile-strained germanium thin film, and multilayer film structure
JP2009272504A (en) * 2008-05-09 2009-11-19 Univ Nagoya Multilayer film structure and forming method thereof
US11362182B2 (en) 2020-04-29 2022-06-14 Samsung Electronics Co., Ltd. Semiconductor device including superlattice pattern
US11777001B2 (en) 2020-04-29 2023-10-03 Samsung Electronics Co., Ltd. Semiconductor device including superlattice pattern

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