JPH05121783A - Light emitting element drive circuit - Google Patents

Abstract

PURPOSE:To enable a light emitting element to output an optical waveform lessened in rise jitter by compensating oscillation delay at the rise time of an optical waveform and improved in fall time by forcibly discharging the stored carrier at the time when the light emitting element transfers from an ON-state to an OFF-state. CONSTITUTION:A light emitting element drive circuit 1 is provided with a retiming circuit 10 which reproduces input NRZ data signal 20 that takes up a binary logic synchronizing with a clock signal 21 and a pulse conversion circuit 11 which converts a reproduction data signal 22 outputted from the retiming circuit 10 into a current pulse signal used for driving a light emitting element 2. A differentiation circuit 12 which shapes reproduction data signals 22 outputted from the retiming circuit 10 in waveform differentiating them at rise and at fall and a direct current bias circuit 13 which enables a differentiation control current pulse 24 where a direct current bias is given to the differentiation shaping waveform signal 23 outputted from the differentiation circuit 12 to overlap the current pulse signal of the pulse conversion circuit 11 are provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a light emitting element drive circuit in an optical transmitter applied to a high speed optical communication system.

[0002]

2. Description of the Related Art Referring to FIGS. 3 and 4, a conventional light emitting element drive circuit 3 includes a retiming circuit 30 for reproducing (retiming) an input NRZ data signal 40 in synchronization with a clock signal 41, and a retiming circuit 30. The pulse conversion circuit 31 for converting the reproduction data signal 42 reproduced by the circuit 30 into a current pulse and supplying the current pulse to the light emitting element 2, and the light emitting element 2
DC bias circuit 32 for supplying DC bias current a to
It consists of and.

More specifically, the NRZ data signal 40 input to the light emitting element drive circuit 3 is retimed by the retiming circuit 30 in synchronization with the clock signal 41.
Moreover, the waveform is shaped to the TTL level. Here, the retiming circuit 30 is composed of a D-type flip-flop (DF / F). Further, the reproduction data signal 42 of the retiming circuit 30 is supplied to the pulse conversion circuit 31, and the TT
The L-level voltage pulse is converted into a current pulse having a magnitude sufficient to drive the light emitting element 2. Further, the light emitting element drive current pulse 43 in which the DC bias current a supplied from the DC bias circuit 32 is superimposed on the current pulse at the output of the pulse conversion circuit 31 is supplied to the light emitting element 2. Here, the input NRZ data signal 40 is 4 of “1010”.
Bits are illustrated. The light-emitting element 2 emits light from the "1" bit of the reproduction data signal 42, that is, from the rising edge to the falling edge of the voltage pulse and from the falling edge to the rising edge of the current pulse, and outputs "0" of the reproduction data signal 42. The light is extinguished between the falling edge and the rising edge of the bit, that is, the voltage pulse and between the rising edge and the falling edge of the current pulse.

[0004]

In the light emitting element drive circuit 3 described above, when the waveform response characteristics of the pulse conversion circuit 31 and the pulse modulation characteristics of the light emitting element 2 are not sufficiently high speed, the light output waveform of the light emitting element 2 falls. However, even after the current pulse for driving the light-emitting element 2 has reached the “0” level, the transient response thereof causes the influence of the trailing edge of the previous pulse to remain until the leading edge of the next time slot, deteriorating the optical output characteristics. There is a problem of spontaneous emission.

In order to improve the light output characteristics of such a light emitting element, a configuration in which a parallel circuit of a capacitor and a resistor is connected in series with the light emitting element is adopted, which compensates for the oscillation delay of the light emitting element and causes the pulse rise portion. The jitter can be reduced, but the falling characteristics can hardly be improved.

[0006]

A light emitting element drive circuit according to the present invention comprises: a first means for reproducing a data signal having a binary logic in synchronization with a clock signal; and a data signal for driving the light emitting element. Second means for converting the current signal into a current pulse signal, third means for differentiating the data signal at a rising edge and a falling edge, and a current signal obtained by applying a DC bias to the output signal of the third means. And a fourth means for superimposing on the pulse signal.

[0007]

The present invention will be described below with reference to the drawings. Referring to FIG. 1 and FIG. 2 showing an embodiment of the present invention, the light emitting element driving circuit 1 includes an input NRZ data signal 20.
Playback in synchronization with the clock signal 21 (retiming)
A retiming circuit 10, a pulse conversion circuit 11 for converting the reproduction data signal 22 reproduced by the retiming circuit 10 into a current pulse and supplying the current pulse to the light emitting element 2, and a reproduction data signal 22 output from the retiming circuit 10. A differentiating circuit 12 for differentiating and shaping the waveform, and a DC bias circuit 1 for supplying to the light emitting element 2 a differential control current pulse 24 which is bias-controlled by the differential shaping waveform signal 23 output from the differentiating circuit 12.
3 and 3. More specifically, the NRZ data signal 20 input to the light emitting element drive circuit 1 is retimed by the retiming circuit 10 in synchronism with a clock signal 21, and waveform-shaped to a TTL level to obtain a reproduction data signal 22. Here, the retiming circuit 10 is D
Type flip-flop (DF / F). Reproduced data signal 22 output from retiming circuit 10
Is supplied to the pulse conversion circuit 11, and the voltage pulse of the TTL level is converted into a current pulse of a magnitude sufficient to drive the light emitting element 2. The reproduced data signal 22 output from the retiming circuit 10 is input to the differentiating circuit 12.
After differentiating the retiming reproduction data signal 22, the differentiating circuit 12 waveform-shapes a rectangular pulse having a pulse width b and a pulse height d by using the differential pulse as a trigger to obtain a voltage pulse of the differential-shaped waveform signal 23. Differential shaped waveform signal 23
Is supplied to the bias control input of the DC bias circuit 13, and the DC bias current a of the output of the DC bias circuit 13 is
To obtain a differential control current pulse 24. Here, the waveform of the differential control current pulse 24 shows the output of the DC bias circuit 13 when the output of the DC bias circuit 13 and the output of the pulse conversion circuit 11 are not connected. By connecting the output of the DC bias circuit 13 and the output of the pulse conversion circuit 12, the light emitting element drive current pulse 25 in which the differential control current pulse 24 is superimposed on the current pulse of the pulse-converted reproduction data signal 22 is generated. Is supplied to.

Here, the input NRZ data signal 20 is illustrated for 4 bits of "1010". The light emitting element 2 emits light at the bit "1" of the reproduced data signal 22, that is, from the rising edge to the falling edge of the voltage pulse and from the falling edge to the rising edge of the current pulse, and the reproduced data signal 22
The bit is "0", that is, the light is extinguished between the falling edge and the rising edge of the voltage pulse and between the rising edge and the falling edge of the current pulse.

As mentioned above, the input NRZ data signal 2
The light-emitting element 2 is driven by superimposing a differential control current pulse 24, which is bias-controlled by a rectangular pulse whose waveform is reshaped by retiming the input NRZ data signal 20, on the current pulse obtained by retiming 0 and pulse conversion. By intentionally having an overshoot e and an undershoot f at the rising and falling edges of the current pulse for overshooting, the overshoot e compensates for the oscillation delay at the rising edge of the light output waveform of the light emitting element 2 and has less rising jitter. Since it is possible to obtain an optical output waveform and the undershoot f gives a reverse bias to the DC bias current, the light emitting element 2
It is possible to forcibly release the accumulated carriers when shifting from the ON state to the OFF state and improve the fall time of the optical output waveform.

Although the NRZ code has been described as the input data signal 20 in the above description, other signals having bits of "1" and "0" can be similarly implemented. In addition, an example in which a rectangular wave pulse is added as the overshoot e and the undershoot f added to the DC bias current has been described, but as long as a sufficiently good result can be obtained for the rising and falling characteristics of the optical output waveform. Similarly, a pulse having a shape other than the rectangular wave can be implemented. Further, the NRZ input to the light emitting element drive circuit 1
When the light emitting element drive circuit 1 is applied to the optical transmission side, the data signal 20 and the clock signal 21 are generated and processed by the clock signal generated and processed in the optical transmission device and the NRZ generated and processed in synchronization with the clock signal. Data signal is supplied,
When the light emitting element drive circuit 1 is applied to the optical receiving side, the NRZ data signal received from the optical transmission line by the optical receiving device and the clock signal reproduced from the received NRZ data signal are supplied.

[0011]

As described above, according to the present invention, the oscillation delay of the light emitting element is added by adding the overshoot and the undershoot according to the differential waveform of the reproduced data signal to the current pulse for driving the light emitting element. Also, a good optical output waveform with little rising jitter and a short falling time can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing a light emitting element drive circuit of an embodiment of the present invention.

FIG. 2 is a waveform chart of each part of the light emitting element drive circuit of the embodiment.

FIG. 3 is a block diagram showing a conventional light emitting element drive circuit.

FIG. 4 is a waveform chart of each part of a conventional light emitting element drive circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Light emitting element drive circuit 2 Light emitting element 10 Retiming circuit 11 Pulse conversion circuit 12 Differentiation circuit 13 DC bias circuit

Claims (1)

[Claims] 1. A first means for reproducing a data signal having a binary logic in synchronization with a clock signal, and a second means for converting the data signal into a current pulse signal for driving a light emitting element, Third means for differentiating the data signal at a rising edge and a falling edge, and a fourth means for superimposing a current signal obtained by applying a DC bias to the output signal of the third means on the current pulse signal. A light emitting element drive circuit characterized by the above.