JPH05101132A - Verification device for logic circuit operation - Google Patents

Abstract

PURPOSE:To secure the smooth and efficient verification of an object logic circuit. CONSTITUTION:The contents of circuit operation specification describing means 41 which describes how an output should operate for an input are sent to an output signal generation factor inspecting means 43. Connection data on the object logic circuit in circuit storage means 32 and data on basic circuit element operation in circuit element operation storage means 33 are sent to a circuit element input condition analyzing means 42a in an output signal generation factor analyzing means 42. The means 42a analyzes how an input signal to a circuit element should operate when the output conditions of the circuit element are given. The means 42 which has this means 42a analyzes the generation factor of the output signal of the object logic circuit to be verified and sends the analytic result to the means 43. The means 43 compares the operation of the output signal generation factor obtained from the means 42 with operation specifications in the means 41 to detect an error in the operation of the object logic circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plurality of inputs, such as when including a handshake in which a predetermined signal is exchanged by establishing a connection between two transmission devices. The order of operations between signals, between multiple output signals, and between multiple input and output signals is not uniquely determined, and circuit verification can be performed smoothly and efficiently when verifying operations with inconsistent timing. The present invention relates to a logic circuit operation verification device that guarantees to perform the above.

[0002]

2. Description of the Related Art FIG. 2 is a block diagram showing a configuration example of a conventional logic circuit operation verification device. This logic circuit operation verification device includes a circuit storage means 1 for storing a connection state of a logic circuit composed of a plurality of circuit elements, a circuit element operation storage means 2 for storing a basic operation of the circuit element, and the circuit storage. An external input storage means 3 for storing an input pattern and an input time to be externally input to the logic circuit stored in the means 1 are provided, and the operation verification device main body 1 is provided on the output side thereof.
0 is connected. The operation verification device main body 10 is composed of a circuit calculation means 11 and a circuit calculation result storage means 12.

The circuit calculation means 11 inputs the storage information of the respective storage means 1 to 3 and calculates how each circuit element in the target logic circuit which is the target of the logic verification changes due to the change of the external input signal. Then, the calculation result is held in the circuit calculation result storage means 12. And in the visual inspection 20,
The contents of the circuit operation result storage means 12 are compared with the handshake protocol specification 21 to confirm whether the output signal for the input of the target logic circuit is correctly generated.

Before specifically explaining the conventional logic circuit operation verification device, a handshake will be described with reference to FIG. FIG. 3 is a timing chart showing an example of the handshake. In this figure, an example is shown in which a bus master performs a read operation on a bus slave via the bus.

BUSY *, AS *, ADRS, DS * are signals output by the bus master and received by the bus slave, and DATA, ACK * are signals output by the bus slave and received by the bus master. * Indicates a negative logic signal. BUSY * indicates that the bus is in use, AS * indicates that the address is output to the bus, DS * indicates that data may be output to the bus, and ADRS indicates the address of the bus. , DATA represent bus data. Further, ACK * indicates that the bus slave of the bus may terminate the bus access to the bus master because the read data has already been output to the bus.

In the bus protocol shown in FIG. 3, the following operations (1) to (8) are sequentially performed. (1) The bus master asserts the signal BUSY * (a
(assert) to indicate that the bus is being used. (2) The bus master asserts the signal AS * after outputting the address ADRS to indicate that the address ADRS is present on the bus. (3) It indicates that the bus master may output the data by asserting the signal DS *. (4) After performing the operations of (1) and (2), the slave decodes the address ADRS to confirm that the self slave is being accessed, and further the signal BUSY *.
After confirming that AS and AS * are both at the L level, the data DATA is prepared. (5) After confirming that the above (3) has been performed, the slave outputs data DATA and asserts the signal ACK *. (6) After confirming the operation of (5), the bus master negates the signals AS * and DS * and stops the output of the address ADRS. (7) After confirming the operation of (6), the bus slave negates the signal ACK * and stops the output of data DATA. (8) After confirming the operation of (7), the bus slave negates the signal BUSY * and ends the use of the bus.

In the conventional logic circuit operation verification device shown in FIG. 2, when the bus slave outputting the signals DATA and ACK * shown in FIG. 3 is to be simulated, the signal BUSY *, which is output from the bus master, is output. AS *,
The DS * is given to the external input storage means 3. Then, the circuit operation means 11 uses the circuit information in the circuit storage means 1 and the basic operation information of each circuit element in the circuit element operation storage means 2 to determine how the data DATA and the signal ACK * operate with respect to the input. After calculating whether or not to perform the calculation, the calculation result is held in the circuit calculation result storage means 12, and it is manually determined whether or not the result is correct. Therefore, various external input patterns were created and simulated so that the signals given as external inputs could cover all timings.

[0008]

However, in the apparatus having the above configuration, in order to check the external input in all cases permitted by the handshake protocol, a sufficient external input pattern must be created, and the external input pattern can be visually inspected. In order to confirm the simulation result,
There were the following problems, and it was difficult to solve them.

(I) Creating sufficient external input patterns to test external inputs in all cases reduces the efficiency of circuit verification. (Ii) Since it is necessary to visually confirm the simulation result, the efficiency of the circuit verification is lowered and a confirmation error due to an artificial factor occurs.

SUMMARY OF THE INVENTION The present invention provides a logic circuit operation verification device which solves the problems of the prior art described above, such as a decrease in the efficiency of circuit verification and the occurrence of a verification error due to an artificial factor.

[0011]

In order to solve the above problems, the present invention solves the above problems by a circuit storing means for storing a connection state of a target logic circuit which is a target of logic verification, and a circuit which constitutes the target logic circuit. A logic circuit operation verification device for verifying the operation of the target logic circuit by referring to the contents of the circuit storage means and the circuit element operation storage means. Equipped with such means.

That is, according to the present invention, circuit operation specification description means for describing operation specifications between an input signal series and an output signal series in the target logic circuit, an output signal generation factor analysis means, and the output signal generation factor. An output signal generation factor inspection means for inspecting the operation of the output signal generation factor obtained from the analysis means by comparing it with the operation specification in the circuit operation specification description means. The output signal generation factor analysis means refers to the contents of the circuit storage means and the circuit element operation storage means to determine each input condition of all circuit elements in the target logic circuit relating to the transition operation of the output signal of the target logic circuit. It has a function of analyzing the generation factor of the output signal by sequentially analyzing toward the input side.

[0013]

According to the present invention, since the logic circuit operation verification device is constructed as described above, the circuit operation specification description means describes how the output should operate with respect to the input. Therefore, the description content is sent to the output signal generation factor inspection means. Further, the connection state data of the target logic circuit in the circuit storage means and the data indicating the basic operation of the circuit element in the circuit element operation storage means are sent to the circuit element input condition analysis means in the output signal generation factor analysis means. Given.

The circuit element input condition analysis means analyzes what kind of operation the input signal of the circuit element should perform when the output condition of the circuit element is given.
Then, the output signal generation factor analysis unit including the circuit element input condition analysis unit analyzes the generation factor of the output signal in the target logic circuit and sends the analysis result to the output signal generation factor inspection unit. The output signal generation factor inspection means compares the operation of the output signal generation factor obtained from the output signal generation factor analysis means with the operation specification in the circuit operation specification description means to determine whether or not there is an error in the target logic circuit. To detect.

Thus, the target logic circuit is designed to meet the operation specifications including the handshake protocol, for example, without making a plurality of test patterns describing the input signal as in the conventional case. Furthermore, it can be accurately verified without requiring human intervention. Therefore, the above problem can be solved.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing the configuration of a logic circuit operation verification device showing an embodiment of the present invention.

This logic circuit operation verification device includes a handshake protocol specification storage means 31 and a circuit storage means 3 for storing the connection state of a target logic circuit which is the target of logic verification.
2 and a circuit element operation storage means 33 for storing the basic operation of the circuit element forming the target logic circuit. These storage means 31, 32, 33 are composed of semiconductor memories or the like, and the operation verification device body 4 is provided on the output side thereof.
0 is connected. The operation verification device main body 40 has a function of verifying the operation of the target logic circuit by referring to the contents of the storage means 31 to 33, and the circuit operation specification description means 41
An output signal generation factor analysis unit 42 having a circuit element input condition analysis unit 42a and an output signal generation factor inspection unit 43 are provided.

Each of the means 41, 42, 43 is composed of an individual circuit such as an integrated circuit, or a program control of a computer. Of these, the circuit operation specification description means 41 is the one that inputs the content of the handshake protocol specification storage means 31 and describes the operation specification between the input signal series and the output signal series in the target logic circuit. It has a function of outputting to the output signal generation factor inspection means 43.

The circuit element input condition analyzing means 42a in the output signal generating factor analyzing means 42 obtains the operation of the circuit element in the logic circuit by the circuit element operation storing means 33, and thereby the target in the circuit operation specification describing means 41. With respect to the transition operation of the output signal of the logic circuit, the input condition of how the input of the circuit element should operate in order to cause the transition of the output signal is analyzed, and when there are a plurality of candidates, those are analyzed. It has the function of holding.

Then, in the output signal generation factor analysis means 42, information (input condition) indicating how the input signal of the circuit element for generating the output signal of the target logic circuit should operate,
Information obtained from the circuit element input condition analysis means 42a, further applying the input condition as an output signal to the circuit element which generates the input signal, and how the input signal of the circuit element should operate (input Condition) is obtained from the circuit element input condition analysis means 42a. A series of processing like this
It is repeated until the input signal of the circuit element becomes the input signal of the target logic circuit, and when there are a plurality of input candidates in the circuit element input condition analysis means 42a, the above processing is performed for all cases and the processing result is output. It has a function of outputting to the signal generation factor inspection means 43.

The output signal generation factor inspection means 43 has a function of comparing the operation of the output signal generation factor obtained from the output signal generation factor analysis means 42 with the operation specification in the circuit operation specification description means 41. There is.

Next, the operation will be described with reference to FIGS. FIG. 4 is a diagram showing an example of the handshake protocol stored in the handshake protocol specification storage means 31 of FIG. This description example is for the handshake of FIG.

In FIG. 4, the state change is indicated by the combination of the signal name and the logical value surrounded by (), and the state change occurs in the order of appearance of (). For example, (1) indicates that the signal BUSY * becomes 0 (L level).

After "if", the input from the bus master to the bus slave is shown, and after "then", the output from the bus slave to the bus master is shown. For example, (1) and (2) are bus master outputs, and (5) are bus slave outputs.

BEFORE and AFTER indicate the order of state change of signals before and after that. For example, in (2), ((ADRS → VALID) BEFORE (AS * → 0)) means that ADRS is VAL before signal AS * becomes L level.
Indicates that it will be an ID. In (7), ((DATA → INVALD) AFTER (ACK * →
1)) is data DAT after the signal ACK * becomes L level.
It indicates that A becomes invalid (INVALID).

AND indicates a logical product. For example, in (9), ((DATA → 3-STATE) AND (ACK
* → 3-STATE))) indicates that the data DATA is in the 3-state state and the signal ACK * is also in the 3-state state. However, the order of time does not matter.

(3) (wait 3CLK) indicates that the operation following this is performed after the time of inputting at least three clocks CLK has elapsed. FIG. 5 is a circuit diagram showing an example of a slave circuit for realizing the protocol example of FIG. FIG. 6 is a circuit diagram showing an example of a slave circuit that is erroneously created when the protocol example of FIG. 3 is realized. Further, FIG. 7 is a flowchart of the handshake corresponding to FIG. 3 in the incorrect slave circuit of FIG.

The slave circuit shown in FIG. 5 comprises a slave access recognition section 50 composed of a decode 51 and a 3-input NOR gate 52, and a memory control section 61 and a dynamic random access memory (DRAM) on the output side thereof. Is connected to the memory 62. A 3-state driver 63 is connected to the output side of the memory control unit 61.

An ACK * generation unit 70 is connected to the output side of the slave access recognition unit 50, and a 3-state driver 81 controlled by the output of the slave access recognition unit 50 is connected to the output side thereof. ing. ACK
* The generating unit 70 includes delay-type (D-type) flip-flops (hereinafter referred to as FFs) 71 to 74 that are cascade-connected in four stages.
It is composed of an inverter 75 and a 2-input OR gate 76.

On the other hand, the ACK * generator 70A shown in FIG.
Then, the final stage FF 74 is missing. Note that, in both FIGS. 5 and 6, since the data is held in the memory 62 composed of DRAM, a certain time is required for reading. This time is assumed to be the input time of 3 clocks CLK.

The operation of FIG. 5 is as follows. Signal BU
When SY *, ADRS, AS * is input, the slave access recognition unit 50 decodes the address ADRS and recognizes that it is an access to the circuit,
Atto signal HIT. Further, the slave access recognition unit 50 outputs the signal DRIVE * and outputs the signal ACK.
The output 3-state driver 81 that outputs * is enabled.

In the ACK * generator 70, when the signal AS * is asserted, the reset inputs R of the four FFs 71 to 74 are negated, and when the signal HIT is asserted thereafter, the data input D of the FF 71 is asserted. , In sequence,
The information in which the signal HIT is asserted is shifted to the FF 74 by the input clock CLK. At this time, if the input signal DS * is asserted, the signal ACK * is asserted.

On the other hand, in FIG. 6, FFs 71 to 73 are provided.
There are only three. Therefore, as shown in FIG.
K * is asserted one clock earlier than correct operation. This violates the handshake protocol shown in FIG.

The error detecting operation will be described below with reference to the apparatus shown in FIG. In the following description of the operation, the circuit connection state of FIG. 6 is stored in the circuit storage means 32, and each signal of FIG. 3 is described in the circuit operation specification description means 41. Then, when the output signal generation factor analysis unit 42 analyzes, the output signal generation factor analysis unit 42 inspects the conditions for asserting the signal ACK *, and the analysis process and the inspection process are as follows. a) ~
(J) shows that an error in the above operation can be detected.

(A) When the output signal generation factor analysis means 42 of FIG. 1 reads the circuit which outputs the signal ACK * from the circuit storage means 32, the circuit is the 3-state driver 81 of FIG. The output signal generation factor analysis unit 42 recognizes from the data in the operation storage unit 33 that the output enable of the 3-state driver 81 and the data input must be inspected. After that, the inspection of the output enable is omitted.

(B) When the circuit element serving as the data input of the 3-state driver 81 is read from the circuit storage means 32, it is found that it is the output of the 2-input OR gate 76. Therefore, regarding the two inputs of the OR gate 76, inspect. Note that the signal ACK * is asserted because both of these two inputs must be at L level.
The circuit element input condition analysis means 42a discriminates from the data on the 2-input OR gate in the circuit element operation storage means 33.

(C) One of the inputs of the 2-input OR gate 76 is directly connected to the input represented by the signal DS *. Signal AC of circuit operation specification description means 41 shown in FIG.
The description regarding the assertion of K * is (5), and the description regarding the signal DS * is included in (4). And, the limitation by the signal DS * regarding the assertion of the signal ACK * is
Since the signal ACK * must be asserted after the signal DS * is asserted, the output signal generation factor inspection means 43 determines that the operation of this circuit conforms to the specifications.

(D) One of the remaining inputs of the 2-input OR gate 76 is that the output of the FF 73 becomes L level. (E) Further, the condition that the output QN of the FF 73 becomes L level is that the clock input C is changed from L level when the reset input R of the FF 73 is H level and the data input D, that is, the output QA of the FF 72 is H level. The circuit element input condition analyzing means 42a indicates that the transition to the H level is made.
Is identified from the data regarding the D-type FF in the circuit element operation storage means 33. The inspection process regarding the reset input R is omitted. (F) As in the above case, the output QA of the FF 72 is H
The condition for the level to become is that the reset input R of the FF 72 is H.
At level and data input D, that is, output QA of FF71
Is at the H level, the clock input C changes from the L level to the H level.
It is to transit to the level. The inspection process regarding the reset input is omitted. (G) As in the above case, the output QA of the FF 71 is H
The condition for the level to be set is that the reset input R of the FF 71 is H.
At the level and when the data input D, that is, the signal HIT is at the H level, the clock input C transits from the L level to the H level. The inspection process regarding the reset input is omitted.

(H) The condition that the signal HIT becomes H level, that is, the output of the 3-input NOR gate 52 becomes H level is that all the inputs of the 3-input NOR gate 52 become L level. The condition analysis means 42a discriminates from the data on the 3-input NOR gate in the circuit element operation storage means 33.

(I) The signal BUSY *, which is one input of the 3-input NOR gate 52, is the signal A as shown in FIG.
This condition is one of the factors for generating CK *, and this condition is stored in the handshake protocol specification storage means 31. Furthermore, as the specifications of this circuit, the signal BUSY *
And AS * are asserted, and as a result of decoding the address ADRS, it is recognized that the signal ACK * is not asserted after a lapse of at least 3 clocks CLK from the time when it is recognized that this circuit is being accessed. The condition that does not hold is described in the circuit operation specification description means 41. However, as a result of the above, the output signal generation factor inspection means 43 detects that the signal ACK * can be asserted when the time of 2 clocks CLK has elapsed since the signal BUSY * was asserted.

(J) Similar results are obtained for the decode output AS * of the address ADRS, which is another condition of the 3-input NOR gate 52. In the process as described above, it is detected that the circuit shown in FIG. 6 violates the operating specifications.

The present invention is not limited to the above embodiment,
Various modifications are possible. For example, the above-described embodiment is not only applicable to the operation verification of the logic circuit including the handshake, but also applicable to the case where the output signal series with respect to the input signal series is defined by a certain standard. further,
The operation specification is not limited to the description method shown in FIG. 4, and any description content can be applied.

[0043]

As described in detail above, according to the present invention, the circuit operation specification description means, the output signal generation factor analysis means, and the output signal generation factor inspection means are provided.
The operation of the target logic circuit can be verified without creating multiple test input patterns as in the past, and because the operation can be mechanically confirmed, the efficiency of circuit verification is significantly improved and it is possible to visually check it. Confirmation errors due to factors can be eliminated.

[Brief description of drawings]

FIG. 1 is a configuration block diagram of a logic circuit operation verification device showing an embodiment of the present invention.

FIG. 2 is a configuration block diagram of a conventional logic circuit operation verification device.

FIG. 3 is a timing chart showing an example of a handshake.

FIG. 4 is a diagram showing an example of contents of a handshake protocol storage means and a circuit operation specification description means 41 of FIG.

5 shows an example of a circuit for realizing the operation shown in the embodiment of the present invention, and is a slave circuit diagram when the protocol of FIG. 3 is realized.

6 is an example of a circuit that realizes the operation shown in the embodiment of the present invention, and is a slave circuit diagram when the protocol of FIG. 3 is not realized.

FIG. 7 is a timing chart showing a handshake operation in the wrong slave circuit of FIG.

[Explanation of symbols]

31 handshake protocol specification description means 32 circuit storage means 33 circuit element operation storage means 40 operation verification device body 41 circuit operation specification description means 42 output signal generation factor analysis means 42a circuit element input condition analysis means 43 output signal generation factor inspection means

Claims (1)

[Claims] 1. A circuit storage means for storing a connection state of a target logic circuit to be a target of logic verification, and a circuit element operation storage means for storing a basic operation of a circuit element forming the target logic circuit. A logic circuit operation verification device for verifying the operation of the target logic circuit by referring to the contents of the circuit storage means and the circuit element operation storage means, wherein the operation between the input signal series and the output signal series in the target logic circuit With reference to the contents of the circuit operation specification description means describing the specifications and the contents of the circuit storage means and the circuit element operation storage means, each of all circuit elements in the target logic circuit relating to the transition operation of the output signal of the target logic circuit Output signal generation factor analysis means for analyzing generation factors of the output signal by sequentially analyzing input conditions toward the input side, and output signal generation factor analysis means An output signal generation factor inspection means for inspecting the operation of the output signal generation factor compared with the operation specifications in the circuit operation specification description means, and a logic circuit operation verification device.