JPH04273382A - Logic simulation system of lsi - Google Patents

Abstract

PURPOSE:To facilitate the simulation by a logic simulator which does not have a bi-directional input output element as a model for an LSI logic circuit to access to a common bus. CONSTITUTION:In the logic simulation system of an LSI circuit including a bus circuit connected by plural try state elements which do not take a wired logic including a bi-directional input output pin to one signal line, a try state calculating means 1 to calculate for the signal corresponding to the state from the try state element, a pin input output deciding means 2 to decide the signal input output of the bi-directional pin connected to the bus circuit from the signal corresponding to the state, an input output signal selecting means 3 to select the input output signal to the bi-directional pin and the logic circuit, and a bus conflict detecting means 4 to compare the signal corresponding to the try state with the signal corresponding to the try state inputted through a bi-directional pin from an external circuit and detect the occurrence of the bus conflict are equipped.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic simulation method for LSI logic circuits in which a plurality of logic circuits access a common bus via tristate elements.

0002

2. Description of the Related Art With recent advances in manufacturing technology such as VLSI, the scale of circuits that can be realized on one chip has increased dramatically. For this reason, in addition to logic circuits, a single VLSI can include an interface circuit with external memory and a bus circuit, and such VLSIs have bidirectional external input/output pins ( bus pin)
exists.

[0003] When designing a circuit, logic simulation is performed to verify the design, but it is necessary to treat this bidirectional pin as an input under a certain pattern, and as an output under another pattern. . In addition, in order to identify defective products after VLSI manufacturing, a test pattern is generated in advance, and a failure simulation is performed to measure the failure detection ability of the generated pattern. When generating a test pattern, bidirectional pins need to be treated as inputs or outputs, depending on the case, to improve the detection rate.

Until now, logic simulation, fault simulation, and test generation have been realized and processed by software on large computers, but when handling bidirectional pins, it is necessary to write a special routine for the processing. I was dealing with this.

[0005]

[Problems to be Solved by the Invention] As mentioned above, conventional logic simulations of LSI logic circuits that handle bidirectional pins require special routines that treat bidirectional pins as inputs or outputs. I dealt with it by writing it as .

However, as the scale of circuits has increased in recent years, the time required for one simulation has become enormous. To deal with this, specialized machines for logic simulation have been developed, but some gate-level simulators do not have bidirectional gates as models. In this case, since the computer cannot add a special routine for handling bidirectional pins, an additional circuit for handling bidirectional pins is required on the target circuit side.

The present invention provides an LSI logic simulation method that facilitates logic simulation of a logic circuit including bidirectional input/output elements in a logic simulation that does not have bidirectional input/output elements as a model. The purpose is to

[0008]

Means for Solving the Problems The means adopted by the present invention to solve the above-mentioned problems will be explained with reference to FIG. FIG. 1 is a diagram showing the principle of the present invention.

[0009] A logic simulation method for an LSI circuit including a spring circuit connected to a plurality of tri-state elements that cannot perform wired logic including bidirectional input/output pins on one signal line,

tristate calculation means 1 for performing calculations on signals corresponding to states from the tristate element;

pin input/output determination means 2 for determining signal input/output of a bidirectional pin connected to the bus circuit based on a signal corresponding to a state from the tristate element;

[
input/output signal selecting means 3 for selecting input/output signals to the bidirectional pins and the logic circuit according to the result determined by the pin input/output determining means 2;

[0013]
Bus conflict detection for detecting the occurrence of a bus conflict by comparing a signal corresponding to tristate output from the tristate element and a signal corresponding to tristate input from an external circuit via the bidirectional pin. means 4, for correcting the input value when a bus conflict occurs due to a signal input from an external circuit via a bidirectional pin.

[0014]

[Operation] The tristate calculation means 1 performs calculations on signals corresponding to states from tristate elements.

The pin input/output determination means 2 determines the signal input/output of the bidirectional pin connected to the common bus based on the signal corresponding to the state from the tristate element.

The input/output selection means 3 selects and outputs input/output signals to the bidirectional pins and logic circuits based on the determination result by the pin input/output determination means 2.

The bus conflict detection means 4 compares the tristate signal output from the tristate element with the tristate signal inputted from an external circuit via the bidirectional pin to detect the occurrence of a bus conflict.

As described above, in a logic simulator that does not have bidirectional input/output elements as a model, the signal input/output of bidirectional pins is determined based on the tristate signal from the logic circuit, and bus conflicts are detected. Therefore, logic simulation of a logic circuit including bidirectional input/output elements can be easily performed.

[0019]

Embodiment A first embodiment of the present invention will be described with reference to FIGS. 2 to 4. FIG. 2 is a configuration diagram of the first embodiment of the present invention, and FIG.
4 is a diagram showing an example of a specific circuit configuration for modeling, and FIG. 4 is an explanatory diagram of the operation of the first embodiment.

[Configuration of the first embodiment] In FIG. 2, the tristate calculation means 1, pin input/output determination means 2, input/output signal selection means 3, and bus conflict detection means 4 are as explained in FIG. It is.

7 is a target circuit for performing logic simulation, 7o is an output from the target circuit, and 7i is an input to the target circuit.

72a and 72n in the target circuit 7o are tri-state elements (TRST); when the gate input (a) is 1, the output (f) of the TRST 72a is Z; when (a) is 0, the output (f) of the TRST 72a is Z; is the other input (b)
Outputs a signal value of 0 or 1.

9 is a bidirectional pin that connects the target circuit and an external circuit, eo is a signal output to the external circuit via the bidirectional pin, and ei is a signal input from the external circuit via the bidirectional pin. It shows.

Reference numerals 31, 32 and 33 designate select circuits, which select and output one of the signals input to the select circuit according to the control signal output from the pin input/output determining means 2.

ei input to the select circuit S1 of 33
Alternatively, it is the same signal as Z output from the tristate element 72.

[Operation of the first embodiment] Before explaining the operation of the first embodiment, modeling using a specific circuit configuration example will be explained with reference to FIG.

FIG. 3 shows an example of the structure inside the LSI logic circuit, and 7a, 7j and 7n are logic circuits. Output signals (b) and (d) and input signal (h) from each logic circuit 7a and 7n access common bus 8 via drivers 71a and 71n, respectively. Further, the input to each logic circuit 7a, 7j, 7n is directly input from the common bus 8 as shown by an input signal (h).

Control inputs of drivers 71a and 71n (
A) and (c) are transmitted from a bus beater (not shown).

Reference numeral 9 is a bidirectional pin, which is an external connection terminal of the common bus 8.

When the control input signal (a) becomes 0, the driver 71a gates on, that is, becomes low impedance, and sends the output signal (b) to the common bus 8.

When the control input signal (a) becomes 1, the driver 71a gates off, that is, becomes high impedance, and inputs the signal from the common bus 8 as the input signal (h). However, the circuit 7a determines whether or not the input signal (h) is to be read as a processing input to a register (not shown).

(a), (b) (of the circuit 7o shown in FIG. 2)
c) and (d) correspond to the control signals (a) and (c) and output signals (b) and (d) shown in FIG. In addition, the input signal (h) of the circuit 7i is input to the circuits 7a and 7j of FIG.
and 7n input signal (h).

The tri-state element TRST72a changes the high impedance state of the driver 71a shown in FIG.
The corresponding operation is performed.

That is, when (a)=0, (b)=0, (f)=0(a)=0,
When (b)=1, (f)=1, (a)=1, when (b)=0, (f)=Z(a)=1, when (b)=1, (f)=
Assume that a signal Z is output.

The TRST 72n also outputs output signals (g) corresponding to the same three states.

The tri-state calculation means 1 inputs (f
) and (g), when the output is (x),

0037
] When (f)=0, (g)=0, (x)=0(f)=1,
When (g) = 0, (x) = C (f) = 0, when (g) = 1, (x) = C (f) = 1, when (g) = 1, (x) =
When 1(f)=Z, (g)=0, (x)=0(f)=Z
, (g)=1 then (x)=1(f)=0, (g)=Z
When (x) = 0 (f) = 1, when (g) = Z (x)
When =1(f)=Z and (g)=Z, the arithmetic processing of (x)=Z is performed. C is a signal newly indicating a conflict.

In the pin input/output determining means 2, when the inputs are (f) and (g) and the output is (y),

When (f)=Z and (g)=Z, (y)=0 (y)=1 except for the above (f) and (g) are output.

The select circuits S0 31, S1 32, and S2 33 select all signals (ei) input from the bidirectional pin 9 when the control signal value output from the pin input/output determination means 2 is 0. Output. When the control signal value is 1, the select circuit S0 31 selects the output (x) from the tristate calculation means 1 as the select circuit S1 32
The select circuit S2 33 selects the output (x) from the tri-state calculation means 1 and outputs the signal (eiz).

The bus conflict detection means 4 compares the signal (ei) inputted from the bidirectional pin 9 with the signal (x) outputted from the tristate calculation means 1,

00
42] When (x) is C, output (Bcon) = 1 regardless of the value of (ei) (x) = 1, when (ei) = 0, (Bcon) = 1
When (x)=0, (ei)=1, (Bcon)=1
is output, and input signals (x) and (ei) are all set to 0 except for the above. In the above example, the output signal (Bcon) =
1 corresponds to the occurrence of bus conflict.

Next, the operation of the first embodiment will be explained with reference to FIG. Figures 4 (A), (B), (C) and (
D) Both, the first column is the signal (a) (b) shown in Fig. 2...
(h), and the second and subsequent columns show the signal values.

FIG. 4A shows a case where bidirectional pins are considered as inputs.

Since signals (a) and (c) are both 1, the signal (f
), (g) and (x) become Z, and the signal (y) becomes 0. That is, the circuit W7 becomes high impedance,
No signal is sent out from circuit W7.

In this state, that is, (y) is 0
Therefore, select circuit S1 32, select circuit S
2 33 and select circuit S0 31 both select the signal (ei) and output an output signal (h), which is sent to circuit W7i.

FIG. 4(B) shows the case where bidirectional pins are regarded as outputs.

Signals (a), (b), (c) and (d)
is 4 depending on the signal value, as shown in the second to fifth columns.
Sometimes it's a street. The second and fourth columns are the circuit W shown in FIG.
The third and fifth columns correspond to the case where the signal (b) is sent from the circuit Wn 7a to the common bus 8, and the third and fifth columns correspond to the case where the signal (d) is sent from the circuit Wn 7n to the common bus 8.

In the second column, since the signal (c) is 1, (g
) is Z, and since (b) is 0, (x) is 0, and (y)
outputs 1.

On the other hand, since the external circuit connected to the bidirectional pin 9 is in a signal receiving state, (ei) is Z.

Since (y) is 1, the select circuit S0 31 selects the signal (x) and outputs the output signal (h).
outputs 0 and sends it to circuit W7i.

Since (y) is 1, the select circuit S1 32 selects the signal (x) and outputs the output signal (em
) outputs Z.

Since (y) is 1, the select circuit S2 33 selects the signal (x) and outputs the output signal (eo
) outputs 0.

The same operation is performed for the signal inputs to the third to fifth columns, and the signals (h), (em) and (eo
) is output.

FIG. 4(c) shows a case where a bus conflict caused by an input value from a bidirectional pin is corrected.

Signals from the second column to the fifth column (a), (b),
For the signal values of (c) and (d), the signals (f), (
g), (x) and (y) are output, and the select circuit S
Output signals (h), (em) and (eo) from 0 31, S1 32 and S2 33 are output by selecting signals (x), (eiz) and (x), respectively.

At this time, if the signal (ei) input from the bidirectional pin 9 is different from the value of the signal (x), the bus conflict detection means 4 outputs a signal (Bcon) indicating that a conflict has occurred. Output as .

FIG. 4D shows a case where a bus conflict caused by the output value of the driver of each circuit shown in FIG. 3 is detected.

Second and third column signals (a), (b), (
For the signal values of c) and (d), the signals (f) and (g
), (x) and (y) are output, and each select circuit 3
Output signals from 1, 32 and 33 (h), (em)
and (eo) are the signals (x), (eiz
) and (x) are selected and output.

Furthermore, in the bus conflict detection signal 4,
Since the signal (x) is C, a signal (Bcon) indicating that a conflict has occurred is output as 1.

In the above explanation, the pin input/output determining means 2 makes a determination based on the signals (f) and (9) from the circuit W7o, but the output signal (x) of the tristate calculating means 1 is Based on this, when (x) is Z, (y) is 0
, (x) is other than Z, a similar result can be obtained even if (y) is set to 1.

Next, a second embodiment of the present invention will be described with reference to FIGS. 5 and 6. FIG. 5 is a block diagram of the second embodiment, and FIG. 6 is an explanatory diagram of the operation of the second embodiment.

[Configuration of Second Embodiment] In FIG. 5, the tristate calculation means 1, pin input/output determination means 2, input/output signal selection means 3, and bus conflict detection means 4 are as explained in FIG. be.

Reference numeral 34 denotes an input fault generating section, which falsifies the signal from the logic circuit connected to the outside via the bidirectional pin, and generates a pseudo fault.

Reference numeral 35 denotes an output fault generating section, which erroneously sends a signal to a logic circuit connected to the outside via a bidirectional pin to generate a pseudo fault.

[Operation of Second Embodiment] Next, the operation of the second embodiment will be explained with reference to FIG.

The second embodiment is a case in which a failure in a logic circuit is simulated. When simulating a failure in a logic circuit, a pseudo fault is generated in the input fault generating section 34 and the output fault generating section 25. Set the fault insertion signal (flt) to 1.

FIG. 6A shows the case where the bidirectional pin 9 is considered as an input.

When the bidirectional pin 9 is considered as an input, the output signal (x) of the tristate calculation means 1 is Z, and the output signal (y) of the pin input/output determination means 2 is 0, so the selection circuit 31, 32 and 33 select the input signal (ei) from the bidirectional pin 9 and output it.

However, since the fault insertion signal (flt) to the input fault generating section 34 is 1, the signal (Fi) output from the input fault generating section 34 and input to the select circuit S031 is different from the signal (ei). Output a false D or E.

As a result, the incorrect signal D or E is input as the signal (h) input to the circuit W7i.

[0072] As a method of making the signal erroneous in the input fault generating section 34, it is converted into a special signal that can simulate a failure in a logic circuit. That is, for example, assuming that a certain circuit in a logic circuit is damaged, the logic circuit can be simulated by converting and inputting a signal equivalent to that the circuit is damaged. In the embodiment, a case where the normal signal value is 1 and a fault signal value is 0 is indicated by the symbol D, and a case where the normal signal value is 0 and the fault signal value is 1 is indicated by the symbol E.

FIG. 6(B) shows the case where the bidirectional pins are regarded as outputs.

In this case, since the output signal (y) of the pin input/output determining means 2 is 1, the select circuits S0 31 and S2 33 select and output the output signal (x) of the tristate calculation means 1. .

However, since the fault insertion signal (flt) to the output fault generating section 35 is 1, the signal (Fo) output from the output fault generating section 35 and input to the select circuit S233 is different from the signal (x). Output D or E by mistake.

As a result, the signal (eo) output via the bidirectional pin 9 outputs an erroneous signal D. However, the signal (h) input to the circuit W7i is an error-free signal (x), making it possible to simulate the case of a failure in the external circuit.

The method of making the signal erroneous in the output fault generation section 35 is the same as the method used in the input/output fault generation section 34 described above, and the method of causing the signal to be erroneously output when a certain circuit in the logic circuit fails. A conversion is performed into a signal equivalent to the signal.

Note that when performing a logic simulation, there are cases where the simulation is performed without being able to specify each signal value, but even in such a case, the tri-state calculation means, pin input/output determination means, input/output signal selection means The operation of the bus conflict detection means is similar to that described in the embodiment with respect to the signal values input to each means.

Although one embodiment of the present invention has been described above, the present invention is not limited to these embodiments, and various modifications can be made in accordance with the gist of the invention.

[0080]

[Effects of the Invention] As explained above, according to the present invention, the following effects can be obtained.

■In a logic simulator that does not have bidirectional input/output elements as a model, the signal input/output of bidirectional pins is determined based on tristate signals from the logic circuit, and bus conflicts are detected. Therefore, logic simulation of a logic circuit including bidirectional input/output elements can be easily performed.

(2) Since the signal is erroneously generated to generate a pseudo fault, the operation at the time of a fault can be easily simulated.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the principle of the present invention.

FIG. 2 is a configuration diagram of a first embodiment of the present invention.

FIG. 3 is a diagram showing a specific example of a circuit configuration for modeling.

FIG. 4 is an explanatory diagram of the operation of the first embodiment.

FIG. 5 is a configuration diagram of a second embodiment of the present invention.

FIG. 6 is an explanatory diagram of the operation of the second embodiment.

[Explanation of symbols]

1 Tri-state calculation means 2
Pin input/output determination means 3 Input/output signal selection means 4
Bus conflict detection means 7 Logic circuit 8 Common bus 9 Bidirectional pin 31 Select circuit S0 32 Select circuit S1 33 Select circuit S2 34 Input fault generating section 35 Output fault generating section 71 Driver

Claims (2)

[Claims] 1. A logic simulation method for an LSI circuit including a bus circuit in which a plurality of tri-state elements that cannot perform wired logic including bidirectional input/output pins on one signal line are connected, the method comprising: (1) a tri-state calculation means 1 that performs calculations on signals corresponding to the states of the tri-state elements; input/output determination means 2; (i) input/output signal selection means 3 for selecting input/output signals to bidirectional pins and logic circuits according to the determination result of said pin input/output determination means 2; and (iii) output from said tristate element. bus conflict detection means 4 for detecting the occurrence of a bus conflict by comparing a signal corresponding to the tristate inputted from the external circuit with a signal corresponding to the tristate input from an external circuit via the bidirectional pin. An LSI logic simulation method, characterized in that when a bus conflict occurs due to a signal input from an external circuit via a bidirectional pin, the input value is corrected. [Claim 2] The input/output signal selection means 3 includes:
An input fault generating section 34, in which signals are input to the LSI circuit via bidirectional pins, which falsifies input signals and generates pseudo-faults; and ■ an output, in which signals are output from the LSI circuit via bidirectional pins. 2. The LSI logic simulation method according to claim 1, further comprising an output fault generating section (35) that falsifies a signal and generates a pseudo fault.