JPH0462217B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an apparatus for demodulating FM modulated optical communication signals and magnetic electrical signals.

The NRZ method (Non Return zero) has been in practical use for a long time as a digital information recording method, but this method has the disadvantage that the recording frequency fluctuates greatly depending on the pattern of the information being recorded, and that The disadvantages are that a timing signal is required in addition to the original information signal, and that there are strict requirements regarding the temporal phase skew between this information signal and the timing signal.

Therefore, the FM method is a digital information recording method that has improved the above-mentioned drawbacks, and is widely used. The FM method is a type of modulation method called a self-clocking method, and because it sends information by mixing information and timing signals into one type of signal, there are no problems such as skew, and it has many advantages over the NRZ method. . However, when demodulating a signal modulated by the FM method, there is a drawback that accurate demodulation cannot be performed if the 1-bit period of the signal varies greatly. In order to improve these shortcomings, USP3902129,
USP3949313 and USP3962726 have already been proposed. FIG. 2 is an explanatory diagram of conventional FM demodulation, and FIG. 3 is a circuit diagram for the demodulation. As shown in the figure, when the information 0011010001 is modulated by the FM method, the waveform is as shown in FIG. 1A. In the FM method, as shown in the figure, there is always a change in level at the boundary point of a bit frame, and furthermore, when the information is "1", there is a change in level even at the midpoint of one bit frame. Therefore, as shown in FIG. 1A, the recording frequency when the information is "1" is twice that when the information is "0".

The waveform of FIG. 1A is input to the input circuit 11 of FIG. 2 to generate pulse trains as shown in FIG. 3 a, b, and c. As shown in the figure, a, b, and c are three pulse trains whose timings are slightly shifted from each other. This pulse train includes a mix of information pulses and clock pulses. Reference numeral 51 in FIG. 3 is an oscillator that generates a pulse train of a constant period. 56 and 57 are frequency dividers, and the frequency divider 56 outputs a signal with a duty cycle of 50% by, for example, 1/3 of the number of input pulses, and the frequency divider 57 outputs a signal with a duty cycle of 50% by 1/3 of the number of input pulses. Outputs /4 number of pulses. In the current preceding bit frame, if the counter 54, frequency dividers 56 and 57 are cleared by the pulse example b', and the oscillator 51 generates, for example, 120 pulses during the bit frame period, the contents of the counter 54 will be the same as that of the bit frame. At the end of , the value becomes 30 (=120×1/4), and this value 30 is loaded into the up-down counter 53 at the timing signal a' of the next bit frame. The contents of the up-down counter 53 are subtracted one by one by the output of the frequency divider 56 in the relevant bit frame, but since the frequency divider 56 divides the frequency by 1/3, it generates 40 pulses in one bit frame. When the 31st pulse is generated from the frequency divider 56, the counter 53 generates a borrow signal, and this signal is used as a clock output. The borrow timing is 31/40≒3/4. In FIG. 2, the gate control 55 outputs a signal as shown in FIG. 3(f), and the demodulated data output circuit 14 is constituted by a flip-flop. Signal f and input signal a and signal f and input signal b are input to AND gates 18a and 18b, respectively. Next, by inputting these outputs to the flip-flop 14 as a set input s and a reset input R, a data signal g is obtained in which signals a and b are masked with a pulse signal f as shown in FIG. 3g. Furthermore, it is also possible to operate the up-down counter 53 as an up-counter. In that case, the complement of the output of the counter 54 may be loaded into the counter 53, and the carry output may be used as the clock output instead of the borrow output.

In such a conventional demodulation circuit, 1/4, 1/4,
It is necessary to create a timing pulse with a frequency of 1/3. This means that the frequency of the oscillator 51 needs to be at least four times the frequency of the timing pulse used. This poses a large manufacturing burden when converting the above circuit into an IC. In addition, recent magnetic recording technology and optical communication technology have enabled faster speeds.
There is a demand for demodulating FM modulated signals, in other words, shorter signals within one bit frame time. To meet this requirement, a higher frequency oscillator is required. Also, in the above example, using the borrow or carry of counter 53, 31/40≒
However, when the 1-bit interval is short, the ratio of errors becomes large, and there is a problem that correct demodulation may not be possible. Furthermore, with conventional equipment, if demodulation is not performed correctly in a certain bit frame due to bit interval jitter or external noise when demodulating continuous FM modulated signals, demodulation of all subsequent FM modulated signals is delayed. There was also the problem that it was conducted differently.

The present invention has been made by focusing on such conventional problems, and includes a mask circuit, a first counter that starts counting by the clock pulse output from the mask circuit, and a first counter that starts counting by a clock pulse that is the output of the mask circuit. a second counter having a function of releasing the mask; and a second counter having a function of releasing the mask by detecting a data pulse generated while the mask circuit is closed.
The purpose of this invention is to solve the above problems by providing an FM signal demodulator equipped with a flip-flop.

The present invention will be explained below based on the drawings.

FIG. 4 is a diagram for explaining the FM signal demodulation device of the present invention, and FIG. 5 is a block diagram showing one embodiment thereof. In Figure 5
DIN is an FM modulation signal, and this DIN signal is input to the edge pulse generator 61 and EPG. The signal (OSC) from the oscillator 60 is simultaneously input to the edge pulse generator 61, and when the DIN signal rises,
An edge pulse a corresponding to a falling edge is output.
The obtained edge pulse is input to the gate 72,
Thereafter, the signal is input to the delay circuit 82. Delayed signals b and c are generated in this delay circuit 82. The output c is applied as a clear signal to the first counter CNT1 65, and at the same time sets the first flip-flop 69 and starts the mask signal.
The output Q of the first flip-flop 69 is connected to the gate 7
2 is closed, so that the signal from the edge pulse generator 61 is no longer input to the delay circuit 82. This delay circuit 82 outputs a pulse signal c obtained by delaying the edge pulse a, which is the output of the gate 72, by a predetermined minute time to the first counter 65, CNT1, and clears the counter 65. On the other hand, the circuit 63,
64 is one of three output pulses from the oscillator 60.
A pulse deletion circuit is configured to delete pulses d, and the deleted pulses d are inputted to the first counter 65 as counting pulses.

The first counter 65 counts for one bit frame, and its contents are determined by the output b of the delay circuit 82.
Complement circuit 66, second counting circuit 67 via COMP
Loaded into CNT2. The second counter 67 is counted up by a constant period pulse (OSC) from the oscillator 60.

Next, when the detection circuit 68 and DET detect that the contents of the second counter 67 have become all "1",
At the same time, gate 72 is opened and the output of edge pulse generator 61 is input to the delay circuit. The output signal from the detection circuit 68 instantly resets the first flip-flop 69 via the OR circuit 71 and closes its mask. In this way, the presence or absence of data can be confirmed in exactly 2/3 of a 1-bit interval. Furthermore, if data edge pulses are output from the edge pulse generator 61 in quick succession before setting the next mask, the second flip-flop 7
0 is set as soon as possible, and its output Q is the OR circuit 71.
The first flip-flop is reset for the beginning of the mask via. Even if a sudden reduction in the bit interval occurs in this way, if the bit frame contains a data "1" pulse, demodulation will be performed accurately. Even if a demodulation error occurs, according to the present invention, if a frame with accurate data "1" is provided for one bit frame in the middle of the data, the start of the mask can be synchronized with the clock pulse at that point. can be corrected. Subsequent data can then be correctly demodulated.

As described above, according to the present invention, an accurate mask width can be obtained using a relatively simple circuit and without requiring a high frequency. Therefore, it is possible to provide an FM signal demodulation device that not only can stably demodulate the recent high-speed FM modulated signals, but also can instantly recover from demodulation errors.

[Brief explanation of the drawing]

Figure 1 is a waveform diagram of FM modulation, Figure 2 is a waveform diagram of conventional FM signal demodulation, and Figure 3 is a waveform diagram of conventional FM signal demodulation.
Block diagram of FM signal demodulator, No. 4
The figure is a waveform diagram of the FM signal demodulation system according to the present invention, and FIG. 5 is a block diagram showing one embodiment of the present invention. 60... Oscillator, 61... Edge pulse generator, 6
3, 64... Pulse deletion circuit, 65... First counter, 66... Complement circuit, 67... Second counter, 68
...Detection circuit, 69...First flip-flop, 70
...Second flip-flop, 71...OR circuit, 72
…Gate.

Claims (1)

[Claims] 1 In the demodulation method of digital signals modulated by the FM method (also called F2F), a timing pulse generator with a fixed period, a pulse deletion gate circuit that deletes one in three of the continuous timing pulse train, and , an edge pulse generation circuit that generates edge pulses corresponding to the rising and falling edges of an input signal modulated by FM, a delay circuit that delays these edge pulses by a predetermined period of time, and a circuit that synchronizes with a pulse corresponding to a clock pulse among the edge pulses. a first counter that starts counting the output pulse train from the pulse deletion gate circuit and finishes counting at the next clock pulse; a detection gate circuit that receives the contents in parallel and in the form of complements and detects a state in which the contents of a second counter counted by the timing pulse from the timing pulse generator are all "1"; and the edge pulse A first flip-flop circuit that is set by an edge pulse corresponding to the clock pulse of the output of the generator and reset by the output from the detection gate circuit; When there is a pulse corresponding to the data pulse among the edge pulses, the first
It consists of a second flip-flop circuit that generates a signal for resetting the flip-flop, and a gate circuit that outputs only a pulse corresponding to a clock pulse among the outputs of the edge pulse generating circuit based on the output of the first flip-flop circuit and the output of the edge pulse generating circuit. FM signal demodulator.