JPH0461071A - Recording and reproduction circuit for magnetic disk storage device - Google Patents

Abstract

PURPOSE:To execute a recording operation at high speed by executing the recording operation of the information by a parallel processing. CONSTITUTION:Plural magnetic disk storage medium surfaces 9,10 and plural write-in/read-out heads 7,8 are provided, and a write-in serial information is successively set to plural flip-flops 1,2. And, a bit value set at least one of the plural flip-flop 1,2 is monitored and the set timing of the bit value ''1'' is detected, the write-in serial information is distributed time sequentially for every bit and set after the detection of the bit value ''1'', and the plural write-in data signals transmitted from the plural flip-flops 1,2 are simultaneously modulated and simultaneously supplied to the plural write-in/read-out heads 7,8. Thus, the recording operation of the information can be executed at high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a magnetic disk private storage device, and more particularly, to a magnetic disk storage device having multiple storage media surfaces and multiple read/write heads. The present invention relates to a recording and reproducing circuit for a magnetic disk storage device that increases the speed of information recording and reproducing operation.

[Conventional technology]

Conventionally, during a recording operation, this type of magnetic disk storage device modulates write serial information and records it on a single selected storage medium surface through a single selected read/write head. In addition, during playback, the modulated and written recorded information is read out from the selected single recording medium through the selected single read/write head, and the read serial information is reproduced by demodulating it. It has become.

[Problem to be solved by the invention]

In the recording and reproducing operations of conventional magnetic disk drives as described above, in order to achieve the significant increase in recording and reproducing speed that has been desired in recent years, the switching frequency of the drive current of the write/read head must be significantly increased. Therefore, it is necessary to dramatically improve the frequency characteristics of the recording medium and the read/write head, but this is not always easy, and this has traditionally been an important factor preventing speed increases in magnetic disk drives.

[Purpose of the invention]

The present invention aims to solve these problems of the prior art.

In other words, the present invention enables information recording and reproducing operations to be performed several times faster than conventional methods by performing information recording and reproducing operations through parallel processing, without requiring any improvement in the frequency characteristics of the recording medium and the write/read head. The purpose of the present invention is to provide a recording/reproducing circuit for a magnetic disk device that can perform the following steps.

[Means to solve the problem]

In the present invention, a plurality of magnetic disk storage medium surfaces (9, 10
) and a plurality of read/write heads (7, 8), write serial information is sequentially set by a plurality of flip-flops (12), and written serial information is set by a synchronization bit detection means (12). , monitors the bit value set in at least one of the plurality of flip-flops (1, 2), detects the timing of setting the bit value "1", and uses the clock distribution means (13) to set the bit value "1". Value “1”
After the detection of , serial information is written to multiple flip-flops (1, 2) and set by distributing it chronologically for each bit, and the modulation writing means (3, 4, 5, 6) writes serial information to multiple flip-flops (1, 2). - The configuration is such that a plurality of write data signals sent out from the flops (1, 2) are simultaneously modulated and simultaneously supplied to a plurality of write/read heads (7, 8).

Further, the present invention provides a plurality of magnetic disk storage medium surfaces (9,
10) and a plurality of read/write heads (7, 8), the read signals from the plurality of write/read heads (7°8) are processed by the plurality of demodulators (20, 21). are demodulated respectively, and a plurality of read synchronization bit detection means (22, 2
3), the first demodulated bit value "l" after the start of reading is detected in each demodulated data, and multiple first-in/first-out memories (27, 28) are detected.
After detecting the first demodulated bit value “1”,
The demodulated signals of the demodulation means (20, 21) are stored in a first-in, first-out manner, and the readout control means (26) alternately stores data stored in the first-in/first-out memories (27, 28) at a period of 1/2 of the demodulated data. read out,
The configuration is such that the logical sum means (29) calculates the logical sum of the read stored data.

This aims to achieve the above-mentioned purpose.

[For production]

In the recording circuit of the present invention, writing serial information is sequentially set in a plurality of flip-flops, and the timing for setting the focus value "1" is determined by monitoring the bit value set in at least one of the plurality of flip-flops. After detecting the bit value “1”, multiple flips and
Write serial information is distributed and set in flops in time series for each bit, and a plurality of write data signals sent from a plurality of flip-flops are simultaneously modulated and simultaneously supplied to a plurality of write/read heads.

In addition, in the reproducing circuit of the present invention, each of the read signals from a plurality of write/read heads is demodulated, the first demodulated bit value "1" after the start of reading is detected in each demodulated data, and the first demodulated bit Value ``1''
After detection of multiple first-in, first-out,
The demodulated signal is stored in the memory in a first-in, first-out manner, and the stored data in the first-in, first-out memory is read out alternately in 172 cycles of the demodulated data, and the serial information is reproduced by calculating the logical sum of the read stored data. .

Therefore, according to the present invention, it is possible to realize a recording/reproducing circuit for a magnetic disk device that is capable of recording and reproducing information at a higher speed than before without requiring improvement of the frequency characteristics of the recording medium and the write/read head. be able to.

〔Example〕

Hereinafter, one embodiment of the present invention will be explained based on FIGS. 1 and 2.

The recording device shown in FIG. 1 is a magnetic disk storage device having a plurality of magnetic disk storage medium surfaces 9.10 and a plurality of read/write heads 7.8, and is equipped with a plurality of flip-flops 1, 2 for writing and reading. Serial information is set sequentially, and a sync bit detector 12 is provided to monitor the bit value set in at least one flip-flop of the plurality of flip-flops 1.2, and detect the bit value "1". The set timing is detected, and the clock distributor 13 is provided, and when the bit value "l" is detected, the set timing is detected.
Serial information written to multiple flip-flops 1 and 2 is distributed and set bit by bit in time series, and the modulator 3
．． 4 and a head driver 5.6, it simultaneously modulates a plurality of write data signals sent out from a plurality of flip-flops 1.2 and simultaneously supplies them to a plurality of write/read heads 7.8.

To explain this in more detail, in FIG. 1, the write serial information signal S1 is connected to the data input terminals of flip-flop 1 and flip-flop 2.

Flip-flop 1 outputs write data signal S4. The write data signal s4 is connected to the data input of the modulator 3. The modulator 3 receives a magnetization reversal signal S
Outputs 10. The magnetization reversal signal S10 is connected to the head driver 5. The head driver 5 is connected to the read/write head 7. The write/read head 7 is
It contacts the storage medium 9.

Flip-flop 2 outputs write data signal S5. Write data signal S4 is connected to the data inputs of modulator 4 and sync bit detector 12. Modulator 4 outputs magnetization reversal signal S11. The magnetization reversal signal 311 is connected to the head driver 6. Head driver 6 is connected to write/read head 8 . A read/write head 8 contacts a storage medium 10 . Storage medium 9 and storage medium 10 are connected to a spindle motor 11 .

Further, the write clock signal S2 is connected to the clock input terminals of the sync bit detector 12, the clock distributor 13, and the frequency divider 14. The sync bit detector 12 outputs a sync detection signal S6. The sink detection signal S6 is
It is connected to the clock distributor 13. Clock distributor 13
outputs a data sampling clock signal S7 and a data sampling clock signal S8.

Data sampling clock signal S7 is connected to the clock input of flip-flip1. data·
Sampling clock signal S8 is connected to the clock input of flip-flop 2. Frequency divider 14 outputs a distributed write clock signal S9. distribution light/
Clock signal S9 is connected to the clock inputs of modulator 3 and modulator 4.

Further, the write control signal S3 supplied to this circuit is connected to the control input terminals of the sync bit detector 12, the clock distributor 14, the head driver 5, and the head driver 6, respectively.

Next, the operation of the recording circuit will be explained.

The write serial information signal S1, which is information to be recorded in the magnetic disk device, is flip-flopped by the data sampling clock signal S7 and the data sampling clock signal S8 output from the clock distributor 13.
The signal is sequentially input to flop 1 and flip-flop 2 and set.

At the beginning when the write control signal S3 becomes true, the data sampling clock signal S7 and the data sampling clock signal S8 are signals having the same timing as the write clock signal S2, and the data sampling clock signal S7 and the data sampling clock signal S8 are signals having the same timing as the write clock signal S2.
The data of the serial information signal S1, which is input as a clock, is sequentially set in flip-flop 1 and flip-flop 2 at the same time.

The sync bit detector 12 monitors the data set in the flip-flop 2, detects the timing at which the bit value becomes "1" for the first time after the write control signal S3 becomes true, and Switch the clock distributor 13.

The clock distributor 13 after switching divides the write clock signal S2 by two and outputs the data sampling clock signal S7 and the data sampling clock signal S8 with a phase difference of π, so that the data of the serial information signal S1 is is alternately distributed to flip-flop 1 and flip-flop 2 and set.

The data sent to flip-flop 1 and flip-flop 2 is sent to clock signal S in frequency divider 14.
A distributed write clock signal S9 obtained by dividing 2 by 2 is sequentially supplied to the modulator 3 and the modulator 4, respectively.

The magnetization reversal signal S10 and the magnetization reversal signal Sll modulated by the modulator 3 and the modulator 4, respectively, are sent to the head driver 5.
and the head driver 6, the read/write head 7
Writing is performed on the storage medium 9 and the storage medium 10 by reversing the respective currents of the write and read heads 8 and 8, respectively.

The write control signal S3 connected to the head driver 5 and the head driver 6 stops the current of each of the write and read heads 8 when the write control signal S3 is false.

Further, the reproducing device for a magnetic disk storage device of the present invention includes a plurality of demodulation circuits 20.21, and demodulates read signals from the plurality of write/read heads 7.8, and detects a plurality of read/sync bits. A plurality of first-in first-out memories (FIFOs) 27 and 28 are provided to detect the first demodulated bit value "l" after the start of reading in each demodulated data. After detecting the demodulated bit value "1", the demodulated signals of the demodulation circuits 20 and 21 are stored in a first-in, first-out manner,
A synthesis control circuit 26 is provided to read the stored data in the first-in/first-out memories 27 and 28 alternately at a period of 1/2 of the demodulated data, and an OR circuit 29 is provided to read out the stored data in the first-in/first-out memories 27 and 28 at a cycle of 1/2 of the demodulated data. It calculates the logical sum and reproduces the serial information.

FIG. 2 is a block diagram showing a reproducing circuit according to an embodiment of the present invention.

In FIG. 2, the read pulse signal 320 supplied to the circuit is connected to the data input of the demodulation circuit 20. The demodulation circuit 20 outputs a demodulated data signal S24, a demodulated clock signal S25, and a half-cycle clock signal S23.

The demodulated data signal S24 is connected to a first-in first-out memory (FIFO) 27 and a data input terminal of a read-sync bit detector circuit 22. Demodulated clock signal 325 is connected to gate circuit 24 .

The read/sync bit detector 22 outputs a read/sync detection signal S26. Read/sync detection signal S
26 is connected to the gate circuit 24. Gate circuit 24
outputs a memory write control signal S27. Memory write control signal S27 is connected to first-in first-out memory 27.

Similarly, the read pulse signal S21 supplied to this circuit is connected to the data input terminal of the demodulation circuit 21. The demodulation circuit 21 receives a demodulated data signal 32B and a demodulated clock signal S2.
Outputs 9. The demodulated data signal 32B is connected to a first-in first-out memory (FIFO) 2B and a data input terminal of a read-sync-bit detector 23.

The read/sync bit detector 23 outputs a read/sync detection signal S30. Read/sync detection signal 3
30 is connected to the gate circuit 25. Gate circuit 25
outputs a memory write control signal S31. Memory write control signal S31 is connected to first-in first-out memory 28.

Half-cycle clock signal S23 and read/sync detection signal 3
26 and the read/sync detection signal S30 are connected to the synthesis control circuit 26. The synthesis control circuit 26 outputs a memory read control signal S32 and a memory read control signal S33. The memory read control signal S32 is connected to the read control input terminal of the first-in, fast-out memory 27. The memory read control signal S33 is
Connected to the read control input terminal of the first-in first-out memory.

First-in first-out memory 27 outputs a memory read signal 334. First in
First-out memory 28 outputs a memory read signal 335. The memory read signal S34 and the memory read signal S35 are connected to an OR circuit 29.

The OR circuit 29 outputs a read serial information signal S36.

Further, the read gate signal S22 supplied to this circuit is transmitted to the demodulation circuit 20, the demodulation circuit 21, the read/sync bit detector 22, the read/sync bit detector 23, the first-in first-out memory 27, and the first The in-first-out memory 28 is connected to the in-first-out memory 28, respectively.

The operation of the reproducing circuit according to one embodiment of the present invention will be explained with reference to FIG.

The read pulse signals S20 and 321, which are simultaneously read and pulsed from two different storage media by different write/read heads, are supplied to demodulation circuits 20 and 21, respectively. The demodulation circuit 20 aligns the phase of the read pulse signal 320 with the demodulated clock signal S25 synchronized with the read pulse signal S20, the half-cycle clock signal S23 having twice the frequency of the demodulated clock signal S25, and the demodulated clock signal S25. The demodulated data signal S24 is output.

The read sync bit detector 22 monitors the demodulated data signal S24, detects the timing at which the bit nod value becomes "1" for the first time after the read gate signal S22 becomes true, and performs a read operation. - Set the sync detection signal 326 to true.

When the read/sync detection signal S26 becomes true, the gate circuit 24 supplies the demodulated clock signal 325 as the memory write control signal S27 to the first-in/first-out memory 27, and outputs the read gate signal 322.
After becoming true, the bit whose bit value is "1" for the first time and the demodulated data signal 324 that is subsequently sent out are sequentially stored in the first-in/first-out memory 27.

Similarly, the demodulation circuit 21 outputs a demodulated clock signal S29 that is synchronized with the read pulse signal S21, and a demodulated data signal 328 that has the phase of the read pulse signal S21 aligned with the demodulated clock signal S29. The read sync bit detector 23 monitors the demodulated data signal 32B, detects the timing at which the bit value becomes "1" for the first time after the read gate signal S22 becomes true, and detects the read sync bit detector 23. It is assumed that the detection signal S30 is true.

When the read/sync detection signal S30 becomes true, the gate circuit 25 supplies the demodulated clock signal 329 as the memory write control signal S31 to the first-in/first-out memory 28, and after the read gate signal 322 becomes true, The bit whose bit value is "1" first and the demodulated data signal 828 that is subsequently sent out are
Sequentially, first-in first-out memory 28
Store in.

The synthesis control circuit 26 monitors the read/sync detection signal 326 and the read/sync detection signal S30 to confirm that writing to the first-in/first-out memory 27 and the first-in/first-out memory 28 has started. and the first written bit value”
1" simultaneous readout and subsequent alternate readout are instructed to the first-in/first-out memory 27 and the first-in/first-out memory 28 via memory read signals 332 and 333 at the timing of the half-cycle clock signal S23. do.

The memory read signals 334 and 835 read from the first-in/first-out memory 27 and the first-in/first-out memory 2B are synthesized by the OR circuit 29, and the read serial information signal 33 is synthesized by the OR circuit 29.
Sent as 6.

Through the operations described above, the write serial information signal S1 is distributed and recorded on the storage media 9 and 10 in a manner that the first bit value of the data "1" is shared.
When reading the information distributed and recorded as 0, the data of the write serial information signal Sl can be reproduced by combining the first bit value "1" of each demodulated signal as a reference.

In each of the above embodiments, an example was shown in which information is simultaneously recorded and reproduced on two sides of a magnetic disk storage medium, but simultaneous recording and reproduction on a larger number of storage medium sides can be easily realized using a similar method.

[Effects of the Invention] As explained above, the recording/reproducing circuit of the magnetic disk device of the present invention changes the first bit value of the data detected by the sync bit detector of the written serial information to "1" during recording. Successive data is distributed chronologically into multiple signals that are simultaneously modulated and recorded via multiple write/read heads onto multiple storage media surfaces simultaneously. Also, during playback, reading and demodulating operations from multiple write/read heads are performed simultaneously, and the data following the first bit value "■" detected by the read/sync bit detector of each demodulated signal is By chronologically synthesizing the data, it is possible to double the recording and reproducing operation speed without changing the current switching frequency for the write/read head, so it is necessary to improve the frequency characteristics of the recording medium and the read/write head. It becomes possible to significantly increase the speed of information recording and reproducing operations without having to do so.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a recording circuit according to an embodiment of the invention, and FIG. 2 is a block diagram showing a reproduction circuit according to an embodiment of the invention. 1.2...Flip-flop, 3.4, 5.6...
- Modulation writing means, 7.8... Writing/reading head, 9.10... Magnetic disk storage medium surface, 12.
... Synchronization bit detection means, 13 ... Clock distribution means, 20.21 ... Demodulation means, 22.23 ... Synchronization bit detection means, 26 ... Readout control means, 27°2
8...First-in, first-out memory (
FIFO), 29... logical sum means. Applicant Nippon Electric Co., Ltd. Agent Patent Attorney Yuka Takahashi δJ Re-T circuit Σ36 (Yu distribution serial S bribe 5i Migo)

Claims (2)

[Claims] (1) In a magnetic disk storage device having a plurality of magnetic disk storage medium surfaces and a plurality of write/read heads, a plurality of flip-flops for sequentially setting write serial information and at least one of the plurality of flip-flops are provided. and synchronous bit detection means for monitoring the bit value set in the flip-flop to detect the set timing of the bit value "1", and after detecting the bit value "1", the plurality of flip-flops a clock distributing means for distributing and setting the write serial information bit by bit in time series; and a clock distribution means for distributing and setting the write serial information bit by bit; and a clock distribution means for simultaneously modulating a plurality of write data signals sent from the plurality of flip-flops to the plurality of write/read heads. What is claimed is: 1. A recording circuit for a magnetic disk storage device, comprising: modulation writing means for simultaneously supplying modulation. (2) In a magnetic disk storage device having a plurality of magnetic disk storage medium surfaces and a plurality of write/read heads, a plurality of demodulating means for respectively demodulating read signals from the plurality of write/read heads, and each of the demodulated data The first demodulated bit value “1” after the start of reading in
a plurality of read synchronization bit detection means for detecting "1", and a plurality of first-in first-out memories for storing the demodulated signal of the demodulation means in a first-in, first-out manner after detection of the first demodulated bit value "1"; , comprising a read control means for alternately reading out the stored data of the first-in first-out memory at a period of 1/2 of the demodulated data, and an OR means for calculating the logical sum of the read stored data. A playback circuit for a magnetic disk storage device characterized by: