JPH0450769B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pseudorandom binary sequence generator.

Pseudo-random binary sequence generators are known, and their construction and operation are described in Baker and Piper, Cryptographic Systems, London, 1982.
Published by Northwood Books.
In particular, this type of generator takes the form of a linear feedback shift register, which in particular is of the "Galois" or "dual" type.

Such pseudo-random binary sequence generators primarily consist of n-stage recirculating shift registers and one
One or more associated logic gates are included in a loop coupling the outputs of at least two shift register stages. By appropriate selection of logic gates, repeating sequences of length 2 ⁿ -1 bits can be obtained. If n is a suitably large number, this sequence can be very long in practice, and the bits can be considered random and therefore "pseudo-random."

It is necessary to reduce the possibility that the outputs of pseudorandom binary sequence generators are imitated, and even if the output signals of these generators and the contents of several shift register stages are known. There are many applications where it is necessary to increase the unpredictability of both.

The gist of the invention will be apparent from the claims below.

Embodiments of the invention will be explained with reference to the drawings.

The pseudo-random binary sequence generator of the present invention, shown in FIG. 1, comprises two linear feedback shift registers S and T. The shift register S is provided with 29 shift register stages S ₀ ...S ₂₈ , and the shift register T is provided with 31 shift register stages T ₀ ...T ₃₀ . Each shift register provides the output of the last shift register stage as an input to the first shift register stage of the recirculation loop during normal operation. This loop is also provided with a plurality of logic gates G in the form of exclusive OR circuits, which connect the output of the last shift register stage and the output of the associated shift register stage to feed the next shift register stage. Synthesize.

The location of the logic gate G is chosen accordingly so that the length of the sequence generated by the register is the maximum possible length. The position of a conventional logic gate can be expressed in polynomial form as expressed by the following equation.

f(x)=1+C ₁ X+C ₂ X ² + ^... C _i X ⁱ + _{... C} ^o -1 I can do it.

1 + X ² ₊ X ^{3 +} X ⁴ ₊ X ⁵ + _X ⁷ + X ¹¹ + X ¹³ + X ¹⁴ _{+ X} ²⁰ ₊ , S ₁₃ , S ₁₄ and S ₂₀ . There are therefore nine logic gates, and each gate introduces an additional term into the polynomial.

Similarly, the logic gate G of the pseudo-random binary sequence generator T also has shift register stages T ₁ ,
T ₂ , T ₃ , T ₅ , T ₆ , T ₇ , T ₉ , T ₁₀ , T ₁₁ , T ₁₅ ,
It will be located on the input side to T ₁₉ , T ₂₃ and T ₂₇ . In this case there are 13 logic gates.

The circuit shown in FIG. 1 also includes a multiplexer M,
That is, a selection circuit is provided. This selection circuit has 5 address input terminals A _i and 32 data input terminals.
A selection circuit B _i is provided which selects one of the data input terminals to be supplied to the output according to the address word supplied to the address input terminal. Generally, when there are p data input terminals, q
There are address input terminals, where q is 2 ^q ≧
Let p be the lowest value that satisfies.

The data input terminal is supplied with the output of the shift register stage of the shift register T, so that T _i is connected to B _i (i=0, 1, . . . 30) and T ₃₀ is also connected to B ₃₁ .

The address input terminals are supplied with the outputs of the first five shift register stages of the shift register S, so that S _i is connected to A _i (i=0, 1, 2, 3,
4) As a result, q outputs can be obtained from the shift register S.

In operation, the two shift registers S and T are clocked simultaneously. The 31 bits of the pseudo-random binary sequence held in the shift register T are applied to the data input terminal of the selection circuit M. One of these bits is selected as the output at any instant. This selected bit depends on the contents of the first five shift register stages of shift register S. Therefore, even if the contents of the shift register T are known, it is difficult to predict the number of outputs.

The total number of shift register stages included in the shift register is greater than the number of shift register stages required to obtain only the q-bit address and p data bits, which is 60. When the total number of shift register stages is r, the following equation holds true.

r>p+q If the outputs of these shift register stages are not supplied to the selection circuit M, it is necessary to provide a large number of "unused" shift register stages, and this number needs to be large compared to the number of address bits. is clear. Therefore, the following equation holds.

r≧p+q ^2The provision of these unused shift register stages increases the unpredictability of the address word, thus making it possible to predict the output of the pseudo-random binary sequence generator even if the contents of the shift register T are known. It can be done without benefit.

It is also obvious that the number of logic gates G used in the shift register is large, 22 in this example. As mentioned above, these logic gates are selected in such a way that a sequence of maximum length is obtained in each case. However, it is not necessary to use such a large number of gates solely for this purpose.

However, the greater the number of logic gates, the more difficult it becomes to predict the contents of the shift register. The reason is that the predetermined sequence is not easily phased from the beginning to the end of the shift register and can change at many points.

If the minimum number of logic gates this accumulates is s, then the following equation is obtained, which increases the degree of unpredictability for the total number of shift register stages.

2 ^s ≧ r ² If the total number of shift register stages is 60, a minimum of 12 logic gates must be provided, and in this case the minimum number for each shift register should be approximately proportional to the number of shift register stages. is suitable. The value of s is usually smaller than r/2.

As is clear from the drawing, switches SW1 and SW
2, SW3 and SW4 are provided so that in normal running conditions two recirculation loops can be formed around the shift registers S and T. However, these four switches can be switched from the position shown to the load position, in which the output of shift register S is supplied as the input of shift register T, and all of the logic gates G are supplied with the output of that shift register. The side supplies a zero value to the input side which is normally sustained. A 60-bit initialization word can then be applied to the load input terminal of clocked switch SW1 through all 60 shift register stages.

This reinitialization operation is properly performed during normal operation of the binary sequence generator upon receipt of a defined cue, and is performed as described below with respect to FIG. This also makes it impossible to predict the output even if the contents of the shift register are known at any given moment.

After receiving the initialization word, the binary sequence generator must be clocked for several cycles before its output can be used.

FIG. 2 shows a modification of the pseudo-random binary sequence generator of FIG. Since most of the apparatus of this example is the same as the apparatus shown in FIG. 1, only the differences will be described.

In this example, the shift register S has 29 shift register stages, and the shift register T has 31 stages.
shift register stages are provided. A logic gate is also coupled to the input side of the shift register stage shown below. Shift register S - shift register stage S ₂ ,
S ₃ , S ₄ , S ₈ , S ₁₁ , S ₁₆ and S ₂₀ Shift Register T - Shift Register Stages T ₁ , T ₂ ,
T ₃ , T ₇ , T ₁₄ , T ₁₉ and T ₂₅ Therefore, in this example there are a total of 60 shift register stages, 32 data input terminals and 5 address input terminals of the selection circuit M, and 14 A logic gate is provided.

However, in this case several of the shift register stages of each shift register are respectively connected to several of each of the data and address input terminals. That is, this connection is shown below.

A ₀ −S ₀ A ₁ −S ₁ A ₂ −T ₀ A ₃ −T ₁ A ₄ −T ₂ B ₀ ~B ₇ −S ₂ ~S ₉ (corresponding to each) B ₈ ~T _31- T ₃ ~T ₂₆ (corresponding to each) By thus mixing the output of the shift register and the input of the selection circuit M, it is extremely difficult to predict the operation of the binary sequence generator even if most of its state is known. It is.

FIG. 3 shows yet another example of the pseudorandom binary sequence generator of the present invention. In this example, instead of the two shift registers of FIGS. 1 and 2, a single shift register S having 61 shift register stages S ₀ to S ₆₀ is provided. Also, 25 logic gates G
is connected to the input side of the next shift register stage as shown.

Shift register stages S ₂ , S ₃ , S ₇ , S ₈ , S ₉ , S ₁₀ ,
S ₁₂ , S ₁₅ , S ₁₉ , S ₂₀ , S ₂₂ , S ₂₄ , S ₂₅ , S ₂₈ , S ₃₀ ,
S ₃₃ , S _{34 ,} S ₃₇ , S 40 , S ₄₃ , S ₄₄ , S ₄₆ , S ₅₄ , S ₅₆ and S ₆₀ This results in 5 address bits A ₀ ...
…A ₄ is the shift register stage S ₄ , S ₉ , S ₁₄ , S ₁₉ and
_S24 and 32 data bits from the outputs of shift register stages _S29 to _S60 . A single recirculating loop thus provides outputs to both the data and address inputs of multiplexer M.

In this case, only two switches SW1 and SW2 are required for reinitialization with the 61-bit initialization word.

The pseudo-random binary sequence generator shown in FIG. 3 also allows a single recirculating loop to be used to supply the address and data input bits of multiplexer M.

According to the prior art, such generators have been described and explained in terms of separate circuits. However, the description and claims similarly provide for carrying out the invention in the form of a computer program that reproduces the polynomials of the generator mathematically or by logical steps to generate a composite sequence similar to the generator described above. The applicability is clear.

The output of the pseudorandom binary sequence generator can be used to scramble the signal components of a conditional access (or subscription) television signal, such as a direct satellite broadcast signal. According to the reinitialization operation described above, it is preferable to transmit a new code every 10 seconds to scrabble the video signal;
Repeat many times during a period of seconds. The reason is that the maximum time to lock the decoder needs to be significantly less than 1 second. However, this means that the image information is scrambled by repeating the same sequence. This is relatively dangerous. The reason is that correlations between different parts of the scrambled image can be performed.

To count television frames, use 8-
A Bit Frame Count Word (FCNT) is transmitted directly with a television signal, such as a satellite broadcast signal. This counting is advanced every 40 ns (every frame) and repeated after a predetermined number of frames, for example every 256 frames (approximately 10 seconds).

This frame count word (FCNT) may then be provided as input to a pseudo-random binary sequence generator at the transmitter and to an associated generator at the receiver's decoder. To this end, both a frame count signal and a secret control signal are provided to the transmitter's pseudo-random binary sequence generator at the beginning of each television frame. The use of the frame count signal has an effect on the binary sequence generator to produce different outputs during each loading of the same control word value. This means that the image signal is always scrambled with a different key stream, which is more secure. Furthermore, since each sequence occurs every television frame (40 ns), the decoder can quickly access the video information. Frame count words can be combined with control words as appropriate. In this case, a simple modulo-2 addition can be performed.

The operation described above will be explained below with reference to FIG.

A frame counter 10 produces an output in the form of so-called 8-bit words that increases from frame to frame. The frame counter supplies its output 10a to the frequency divider circuit 11 every time it performs a step operation, which divides the frequency by a number equal to the required length of the repetition period, in this example 256, and divides the frequency into 10 seconds. Try to get the repetition period. The output of the frequency divider circuit clocks control word generator 12, which generates control words of different lengths, such as 60-bit control words.

The 8-bit output of the frame counter is applied to a divide-by-2/2 inverter circuit 14 where each 8-bit frame count word is alternately complemented. The output of inverter circuit 12 is then applied to a modulo-2 adder, represented by exclusive-OR gate 15, which adds each frame count word modulo-2 to a byte consisting of a 60-bit control word. This allows the first 8-bit byte of the control word to be modulo 2 in the first frame count word.
add the second byte to the complement of the second frame count word, add the third byte to the third frame count word, and repeat until the last byte.
This last byte is only 4 bits for the 60-bit control word and is added to the least significant 4 bits of the complement of the 8th frame count word. The output of the exclusive OR gate 15 is supplied as an initialization input to a pseudo-random binary sequence generator 16 for each frame count, i.e., to the frame counter 10.
Loads this generator every time the stage advances. The generator 16 may be any of the generators described above, but is preferably the generator shown in FIG.

The input of the pseudo-random binary sequence generator is therefore supplied with two types of signals, one signal (frame count) being known and the other signal (control load) being unknown. In such a state, the unknown input cannot be detected by both the known input and the output of the generator. This allows the same control word to be loaded repeatedly into the pseudo-random binary sequence generator, but prevents its output from being repeated in the same sequence, thereby increasing security.

The processing described above can be performed word by word or in series.

Frame counting is a suitable periodic sequence for this purpose, but not an absolute sequence. For example, suitable counts may be derived from an associated data signal, such as a date/time signal, or from other counts, such as line counts, or from a combination of these counts.

[Brief explanation of the drawing]

1, 2, and 3 are block circuit diagrams showing the configuration of each pseudo-random binary sequence generator according to an embodiment of the present invention, and FIG. 4 is a block circuit diagram of the pseudo-random binary sequence generator shown in FIG. 1, 2, or 3. FIG. 2 is a block diagram illustrating a circuit for changing the input to the circuit. M...Selection means, _B0 to _B31 ...Data input terminals, _A0 to _A4 ...Address input terminals, G...Logic gates, S, T...Recirculation shift register means,
10...Frame counter, 10a...Output, 11
... Frequency divider circuit, 12 ... Control word generator, 14
...1/2 frequency divider/inverter circuit, 15... Exclusive OR gate, 16... Pseudo-random binary sequence generator.

Claims (1)

[Scope of Claims] 1 has p data input terminals B ₀ to B ₃₁ and q address input terminals A ₀ to _{A 4} , 2 ^q ≧p, and one of the data input bits according to the address input word. a selection means M for selecting at any instant an output of the device, the number of address input terminals q being in particular the minimum number necessary for the address of each of the p data input terminals; recirculating shift register means S having s shift register stages and s logic gates G located between the shift register stages and logically combining the outputs of selected shift register stages to generate a pseudo-random sequence; T and the p data input terminals of the selection means are connected to the output terminals of the selected shift register stages, and the q address input terminals of the selection means are connected to the output terminals of the q selected shift register stages. a pseudo-random binary sequence generator comprising means for connecting said logic gates, wherein said number r of shift register stages is greater than the number required only to generate q-bit addresses and p data bits; A pseudo-random binary sequence characterized in that the number s of the recirculating shift register means is larger than the minimum value for the total number of shift register stages, and the condition 2 ^S ≧ r ² expressed by the following equation is satisfied. generator. 2 Condition r where the number r of shift register stages is expressed by the following formula
The pseudo-random binary sequence generator according to claim 1, characterized in that ≧p+q ² is satisfied. 3. The recirculating shift register means S, T comprise at least one recirculating loop, and by means of said connecting means several output terminals of the shift register stages of said loop are connected to the data input terminal of said selection means. A pseudo-random binary sequence generator according to claim 1 or 2, characterized in that the other output terminals of the shift register stages in the same loop are connected to the address input terminal of the selection means. . 4. The recirculating shift register means comprises two recirculating loops, each of which is connected to each of the data input terminals of the selection means and to each of the address input terminals of the selection means. A pseudorandom binary sequence generator according to claim 1 or 2. 5. Pseudo-random binary sequence generator according to any one of claims 1 to 4, characterized in that it comprises loading means for correctly loading the re-initialization word into the recirculating shift register means. . 6. The recirculating shift register means comprises first and second shift registers, the first shift register S having a characteristic primitive polynomial 1+X ² +X ³ +X ⁴ +X ⁵ +X ⁷ +
X ¹¹ +X ¹³ +X ¹⁴ +X ²⁰ +X ^{29 ,} and the second shift register T has ^the characteristic primitives 1 ⁺ X ⁺
+X ⁷ +X ⁹ +X ¹⁰ +X ¹¹ +X ¹⁵ +X ¹⁹ +X ²³ +X ²⁷ +
Pseudo-random binary sequence generator according to claim 1, characterized in that it has X ³¹ . 7. The recirculating shift register means comprises first and second shift registers, the first shift register S having a characteristic primitive polynomial 1+X ² +X ³ +X ⁴ +X ⁸ +X ¹¹
+X ¹⁶ +X ²⁰ +X ²⁹ , and the second shift register T
is the characteristic primitive polynomial 1+X+X ² +X ³ +X ⁷ +X ¹⁴ +
Pseudo-random binary sequence generator according to claim 1, characterized in that it has X ¹⁹ +X ²⁵ +X ³¹ . 8. The recirculating shift register means has a shift register S, which has a characteristic primitive polynomial 1+X ² +X ³ +X ⁷ +X ⁸ +X ⁹ +X ¹⁰ +X ¹² +
X ¹⁵ +X ¹⁹ +X ²⁰ +X ²² +X ²⁴ +X ²⁵ +X ²⁸ +X ³⁰ +
X ³³ +X ³⁴ +X ³⁷ +X ⁴⁰ +X ⁴³ +X ⁴⁴ +X ⁴⁶ +X ⁵⁴ +
Pseudo-random binary sequence generator according to claim 1, characterized in that it has X ⁵⁶ +X ⁶⁰ +X ⁶¹ .