JPH0448305B2 - - Google Patents

Description

[Detailed description of the invention]

[Summary] The present invention aims to eliminate variations and fluctuations in packet reception delay time and maintain a constant delay time in a packet switch that performs continuous signal communication such as voice and moving images. By adjusting the packet arrival time within a fixed time range, fluctuations in packet arrival times can be kept within the fixed time range at the receiving end. [Industrial Application Field] The present invention relates to a packet switch, and particularly to a packet switch that performs continuous signal communication such as audio and video signals. So-called continuous signal communication, such as audio and video, requires a constant transmission delay while a path (call) from a calling terminal to a receiving terminal is set up. On the other hand, packet-switched networks are extremely promising for constructing future integrated networks because they can accommodate continuous signal communications such as voice and video as well as intermittent (burst) signal communications such as data communications using the same switch. be. In such a packet network, the transmission time for a packet to be transferred from a source terminal to a destination terminal fluctuates from moment to moment due to fluctuations in packet processing time in a packet switch, queues for packets to be sent to a transmission path, and the like. Therefore, at the packet receiving terminal, it is necessary to add a delay time to the received packet so that the total delay time is constant. [Prior Art] An example of the basic configuration of a conventional voice/data integrated packet switching network is shown in FIG. 8a. The audio signal from the transmitter 100 is converted into a digital signal by the AD converter 102 in the audio packet transmitter 101, and this is sent to the packet assembler (PA) 1.
03 Convert to the packet format shown in Figure 8b. At this time, a sequence number (SQ) is added to the packet, which increases by "1" each time the packet is assembled. This is done by the subsequent packet switch 104.
This is so that even if a packet is lost due to a bit error or the like occurring on the transmission path 105, it can be detected on the receiving side. On the other hand, the data terminal 106 generates packets at arbitrary timing, that is, asynchronously. To prevent data errors, data packets undergo sequence number management that is different from voice packets. Packet switch 104 transfers the voice packet from transmitter 100 and the data packet from data terminal 106 to a predetermined output route by referring to the transfer header (FIG. 8b). The arrival timing of the packets arriving at the receiving terminal varies; however, by temporarily accumulating the delay fluctuations in the voice packet receiving section 107 of the receiving terminal in a buffer (FIFO buffer) 108, the delay time can be reduced. Make it constant. Thereafter, the packet disassembly section 109 extracts the packet from the buffer 108, removes the header, etc. of the packet, and extracts the digital audio signal. At this time, the sequence number (SQ) of the packet is referenced, and if a missing sequence number is detected, a silent pattern is inserted. Finally, the DA converter 110 converts the digital signal into an analog signal and outputs it to the receiver 111. [Problems to be Solved by the Invention] In the conventional voice/data integrated packet network, since the packet exchange process within the network is asynchronous even in voice signal processing, the packet transmission unit 101 to the packet reception unit 107 is The transmission delay of the packet is uncertain. In particular, as the traffic density of the transmission line increases, the packet transmission delay increases rapidly.
This is not a big problem if the speed is over Mbps, but if the transmission line speed drops below several hundred Kbps or the number of relay stages in the packet switch increases, serious problems such as echoes will occur. SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a packet switch capable of keeping the transmission delay time and fluctuations thereof of continuous signal packets transmitted within a packet network within an allowable range. [Means for solving the problem] In order to achieve the above purpose, FIG. 1 shows a system that determines the output route corresponding unit 2 to which the packets are to be distributed based on the logical channel number of the packets that arrive at the packet switch 1 at regular intervals and transfers the packets. This figure shows a schematic diagram of a packet switch, and in the present invention, each output path corresponding section 2 is
A time adjusting unit 3 that gives three types of delay times to arriving packets and sends them out to the transmission path; a pulse generating circuit 4 that generates pulses with the same period as the fixed period; A call expected sequence number generation circuit 5 that generates the expected sequence number of the packet compares the sequence number of the packet with the expected sequence number, and only when the difference is -1, 0, +1, a constant value is generated correspondingly. A control circuit 6 selectively controls one of the delay times of the time adjustment section 3 so that a delay time of
It is equipped with. [Operation] In FIG. 1, assembled packets arrive at the packet switch 1 at a constant period with fluctuations back and forth in time. A logical channel number (LCN) is added to this packet to identify the call, as shown in Figure 2.
This logical channel number allows packet switch 1 to
determines the output route correspondence unit 2 to which the packet is to be distributed and forwards the packet. The output path handling unit 2 is also provided with a pulse generation circuit 4 that generates pulses at the same period as the above-mentioned constant period, and a call is expected according to the pulse at the constant period and the logical channel number of the packet. A sequence number is generated from a call expected sequence number generation circuit 5, and a control circuit 6 compares this expected sequence number with the sequence number in the sent packet to determine the difference between the two. The control circuit 6 further selects and controls the three types of delay times given by the time adjustment section 3 according to the difference, so that the packet is kept within the allowed fixed delay time and sent to the transmission path. FIG. 3 shows the above operation over time. In the figure, synchronous communication packets are generated at a period T from a packet generation source (not shown). When this packet passes through packet switch (PSW) A, the time at which the packet appears at the exit of packet switch 1 varies stochastically within the shaded range due to fluctuations in processing time within packet switch A. Then, the control circuit 6 compares the sequence number of the received packet with the expected sequence number, transfers the packet at any delay time within the time adjustment section 3, and then outputs it to the transmission path A. At this time, the variation range of the time at which the packet is output to the transmission path A falls within the time interval T between the periodic pulses of the output path corresponding section A. Next, when the packet from transmission path A passes through packet switch B, the variation range of the arrival time of the packet at the exit of packet switch B expands to the range shown by diagonal lines. However, even in this case, when the packet passes through the output path corresponding section B, the variation range of the time at which the packet is output to the transmission path B falls within the time interval T between the periodic pulses of the output path corresponding section B. In this way, no matter how many packet relay stages there are, the timing at which packets of the same call pass through a transmission path can be determined by giving a certain delay time to each output path corresponding to the output path connected to that transmission path. It falls within a certain time interval between periodic pulses of the path corresponding part. In other words, it can be seen that the variation in delay time from the originating and terminating terminal to the terminating terminal is always less than or equal to the period T. [Embodiment] Next, an embodiment of the packet switching equipment according to the present invention will be described. FIG. 4 is a block diagram showing an embodiment of the packet switching device of the present invention, in which the time adjustment section 3 shown in FIG.
consists of three continuously connected FIFOs (First-In
First-Out) memories 11 to 13, synchronous packet output FIFO memory 14, and FIFO memories 11 to 13
a switch SW1 that controls packet transfer to
It is made up of. Further, the call expected sequence number generation circuit 5 includes a counter ESQ-O which is provided corresponding to the number of calls, each has a sequence number expected by the call, and is counted up by the pulse generation circuit 4.
~ESQ-N, switch SW2 for selecting these counters, and switch SW2 for selecting these counters, and switch SW2 for selecting these counters according to the logical channel number (LCN) of the packet for call identification.
a switch control logic circuit 21 for controlling 2;
It is made up of. Furthermore, the control circuit 6 includes a subtracter 22 that compares the expected sequence number ESQ from the switch SW2 and the sequence number in the received packet and calculates the difference.
The switch control logic circuit 23 controls the switch SW1 according to the difference. Next, to explain the operation, first, the output route corresponding section 2
Then, the circuit 21 controls the switch SW2 according to the LCN (i.e., the call identification number) of the packet, and the related counters are divided into counter groups ESQ-O to ESQ-N.
Choose from. The counter is set with a sequence number (ESQ) expected for the packet of the call. Incidentally, the counter group increments all the counters by "1" every time a periodic Hals of period T is generated from the circuit 4. Immediately after a call is connected, the expected sequence number (ESQ) is undefined, and the sequence number SQ of the hacker and the expected sequence number ESQ are completely unrelated. Therefore, the packet sequence number SQ
If it is outside the range of ESQ-1 to ESQ+1, the logic circuit 23 discards the packet by not connecting the switch SW1 to anything, and adds "1" to the counter specified by the control logic circuit 21. By gradually changing the expected sequence number ESQ. This is the maximum
It is performed for the modulus of the sequence number. In this way, once the sequence number SQ is ESQ-1
If it falls within the range of ~ESQ+1, it will become stable from then on. Then, the subtracter 22 calculates SQ−ESQ, and the logic circuit 23 switches the switch SW1 so that SQ=ESQ+1 → transfers the packet to the FIFO 11.
Switch. In addition, the output path handling section transfers the contents of the FIFO 13 to the periodic packet output FIFO 14 every time a periodic pulse of period T occurs, and transfers the contents of the FIFO 12 to the FIFO 12.
13, and the contents of FIFO 11 are transferred to FIFO 12. On the other hand, the periodic pulse output FIFO 14 sequentially sends out the packets therein to the transmission path. In this manner, the time adjustment section 3 provides three types of packet delay times to keep the delay time variation within the period T as shown in FIG. Next, another embodiment of the present invention shown in FIG. 5 will be described. In FIG. 5, the time adjustment section 3 shown in FIG.
consists of four FIFO memories 30 to 33, a switch SW3 that selects one of these as the periodic packet output FIFO, and this switch SW3.
The switch is set to a predetermined positional relationship with the position of
It consists of SW4. The call expected sequence number generation circuit 5 also includes a common counter 41 counted up by the pulse generation circuit 4, an offset table 42 storing offset numbers corresponding to packet sequence numbers (LCN), and a common counter 41. and an adder 43 that adds the count of 0 and the offset sequence number of the offset table 42 to generate the expected sequence number of the call. still,
The adder 44 is an adder that adds "1" to the offset table 42 when a packet is discarded. Further, the control circuit 6 outputs the expected sequence number ESQ.
and a subtracter 51 that subtracts the sequence number SQ.
Based on this subtracted value, the switch SW3 of the time adjustment section 3 is
and a switch control logic circuit 52 that controls SW4 in a predetermined relationship, and the output of the subtracter 51 is -1,
The switch control logic circuit 53 controls the switch SW5 to discard the packet and count up the offset number when the offset number is neither 0 nor +1. In addition, in the configuration of the output path corresponding section shown in FIG.
It is necessary to transfer data from FIFO 11 to FIFO 12 instantaneously. However, since the input/output speed of FIFO is finite,
This is difficult. Furthermore, it is difficult to provide a large number of counter groups. To solve this,
In the embodiment shown in FIG. 5, the FIFO of the time adjustment section 3 is of a circulating type. Furthermore, in FIG. 5, a control circuit 60, a switch SW6, and a FIFO 70 are also included for processing not only synchronous communication packets but also asynchronous communication packets. Next, the operation will be described. The packet switch (PSW) 1 outputs packets to be sent to the same output route, synchronous communication packets are output to terminal P1, and asynchronous communication packets are output to terminal P0. Terminal P
The asynchronous communication packets starting from 0 are stored in the asynchronous packet output FIFO 70. On the other hand, the synchronous communication packet from terminal P1 is
First, referring to the offset table 42 using the logical channel number (LCN) as an index,
The read value (offset value) and the value of the common counter 41 are added by an adder 43 to obtain the expected sequence number ESQ of the call. Here, common counter 4
1 is counted up by a pulse with a period T generated by the periodic pulse generating circuit 4. Therefore, the expected sequence number ESQ is also “1” in period T.
The count is increased one by one. That is, by switching the offset value according to the logical channel number (LCN) of the packet received from the packet switch 1, the expected sequence number ESQ represented by "offset value + common counter value" changes. Furthermore, by simply counting up one common counter 41, the expected sequence numbers ESQ corresponding to all logical channel numbers LCN will be counted up at the same time. In the control logic circuit 53, the subtracter 5
The following operation is performed depending on the value of SQ-ESQ output from 1. () If SQ-ESQ=+1, 0, or -1, close the upper side of switch SW5 and open the lower side. () SQ−ESQ=Switch if other than above
Open the upper side of SW5 to discard the packet, close the lower side of switch SW5, and set "1" to the offset value for the current logical channel number (LCN).
The added value is written into the offset table 42. Immediately after the call is connected, the value of ESQ is indeterminate, so the state is in () above, but as the operation in () is repeated, the condition in () is satisfied, and from then on,
() continues. On the other hand, in the control logic circuit 52, every time a pulse with a period T is generated from the circuit 4, the switch SW3 is
Contact number 0, 1, 2, 3, 0, 1, 2, 3,
Rotate it as 0,... The FIFO pointed to by switch SW3 is the synchronous packet output at that time.
FIFO, and from there, in order of increasing contact number (in order of elapsed delay time), FIFO-, FIFO-
, FIFO−. That is, SW3
FIFO− → synchronous packet output every time the rotates
FIFO, FIFO−→FIFO−, FIFO−→
This is the same as a FIFO- transfer. Also, at some point, the synchronous packet output FIFO
The old one becomes FIFO− at the next point, but
At that time, the packets in the FIFO are output and become empty. The control logic circuit 52, as described above,
Dynamically associate FIFOs 30 to 33. and SQ
- Operate switch SW4 as follows according to ESQ. () If SQ−ESQ=+1, the FIFO corresponding to FIFO−, that is, contact number +3 of SW3
Set SW4 and transfer the packet to the FIFO. () If SQ−ESQ=0, switch to the FIFO corresponding to FIFO−, that is, SW3 contact number +2.
4 and transfer the packet to the FIFO. () If SQ-ESQ=-1, the FIFO corresponding to FIFO-, that is, the contact number of SW3 +1
Set SW4 and transfer the packet to the FIFO. () SQ−ESQ=If other than the above, as above
SW4 is irrelevant because the packet is discarded in SW4. The control circuit 60 regards the FIFO designated by the switch SW3 as the synchronous packet output FIFO, and as long as there is a packet there, sets the switch SW6 to the contact 2 side and sends out the synchronous communication packet to the transmission line. When the FIFO becomes empty, the switch SW6 is set to the contact 1 side, and an asynchronous communication packet is taken out from the asynchronous packet output FIFO and sent to the transmission line. FIG. 6 shows an example of the configuration of the control logic circuit 52. FIFO specification counter 7 for synchronous packet output
1 outputs the contact number of switch SW3 that indicates the current synchronous packet output FIFO. Then, the adder 72 (2-bit adder) adds "2" to the contact number of the switch SW3 and executes the addition of the modulus 4. This relationship is shown in the table below.

〔Effect of the invention〕

According to the packet switch of the present invention, the packet delay time is adjusted to a constant value based on the relationship between the expected sequence number of the call and the sequence number of the packet itself using pulses generated at the same cycle as the packet generation cycle. Therefore, no matter how many stages a synchronous communication packet is relayed through packet exchanges, the fluctuation width of the delay time can be kept within the pulse generation cycle, and the delay time per relay stage can be twice the cycle. There is a guaranteed effect within the range. Therefore, the capacity of the fluctuation absorption buffer at the receiving end of synchronous communication packets can be significantly reduced.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the principle of the packet switching equipment according to the present invention, FIG. 2 is a diagram showing the packet type used in the present invention, FIG. 3 is a diagram for explaining the operating principle of the present invention, and FIG. The figure is a block diagram showing one embodiment of the present invention, FIG. 5 is a block diagram showing another embodiment of the present invention, and FIG. 6 is a configuration example of a switch control logic circuit used in the embodiment of FIG. FIG. 7 is a diagram showing a form of packet transfer on a transmission path, and FIGS. 8a and 8b are diagrams showing an example of the basic configuration and packet type of a conventional integrated voice/data packet switching network, respectively. In FIGS. 1, 4, and 5, 1 is a packet switch, 2 is an output path handling section, 3 is a time adjustment section, 4 is a pulse generation circuit, 5 is a call expectation sequence number generation circuit, and 6 is a control circuit. , is shown. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Scope of Claims] 1. In a packet switch that determines an outgoing path handling unit 2 to which a packet is to be distributed based on the logical channel number of a packet that arrives at a packet switch 1 at a constant cycle and transfers the packet, each outgoing path handling unit 2 transmits the packet. a time adjustment unit 3 that gives three types of delay times to the signal and sends it out to the transmission path; a pulse generation circuit 4 that generates the pulse of a certain period; and a sequence number that a call is expected to receive according to the pulse and the logical channel number. A call expected sequence number generation circuit 5 that generates a call packet compares the sequence number of the call packet with the expected sequence number, and only when the difference is -1, 0, or +1, a certain delay time is set correspondingly. A control circuit 6 for selectively controlling one of the delay times of the time adjustment section 3 so as to obtain the desired delay time. 2 The time adjustment section 3 has three cascade-connected
FIFO memories 11 to 13 and synchronous packet output
2. The packet switching equipment according to claim 1, comprising a FIFO memory 14 and a switch SW1 for selecting one of the three FIFO memories 11 to 13 according to the output of the control circuit 6. 3 The time adjustment section 3 has four FIFO memories 30
33 and the above according to the output of the control circuit 6.
A switch SW that specifies one of the FIFO memories 30 to 33 as the synchronous packet output FIFO memory and switches the remaining FIFO memories and the synchronous packet output FIFO memory to provide the three delay times.
3. The packet switching device according to claim 1, comprising: 3 and SW 4. 4. The call expected sequence number generation circuit 5 generates counters ESQ-0 to ESQ-N which are provided corresponding to the sequence number and number of the call and are simultaneously counted up by the pulse generation circuit 4, and the counter ESQ-N. A switch SW2 for switching between 0 and ESQ-N, and a control logic circuit 2 for controlling the switch SW2 in accordance with the sequence number of the call.
1. A packet switching device according to any one of claims 1 to 3, comprising: 5. The call expected sequence number generation circuit 5 includes a common counter 41 counted up by the pulse generation circuit 4, an offset table 42 storing offset numbers corresponding to the sequence number of the call, and the common counter 41. 4. The packet switching equipment according to claim 1, further comprising an adder 43 for generating an expected sequence number of the call by adding the counter and the offset number. 6. The call expected sequence number generation circuit 5 includes an adder 44 that adds 1 to the offset value of the offset table 42, and the control circuit 6 includes:
When the difference between the sequence numbers is other than -1, 0, or +1, the table 4 is added by the output of the adder 44.
6. The packet switching equipment according to claim 5, wherein the packet switching equipment is controlled so as to rewrite the data.