JPH0437147A - Mounting of semiconductor chip - Google Patents

Mounting of semiconductor chip

Info

Publication number
JPH0437147A
JPH0437147A JP2141595A JP14159590A JPH0437147A JP H0437147 A JPH0437147 A JP H0437147A JP 2141595 A JP2141595 A JP 2141595A JP 14159590 A JP14159590 A JP 14159590A JP H0437147 A JPH0437147 A JP H0437147A
Authority
JP
Japan
Prior art keywords
semiconductor chip
conductive
electrode pad
electrode
conductive resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2141595A
Other languages
Japanese (ja)
Inventor
Koichi Murakoshi
村越 孝一
Takashi Kanamori
孝史 金森
Yoshinori Arao
荒尾 義範
Wataru Takahashi
渉 高橋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP2141595A priority Critical patent/JPH0437147A/en
Publication of JPH0437147A publication Critical patent/JPH0437147A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/321Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives

Abstract

PURPOSE:To certainly realize connection between a glass substrate and a semiconductor chip without conducting high temperature heat treatment by supplying photo-setting conductive type resin to an electrode pad on which a recessed area is formed, placing conductive balls thereon, stacking electrodes of a semiconductor chip of such conductive balls and executing the positioning by moving the conductive balls. CONSTITUTION:A recessed area 12a is formed on an electrode 12 of a semiconductor chip 11, an upper layer 15 is formed on a wiring 16 of a glass substrate, the wiring 16 is exposed by selectively removing the upper layer 15 and an electrode pad 20 forming the recessed area is provided, photo-setting conductive resin 14 is supplied to the electrode pad 20, conductive balls 13 are placed on the photo-setting conductive resin 14 and the electrode 12 of semiconductor chip 11 is stacked on the conductive balls 13 through face-down of the semiconductor chip 11. The conductive balls 13 are rotated and moved within the electrode pad 20 to paste the entire part of the conductive balls 13 with the photo-setting conductive resin 14 and conduct the positioning. After the positioning, a load is applied from the upper direction of semiconductor chip 11 for standstill. The electrode pad 20 is irradiated with the light 19. Thereby the photo-setting conductive resin 14 is hardened to establish electrical connection.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は、半導体チップをガラス基板上に半導体チップ
のバンプレスで、フェースダウンボンディングする半導
体チップの実装方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for mounting a semiconductor chip on a glass substrate by face-down bonding without bumping the semiconductor chip.

(従来の技術) 従来、このような分野の技術としては、例えば特開昭5
9−195837号、特開昭61−94330号に記載
されるものがあった。
(Prior art) Conventionally, as a technology in this field, for example, Japanese Patent Application Laid-open No. 5
There were those described in No. 9-195837 and JP-A-61-94330.

第3図はかかる従来のガラス基板における半導体チップ
のフェースダウンボンディング実装例を示す、つまり、
第3図(a)は半田バンプ接続方式、第3図(b)は金
バンブ接続方式、第3図(c)は金バンプ(又は半田バ
ンプ)を熱硬化型導電性樹脂で接続する方式である。
FIG. 3 shows an example of face-down bonding mounting of a semiconductor chip on such a conventional glass substrate, that is,
Figure 3 (a) shows a solder bump connection method, Figure 3 (b) a gold bump connection method, and Figure 3 (c) a method in which gold bumps (or solder bumps) are connected with thermosetting conductive resin. be.

次に、以下各接続方式を第3図(a)〜(c)を参照し
ながら説明する。
Next, each connection method will be explained below with reference to FIGS. 3(a) to 3(c).

まず、第3図(a)に示すように、半田バンブ接続方式
は、半導体チップ1の電極に形成した半田(Pb−Sn
)バンブ2を、ガラス基板9に形成した金属膜6上の半
田ダム8付きの半田濡れ性の良い金属膜5にフラックス
等で仮止めした後、赤外線リフローやホットプレートに
より180〜350℃程度の高温で半田を溶融させて接
続させる。
First, as shown in FIG. 3(a), the solder bump connection method uses solder (Pb-Sn) formed on the electrodes of the semiconductor chip 1.
) After temporarily fixing the bump 2 to a metal film 5 with good solder wettability with a solder dam 8 on a metal film 6 formed on a glass substrate 9 using flux, etc., heat the bump 2 to a temperature of about 180 to 350°C using infrared reflow or a hot plate. The solder is melted and connected at high temperatures.

第3図(b)に示す金バンブ接続方式は、半導体チップ
1の電極に形成した金バンブ3をガラス基板9の配線の
金属膜6の上にSnメツキ膜7に位置合わせして載せた
後、450°C程度の高温で該金バンブ3とSnメツキ
膜7をAu−3nn共晶台により接続させる。
In the gold bump connection method shown in FIG. 3(b), the gold bumps 3 formed on the electrodes of the semiconductor chip 1 are placed on the metal film 6 of the wiring of the glass substrate 9 in alignment with the Sn plating film 7. The gold bump 3 and the Sn plating film 7 are connected by an Au-3nn eutectic stand at a high temperature of about 450°C.

第3図(c)に示す金バンブ(又は半田バンブ)を熱硬
化型の導電性樹脂で接続させる方式は、ガラス基板9の
配線6に熱硬化型の導電性樹脂4をデイスペンサ法やス
クリーン印刷法により選択的に供給し、半導体チップ1
の金バンブ(あるいは半田バンブ)3をそこへ押さえつ
け、150℃程度の温度で前記導電性樹脂を硬化させて
接続させるという方法をとっていた。
The method of connecting the gold bumps (or solder bumps) shown in FIG. 3(c) with a thermosetting conductive resin is to apply the thermosetting conductive resin 4 to the wiring 6 of the glass substrate 9 using the dispenser method or screen printing. The semiconductor chip 1 is selectively supplied by the method.
A method was used in which a gold bump (or solder bump) 3 was pressed thereon, and the conductive resin was cured at a temperature of about 150° C. to make the connection.

(発明が解決しようとする課R) しかしながら、以上述べた半導体チップの実装方法では
、 (1)バンブ形状のバラツキの影響により断線等の接続
不良が生じあい。
(Problem R to be solved by the invention) However, in the semiconductor chip mounting method described above, (1) connection failures such as disconnections occur due to the influence of variations in bump shapes;

(2)半田バンブによるフェースダウンボンディング法
では、半田を溶融して接続をとるため、半田濡れ性の悪
い基板上の電極パッドにはボンディングできない、また
、半田付は可能な電極パッドに対しては、180〜35
0℃程度の高温に加熱する必要がある。
(2) In the face-down bonding method using solder bumps, since the solder is melted to make the connection, it cannot be bonded to electrode pads on a board with poor solder wettability, and it cannot be bonded to electrode pads that can be soldered. , 180-35
It is necessary to heat it to a high temperature of about 0°C.

(3)金バンブによるフェースダウンボンディング方法
では、金を共晶させて接続をとるため、基板上の電極バ
ンドには、Snメツキしなければならない、また、Au
−3n共晶を行うために、450°C程度の高温加熱が
必要である。
(3) In the face-down bonding method using gold bumps, the connection is made by eutectic gold, so the electrode band on the substrate must be plated with Sn.
In order to perform -3n eutectic, high temperature heating of about 450°C is required.

(4)半田バンブ法や金バンブ法を用いてボンディング
する場合、かならず加熱を必要とするため、製造中に基
板の配線が熱ストレスを受け、断線を生じ易くなる。
(4) When bonding is performed using the solder bump method or the gold bump method, heating is always required, so that the wiring on the board is subjected to thermal stress during manufacturing, making it easy to cause disconnection.

(5)バンブ数、即ち、接続端子数が多く、しかも端子
間間隔が狭い高密度な半導体チップでは、良好なボンデ
ィングの位置合わせ精度を得ることが困難である。
(5) In a high-density semiconductor chip with a large number of bumps, that is, a large number of connection terminals, and narrow intervals between the terminals, it is difficult to obtain good bonding alignment accuracy.

(6)半導体チップの製造において、バンブを形成する
ことが難しく、しかも工数が増加する。
(6) In manufacturing semiconductor chips, it is difficult to form bumps and the number of steps increases.

といった問題点があった。There were some problems.

本発明は、上記問題点を除去するために、バンブレスの
半導体チップを基板の電極パッドとの接続を導電性球と
光硬化型導電性樹脂を用い、該導電性球を動かして位置
合わせを行うことにより、高温加熱を行うことなく、確
実に行うことができる半導体チップの実装方法を提供す
ることを目的とする。
In order to eliminate the above-mentioned problems, the present invention connects a bumpless semiconductor chip to an electrode pad on a substrate using a conductive ball and a photocurable conductive resin, and aligns the conductive ball by moving the conductive ball. Therefore, it is an object of the present invention to provide a semiconductor chip mounting method that can be reliably carried out without high-temperature heating.

(課題を解決するための手段) 本発明は、ガラス基板上に半導体チップをフェースダウ
ンボンディングする半導体チップの実装方法において、
半導体チップの電極には窪みを形成し7、ガラス基板の
配線上には上部層を形成し、該上部層を選択的に除去し
て、前記配線を露出させ、窪みが形成された電極パッド
を設け、該電極バンドに光硬化型導電性樹脂を供給し、
該光硬化型導電性樹脂上に導電性球を置き、前記半導体
チップをフェースダウンして、前記導電性球に前記半導
体チップの電極を重ね、前記導電性球を前記電極パッド
内で回転、移動させて、前記導電性球全体を前記光硬化
型導電性樹脂で塗り潰すと共に位置合わせを行い、該位
置合わせ後、前記半導体チップ上面より荷重を加えて静
止させ、前記電極パッドに光を照射させ、前記光硬化型
導電性樹脂を硬化して電気的接続をとるようにしたもの
である。
(Means for Solving the Problems) The present invention provides a semiconductor chip mounting method for face-down bonding a semiconductor chip onto a glass substrate.
A recess is formed in the electrode of the semiconductor chip 7, an upper layer is formed on the wiring of the glass substrate, the upper layer is selectively removed to expose the wiring, and the electrode pad in which the recess is formed is formed. and supplying a photocurable conductive resin to the electrode band,
Place a conductive ball on the photocurable conductive resin, place the semiconductor chip face down, overlap the electrode of the semiconductor chip on the conductive ball, and rotate and move the conductive ball within the electrode pad. Then, the entire conductive sphere is filled with the photocurable conductive resin and aligned, and after the alignment, a load is applied from the top surface of the semiconductor chip to make it stand still, and the electrode pads are irradiated with light. , the photocurable conductive resin is cured to establish an electrical connection.

(作用) 本発明によれば、上記のしたように、半導体チップには
、窪みを有する電極を形成し、ガラス基板側には、透明
電極膜を下地として、その上に金属膜を形成し、電極パ
ッド部のみ、金属膜を取り除いて透明電極膜が露出する
ように凹形の窪みを有する電極パッドを形成し、この電
極パッド内に光硬化型導電性樹脂を供給し、更に、該電
極パッドの前記光硬化型導電性樹脂の上に5μm〜数十
μmオーダの導電性法を電極パッドに供給し、導電性法
は力を加えた時、電極パッド内を自由に回転・移動でき
るので、前記半導体チップの電極と前記基板の電極パッ
ドとにより導電性法を挟み込み、該導電性法にチップ側
から押さえて、電極パッド内で転がして微細な位置合わ
せをした後、光を基板の裏面より照射して前記光硬化型
導電性樹脂を硬化させ、ガラス基板と半導体チップとの
接続を行う、従って、高温加熱を行うことなく、ガラス
基板と半導体チップとの接続を確実に行うことができる
(Function) According to the present invention, as described above, an electrode having a recess is formed on the semiconductor chip, and a metal film is formed on the transparent electrode film as a base on the glass substrate side, For only the electrode pad portion, the metal film is removed to form an electrode pad having a concave recess so that the transparent electrode film is exposed, a photocurable conductive resin is supplied into this electrode pad, and further, the electrode pad is A conductive layer on the order of 5 μm to several tens of μm is applied to the electrode pad on the photocurable conductive resin, and the conductive layer can freely rotate and move within the electrode pad when force is applied. A conductive pad is sandwiched between the electrode of the semiconductor chip and the electrode pad of the substrate, and the conductive pad is pressed from the chip side and rolled within the electrode pad for fine alignment, and then light is emitted from the back side of the substrate. The photocurable conductive resin is cured by irradiation, and the glass substrate and the semiconductor chip are connected. Therefore, the glass substrate and the semiconductor chip can be reliably connected without performing high-temperature heating.

(実施例) 以下、本発明の実施例について図面を参照しながら詳細
に説明する。
(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

第1図は本発明の実施例を示すガラス基板上への半導体
チップの実装工程断面図、第2図はその要部を示す拡大
断面図である。
FIG. 1 is a cross-sectional view of a mounting process of a semiconductor chip on a glass substrate showing an embodiment of the present invention, and FIG. 2 is an enlarged cross-sectional view showing the main parts thereof.

まず、第1図(a)に示すように、ガラス基板17上に
配線パターンとして透明電極膜16、例えばITO膜や
ネサ膜等を蒸着法により形成し、その上に配線抵抗を下
げるために蒸着法又は厚膜印刷法により1層以上の金属
膜15、例えばCu−Cr。
First, as shown in FIG. 1(a), a transparent electrode film 16, such as an ITO film or a NESA film, is formed as a wiring pattern on a glass substrate 17 by vapor deposition. one or more metal films 15, for example Cu-Cr, by a method or a thick film printing method.

Au−Cr等を形成する。なお、ガラス基板17上の電
極パッド20は金属膜15を除去して凹形の窪みにする
Au-Cr etc. are formed. Note that the metal film 15 of the electrode pad 20 on the glass substrate 17 is removed to form a concave depression.

次に、第1図(b)に示すように、光硬化型導電性樹脂
14を粘度を調整しながら、デイスペンサ法やスクリー
ン印刷法により選択的に、前記凹形の窪みが形成された
電極パッド20に供給する。
Next, as shown in FIG. 1(b), while adjusting the viscosity of the photocurable conductive resin 14, the electrode pads in which the concave recesses are formed are selectively applied using a dispenser method or a screen printing method. Supply 20.

更に、前記光硬化型導電性樹脂14を供給した電極パッ
ド20に、電極パッド1個につき1個の導電性法13〔
一般には球状にしたNi、半田、Pb等金属ボールを使
うが、他にポリエチレン(PE)やポリメタクリル酸メ
チル(=PMMA)などのプラスチックにAuやNiメ
ツキを施したボール等を用いる〕を置く。該導電性法1
3は5μm〜数十μmと半導体チップの電極サイズ、あ
るいは電極ピッチにより最適なサイズのものを選ぶもの
とする。
Furthermore, one conductive layer 13 per electrode pad is applied to the electrode pad 20 to which the photocurable conductive resin 14 has been supplied.
Generally, spherical metal balls such as Ni, solder, or Pb are used, but balls made of plastic such as polyethylene (PE) or polymethyl methacrylate (=PMMA) plated with Au or Ni are also used. . The conductivity method 1
3 is selected from an optimal size of 5 μm to several tens of μm depending on the electrode size of the semiconductor chip or the electrode pitch.

なお、上記導電性法は、電極パッド1個につき1個設け
るように説明したが、位置合わせに支障を生じなければ
、複数個配置するようにしてもよい。
Note that in the above conductive method, one electrode pad is provided for each electrode pad, but a plurality of electrode pads may be provided as long as it does not cause any trouble in alignment.

一方、半導体チップ11の電極12については第2図を
基に詳細に説明する。
On the other hand, the electrodes 12 of the semiconductor chip 11 will be explained in detail based on FIG. 2.

第2図(a)に示すように、電極12は、半導体チップ
11の回路中に蒸着法又はメツキ法により形成した金属
電極であり、半球状の富み12aが形成されている。こ
れは、通常バンプ製造工程の中のエツチング工程におい
て、アンダーエツチング法により形成することができる
。この電極12を形成してフェースダウンさせる。
As shown in FIG. 2(a), the electrode 12 is a metal electrode formed in the circuit of the semiconductor chip 11 by a vapor deposition method or a plating method, and has a hemispherical recess 12a. This can be formed by under-etching in the etching process of the normal bump manufacturing process. This electrode 12 is formed and made face down.

以上により、ガラス基板17−導電性法13−半導体チ
ツブ11を重ね合わせ、ガラス基板17の電極パッド2
0と半導体チップ11の位置を導電性法13を用いて凹
形の窪みが形成された電極パッド20の中を導電性法1
3を回転・移動させながら行い、この際、導電性球13
全体に光硬化型導電性tMIiiが塗られるようにする
0位置決め終了後、加圧しながら基板の裏面より、光1
9、例えば紫外線を照射させて(側面からの照射も併用
可能である)、第1図(b)に示すように、光硬化型導
電性樹脂14を硬化させ、導電性法13並びに半導体チ
ップ11を固定し、基板との接続を行うようにした。
As described above, the glass substrate 17 - conductive method 13 - semiconductor chip 11 are superimposed, and the electrode pads 2 of the glass substrate 17 are stacked together.
0 and the semiconductor chip 11 using the conductive method 13 to conduct the inside of the electrode pad 20 in which a concave depression is formed.
3 while rotating and moving the conductive ball 13.
After completing the 0 positioning so that the entire surface is coated with photocurable conductive tMIii, light 1 is applied from the back side of the board while applying pressure.
9. For example, by irradiating ultraviolet rays (irradiation from the side can also be used), the photocurable conductive resin 14 is cured, as shown in FIG. was fixed and connected to the board.

第4図は本発明の他の実施例を示すガラス基板上への半
導体チップの実装要部断面図である。
FIG. 4 is a sectional view of the main part of mounting a semiconductor chip on a glass substrate, showing another embodiment of the present invention.

この実施例においては、凹形の窪み18aが形成された
電極18を有する半導体チップ11を前記したと同様に
フェースダウンさせる。
In this embodiment, the semiconductor chip 11 having the electrode 18 in which the concave depression 18a is formed is face-down in the same manner as described above.

なお、最後に導電性法に光硬化型導電性樹脂がうまく塗
られなかったために、導電性法と半導体チップの接続不
良箇所が生じることもあり、これをなくすためには、実
装後は全体を絶縁樹脂で封止して半導体チップを固定す
るようにすることが望ましい。
Furthermore, because the photocurable conductive resin was not applied properly to the conductive method at the end, poor connection between the conductive method and the semiconductor chip may occur. It is desirable to fix the semiconductor chip by sealing it with an insulating resin.

また、本発明は上記実施例に限定されるものではなく、
本発明の趣旨に基づいて種々の変形が可能であり、これ
らを本発明の範囲から排除するものではない。
Furthermore, the present invention is not limited to the above embodiments,
Various modifications are possible based on the spirit of the present invention, and these are not excluded from the scope of the present invention.

(発明の効果) 以上、詳細に説明したように、本発明によれば、ガラス
基板の電極パッドと半導体チップの接続に、導電性球と
光硬化型導電性樹脂を用いたので、バンブ接続の半導体
チップの電極形成工程が少なくなり、接続高さのバラツ
キを樹脂で調整できるので、接続不良がな(なり、しか
も、接続時に加熱の必要性がないため、熱ストレスによ
る断線がなくなる。
(Effects of the Invention) As described above in detail, according to the present invention, a conductive ball and a photocurable conductive resin are used to connect an electrode pad on a glass substrate and a semiconductor chip, so bump connection is possible. The number of electrode formation steps for semiconductor chips is reduced, and variations in connection height can be adjusted using resin, so there are no connection failures.Furthermore, since there is no need for heating during connection, there is no disconnection due to thermal stress.

更に、半導体チップの電極と基板の電極パッドに窪みを
設けて、導電性球を窪み内で自由に動かせるようにした
ことにより、位置合わせを容易に行うことができる。
Further, by providing depressions in the electrodes of the semiconductor chip and the electrode pads of the substrate, and allowing the conductive sphere to move freely within the depressions, alignment can be easily performed.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の実施例を示すガラス基板上への半導体
チップの実装工程断面図、第2図はその要部を示す拡大
断面図、第3図は従来のガラス基板における半導体チッ
プのフェースダウンボンディング実装例を示す図、第4
図は本発明の他の実施例を示すガラス基板上への半導体
チップの実装要部断面図である。 11・・・半導体チップ、12.18・・・半導体チッ
プの電極、12a・・・半球状の窪み、13・・・導電
性球、14・・・光硬化型導電性樹脂、15・・・金属
膜、16・・・透明電極膜、17・・・ガラス基板、1
8a−・・凹形の窪み、19・・・光(紫外線)、20
・・・電極パッド。 特許出願人 沖電気工業株式会社 代理人 弁理士  清 水  守(外1名)第1図 Φ)采のη°う顯1:お1フる手埒μ本チヮフ゛め災牽
(例もふ肯図第3図
Fig. 1 is a sectional view of the mounting process of a semiconductor chip on a glass substrate showing an embodiment of the present invention, Fig. 2 is an enlarged sectional view showing the main parts thereof, and Fig. 3 is a face of a semiconductor chip on a conventional glass substrate. Diagram showing an example of down bonding implementation, No. 4
The figure is a sectional view of the main part of mounting a semiconductor chip on a glass substrate, showing another embodiment of the present invention. DESCRIPTION OF SYMBOLS 11... Semiconductor chip, 12.18... Electrode of semiconductor chip, 12a... Hemispherical depression, 13... Conductive sphere, 14... Photocurable conductive resin, 15... Metal film, 16... Transparent electrode film, 17... Glass substrate, 1
8a--Concave depression, 19--Light (ultraviolet), 20
...Electrode pad. Patent Applicant Oki Electric Industry Co., Ltd. Agent Patent Attorney Mamoru Shimizu (1 other person) Figure 3

Claims (1)

【特許請求の範囲】  ガラス基板上に半導体チップをフェースダウンボンデ
ィングする半導体チップの実装方法において、 (a)半導体チップの電極には窪みを形成し、(b)ガ
ラス基板の配線上には上部層を形成し、(c)該上部層
を選択的に除去して、前記配線を露出させ、窪みが形成
された電極パッドを設け、(d)該電極パッドに光硬化
型導電性樹脂を供給し、(e)該光硬化型導電性樹脂上
に導電性球を置き、(f)前記半導体チップをフェース
ダウンして、前記導電性球に前記半導体チップの電極を
重ね、前記導電性球を前記電極パッド内で回転、移動さ
せて、前記導電性球全体を前記光硬化型導電性樹脂で塗
り潰すと共に位置合わせを行い、 (g)該位置合わせ後、前記半導体チップ上面より荷重
を加えて静止させ、前記電極パッドに光を照射させ、前
記光硬化型導電性樹脂を硬化して電気的接続をとること
を特徴とする半導体チップの実装方法。
[Claims] In a semiconductor chip mounting method in which a semiconductor chip is face-down bonded onto a glass substrate, (a) a recess is formed in the electrode of the semiconductor chip, and (b) an upper layer is formed on the wiring of the glass substrate. (c) selectively removing the upper layer to expose the wiring and providing an electrode pad with a recess formed therein; (d) supplying a photocurable conductive resin to the electrode pad; , (e) place a conductive ball on the photocurable conductive resin, (f) place the semiconductor chip face down, overlap the electrodes of the semiconductor chip on the conductive ball, and place the conductive ball on the conductive resin. Rotate and move within the electrode pad to fill the entire conductive sphere with the photocurable conductive resin and align the conductive sphere; (g) After the alignment, apply a load from the top surface of the semiconductor chip to make it stand still; A method for mounting a semiconductor chip, comprising: irradiating the electrode pad with light to cure the photocurable conductive resin to establish an electrical connection.
JP2141595A 1990-06-01 1990-06-01 Mounting of semiconductor chip Pending JPH0437147A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2141595A JPH0437147A (en) 1990-06-01 1990-06-01 Mounting of semiconductor chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2141595A JPH0437147A (en) 1990-06-01 1990-06-01 Mounting of semiconductor chip

Publications (1)

Publication Number Publication Date
JPH0437147A true JPH0437147A (en) 1992-02-07

Family

ID=15295664

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2141595A Pending JPH0437147A (en) 1990-06-01 1990-06-01 Mounting of semiconductor chip

Country Status (1)

Country Link
JP (1) JPH0437147A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7968801B2 (en) 2005-07-28 2011-06-28 Sharp Kabushiki Kaisha Solder mounting structure, method for manufacturing such solder mounting structure and use of such solder mounting structure

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7968801B2 (en) 2005-07-28 2011-06-28 Sharp Kabushiki Kaisha Solder mounting structure, method for manufacturing such solder mounting structure and use of such solder mounting structure

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