JPH05206379A - Multichip module and its manufacture - Google Patents

Abstract

PURPOSE: To mount and connect chips of different structures on a carrier substrate by forming an electrical connection pad and a carrier with projections. CONSTITUTION: A substrate 23 has connection pads 21 and 13. The pad 13 is used for accepting a solder ball 11, and the pad 21 accepts a solder coating. A bump 11 is made of an epoxy material and puts a projection on the pads 13 and 21 to connect a solder bump 17 to the carrier 23. Any connection can be mounted between the input/output terminals of chips 3 and 15 for providing proper electrical and mechanical characteristics, such as thermo-compression. The substrate 23 having a via aligned with a pin 27 integrates a dual-in-line package. A passive component 40, such as a resistor, is installed on the substrate 23 by a pad 44 and a projection 42.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates generally to a method of joining modules by bonding each integrated circuit device (chip) having differently formed input / output interconnects to a common carrier. .. More specifically, by providing protrusions such as solder bumps on the carrier,
Allow each chip to be bonded to the carrier at each connection pad.

[0002]

BACKGROUND OF THE INVENTION Bonding each semiconductor chip to a substrate requires a different interconnection method to manufacture a multi-chip module (MCM). It has not been performed satisfactorily due to the added complexity of using different interconnect technologies, including processes with considerable differences, to connect the chips of the. Furthermore, combining chips with differently formed interconnects on the same carrier is not common because of the high cost of manufacturing processes. For example, assembly techniques on such modules include several steps in addition to those required to mount other chips that cannot use wire bonding, such as those that require flip-chip bonding. Wire bonding must be used to bond the chip to the substrate.

The use of complex interconnect technology for MCM manufacturing not only complicates the manufacturing process, but also complicates rework of the completed module, which requires a separate removal process for each interconnect technology. ..

Multi-chip modules are needed in computers with a growing number of electronic characteristics that require packaging density and high performance. Therefore,
In order to achieve the desired properties, it has become necessary to use a wide range of chips with different functions on one substrate.

At IBM Corporation, "Controll
ed Collapse Chip Connect; has been used for many years called C4 "technology. This C4 technology is used to bond a computer chip such as a memory or logic chip to a carrier substrate. Solder balls attached to the chip Is used to interconnect the I / O portion of the chip to the substrate, which has corresponding interconnect pads, the C4 chip is aligned on the substrate, and the solder balls are reflowed. To make electrical connection.
The solder used to form the 4 solder balls is generally a mixture of 90-97% lead and 10-3% tin. This solder has a melting point of approximately 360 ° C., limiting the choice of carrier material and metallization. In general, ceramics have been used for carriers, and sometimes a combination of high temperature polymers and various metals is used for specific MCM manufacturing applications.
Furthermore, it is desirable to have a wide range of materials that can be selected as carriers to meet cost or performance requirements for functionality. Therefore, it would be desirable to be able to use interconnect technologies that allow low temperature processes and material systems compatible with these low temperature processes. The most common low temperature materials are
It contains glass epoxy and a low temperature polymer combined with various metals. To make a cold assembly, cold solder is deposited on the substrate pads and then C4 bumps are soldered to the carrier. This technique has been successfully used to solder multiple C4 chips to a carrier to produce a multi-chip module.

Conversely, chip manufacturers other than IBM do not use C4 technology to a large extent, and as a result, a significant number of non-C4 chips are commercially available. Generally, these non-C4 chips are connected to lead frames, which are used on single chip modules using wire bonding technology. Direct bonding of this type of chip to the carrier has been done by wire bonding the chip pad to a so-called hybrid module, forming the MCM type.

In addition, the chip is bonded to the carrier material using an epoxy filled conductor. This method has achieved high results in the development of liquid crystal displays,
In a liquid crystal display, the pads of each line driving chip are attached to a glass plate containing metal lines connected to the liquid crystal display. This type of display is also in the form of an MCM. The chip also uses TAB (Tape Automated Bondin) that utilizes various interconnect technologies.
g) is mounted on a flexible carrier. The connection from the carrier to each chip is made by bonding the lead wire to the chip using thermocompression bonding energy.

Further, US Pat. No. 3,811,186 discloses an integrated circuit chip in which the solder coated terminals of the integrated circuit chip are aligned with the engaging circuit lands on the substrate. The legs are used to align and support the integrated circuit during bonding to the substrate. U.S. Pat. No. 4,179,802 discloses plating a plurality of metal studs on a chip carrier in a pattern that engages chips that are bonded to the carrier.

It is desirable to have the ability to use any of these chips that use a combination of different connection technologies on a single module. It is also desirable to be able to mix chips made of different materials such as silicon and gallium arsenide on a single module. Hardware designers can have a great deal of flexibility in component selection during functional design and can produce a wide range of differently formed functional modules. These different MCMs are referred to herein as mixed multi-chip modules. However, a number of separate bonding processes must be used to make these mixed multi-chip modules without the benefits of the present invention.

A plurality of chips having only pads, C4
It is easy to see how manufacturing these mixed MCMs using a single process of the same technology to mount other chips with bumps on a substrate carrier can have a cost impact. If it is not necessary from the standpoint of design flexibility, a chip having a certain function that can be obtained only by a specific interconnect structure is replaced by an M having another interconnect structure.
It is also required to have the ability to be used on CMs. In addition, the ability to use chips with special I / O interconnections on each multichip module,
It is advantageous to supplement the chip production capacity. There is a need for a process that allows any combination of differently formed chips to be bonded to a substrate carrier to produce mixed multi-chip modules and support considerable flexibility for both designers and manufacturers. I understand.

[0011]

In contrast to the prior art,
The present invention provides a carrier having an electrical connection pad and a protrusion to provide a chip having an electrical connection pad, for example, a chip formed for wire bonding, and
Both other chips with C4 bumps are bonded to their respective predetermined connection points on the same substrate, thereby manufacturing the mixed multi-chip module using the same interconnection process. It should be understood that these chips can be manufactured quite differently, for example chips made of silicon and gallium arsenide.
In addition, a single process can be used to mount passive components such as resistors, capacitors and packaged devices on the same substrate.

The electrical connection pads of the substrate can be made by using known techniques such as etching, electrodeposition and the like. The pads are placed on the substrate, and their positions are aligned in correspondence with the input / output terminal positions of the chips to be joined face down on the substrate. The pads are formed at positions corresponding to the input / output terminals of each chip regardless of the chip type, that is, the C4 chip or the pad connection chip. Any electrical interconnect protrusion, such as soldering, conductive epoxy, etc., can be used on the carrier. Here, solder bumps are used. The solder bumps are mounted on the pads, the position of which corresponds to the position of each input / output terminal of the chip used for input / output interconnection. Solder bumps are used for vapor deposition, sputtering,
It can be formed on the pad by various methods such as plating, electrodeposition and the like. Therefore, a substrate carrier having a chip having C4 bumps and a chip having an electric connection pad instead of the C4 bump, that is, a projection having an electric connection for engaging with a chip having no bump as an input / output terminal is formed. .. The pads with the electrical protrusions (on the substrate) are opposed to each other in relation to the C4 solder bumps on the chip that are bonded to the carrier and the connection pads on the non-C4 type chip that are bonded to different locations on the carrier. Aligned. The chip is heated to a temperature at which the solder bumps on the substrate reflow and is bonded to the carrier.

C4 on a carrier with signal lines and reference lines (extremely thin, eg 5.08 × 10 ⁻³ cm or less) that can interconnect closely packaged chips.
Mounting the chips face down (the protrusions connect to the carrier), as used in the technology, produces an electronic package with extremely high packing density. When mounting the chip on the carrier, most of the wiring will be underneath the chip with small additional areas required for wiring fanout, as is the case with packaged devices, TAB technology, or wire bonded devices. Since they can be stored, the chips can be placed on the carrier in close proximity to each other. If all chips are mounted face down on the carrier with fine wiring capability, as in the case of C4 technology, a very dense packaging multi-chip module can be achieved regardless of the interconnection technology. So-called mixed modules, all using face-down chips, as described above, are more effective than other mixed modules in which mixed chips are joined using wire bonding, TAB connections, packaged devices or a combination of these packaging techniques. Package density can be achieved. All chips are C4 by using independent interconnection technology
The same chip densities can be achieved as when bonded using technology.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENT In FIG. 1, a chip mounting means including a vacuum operating chuck 1 is shown as having an integrated circuit device, the chuck 1 having a chip 3 attached thereto. The chip 3 comprises each input / output connection pad 5 made using any one of many conductive materials. A carrier 9 is shown in FIG. 1, which comprises electrical connection pads 13 and electrical interconnection projections 11. If the electrical interconnection projections 11 are made of solder,
The chip metallization (pad 5) must be solderable. In this case, each pad 5 of the chip
The top layer of the top metallization can be, for example, chrome-copper-gold. If the protrusions 11 are gold bumps or conductive adhesives, standard process aluminum chip pads 5 are sufficient. Chips 3 of this type of structure (chrome-copper-gold and aluminum)
Is quite common in the computer manufacturing industry.
The connection pad 5 is formed by a normal method such as electrodeposition.
It is formed on the chip 3 when the chip 3 is manufactured. The carrier 9 is made of an insulating substrate made of epoxy glass, ceramic, polyimide or the like, and is shown to have input / output electrical interconnection points (pads 13 and protrusions 11) formed similarly to the connection pads 5 of the chip 3. Has been done. The interconnection points of the carrier 9 comprise connection pads 13 made of a conductive material such as copper. The protrusions 11, such as solder balls or bumps of other material, are
It is placed in close contact with No. 3 and is joined by a usual method.
The split prism 7, which is the position matching means,
Between the carrier and the carrier 9 is shown, and by simultaneously viewing the pad and the solder ball through the split prism 7, the pad 5 is accurately aligned with the solder ball 11 on the carrier 9. After aligning the chip 3, the split prism 7 is removed, and the vacuum chuck 1 is lowered until the pad 5 and the solder ball 11 come into contact with each other. Flux can be used to hold the chips in place until the solder bumps 11 are reflowed and the chips 3 are electrically and mechanically bonded to the substrate 9. When the chuck 1 is separated from the chip 3, the chip 3 remains bonded to the carrier 9 by the solder balls 11. This alignment method is commonly used in the industrial field.

FIG. 2 shows the same alignment as in FIG. 1 but holding the chip 15 on the chuck 1 under vacuum pressure. The chip 15 is manufactured using the C4 technology described above, and has a plurality of solder balls 17 bonded to the connection points on the lower surface of the chip 15, which solder balls 17 constitute each input / output interconnection point of the chip. .. A carrier 19 which is an insulating substrate similar to the carrier 9 of FIG. 1 is shown in FIG. Connection pads 21 are formed on the surface of the carrier 19 for interconnecting various signals and reference planes contained in the carrier 19. A prism 7 for aligning the solder balls 17 and the connection pads 21 is shown in FIG. 2 arranged between the chip 15 and the carrier 19. After aligning the chip 15 and the carrier 19, the prism 7 is removed and the chip 1
5 is lowered until the solder ball 17 and the connection pad 21 are aligned and in contact. When the adsorption of the chuck 1 is released, the chips 15 remain arranged on the carrier 19 by the action of the flux, as described in FIG.
To bond the chip 15 to the carrier 19, the pads 21 on the carrier 19 are coated with a bonding metal 22, typically eutectic solder consisting of 63% lead and 37% tin. When the low temperature solder 22 (183 ° C.) reflows, the C4 solder balls 17 are soldered to the carrier pads 21. If the carrier 19 can withstand the high temperatures required to reflow each C4 pad, each C4 ball can be reflowed as opposed to using a low temperature solder coating 22.

FIG. 3A shows a plurality of C4 solder balls 1.
Shown is a chip 15 with a C4 solder ball 17 in contact with a connection pad 21, typically coated with eutectic solder 22, on a carrier 19. Further, FIG. 3B shows a state in which the surface eutectic solder 22 is reflowed and the chip 15 is bonded to the carrier 19, and the solder pillar 18 serves as a signal and reference plane of the chip 15 and the carrier 19. An electrical connection is made between them (via each pad 21). The shapes described in FIGS. 3 (a) and 3 (b), that is, the C4 type chips 15 placed on the carrier 19, form "standard" IBM type chip type interconnections. In a standard C4 module using a ceramic substrate, the C4 ball is reflowed at a considerably high temperature (about 360 ° C.), and the solder pillar 18 formed by this reflow heats the silicon chip 15 and the ceramic substrate 19 together. It has a function of absorbing the stress between the chip 15 and the carrier 19 caused by the difference in expansion coefficient. The C4 technology can be used to form high quality joints and does not require encapsulation of the solder pillars 18, which requires encapsulation materials and the like. However, as described with reference to FIGS. 3 (a) and 3 (b), if the low temperature soldering technique is used, in the case of the chip bonded on the epoxy glass card, the stress applied to the solder pillar 18 is absorbed, It is necessary to encapsulate the chip around the solder posts 18 with a suitable epoxy. The preferred embodiments of the present invention use low temperature soldering techniques because of the desire to use a variety of substrates, and these embodiments require chip encapsulation.

FIG. 4A shows a chip 3 which contacts the carrier 9, and a solder ball 11 is arranged between the chip 3 and the carrier 9. In FIG. 4 (b),
Chip 3 and carrier 9 after reflow of solder balls 11
And the solder pillars 20 are formed by reflowing the solder balls 11, and the input / output connection pads 5 of the chip 3 and the input / output connection pads 13 of the carrier 9 are connected.

As shown above, a chip 15 having a solder ball formed on the surface by using the C4 technique.
Can be bonded to the connection pad 21, or to the carrier 19 with only the connection pad 21 on which the low temperature solder 22 is formed. Further, the chip 3 having the connection pad 5 formed on the surface as an input / output connection point can be bonded to the carrier 9 having the solder ball 11 and the connection pad 13 provided on the surface. Therefore, two different types of connection structures use similar processing steps,
It can be used to assemble mixed multi-chip modules.

The embodiment of the invention illustrated in FIGS. 4 (a) and 4 (b) comprises a bump 11 of any of the types described above, which is mounted on the pad 13 of the carrier 9. As described above, the chip pad 5 and the carrier pad 13 are formed so that the chip 3 can be bonded onto the carrier 9.
It must be made of a metal compatible with the bump 11.
The chips 3 are placed on the carrier 9 and the solder balls 11 are reflowed (or the epoxy is hardened by heating, if this connection method was used). The solder posts 20 are formed after the reflow of the protrusions 11, and the same considerations as described above with respect to the solder posts 18 (FIG. 3 (b)) apply to the solder posts 20. That is, if the low temperature solder (eutectic) balls 11 are used on a carrier having a relatively high coefficient of thermal expansion, encapsulation of the solder posts 20 is required.

Considering FIG. 5, a chip 15 according to C4 technology or a chip 3 according to another technology can be connected to a single substrate carrier 23 using the same technology and thus each with different interconnection structures. It can be seen that it provides a means of manufacturing an MCM to which chips can be bonded.

No particular type of chip can be used exclusively in today's competitive computer manufacturing industry. For example, as mentioned above, IBM Corporation manufactures memory and logic chips using C4 solder ball technology for use in manufacturing IBM computer products. However, due to fluctuations in chip supply and market demand, we have systems and methods for making mixed multi-chip modules by combining chips from other manufacturers as well as chips from C4 technology on a single carrier. Is required. Therefore, the invention shown in FIG. 5 provides for bonding C4 type chips and other differently structured chips to a single carrier substrate manufactured using known techniques and methods. of course,
The carrier is a wiring capability that allows "wiring esccape" from the pattern of the chip pad, that is, from the pad of the chip through the wire leads in the carrier to the pad on the carrier and other desired interconnection points (signals). And / or reference plane, pads associated with other chips, etc.). This step, including pad pattern escape, is typically included in today's MCM manufacturing processes.

Referring to FIG. 5, the substrate 23 is illustrated as having connection pads 21, 13 on its surface. Pad 21 and pad 13 are structurally identical to each other, but differ in that pad 13 is used to receive solder ball 11, and pad 21 can receive solder coating 22. Thus, each pad 13, 21 can be constructed of a conductive material compatible with the solder used in the solder bump 11 or coating 22. The solder bumps 11 are provided on the carrier 23 by various known techniques such as vapor deposition, sputtering, plating, electrodeposition and the like. Any solder material compatible with the material of the carrier connection pads 13 or 21 can be used for the bumps 11, but the preferred embodiment is a low temperature process, so the preferred embodiment is 63% lead and 37 tin. Eutectic low temperature solder consisting of 10% is generally used. Polyimide metallized with copper,
Either a high density carrier (HDC) (as is common in the manufacturing industry) or a carrier system such as a surface laminate carrier (SLC), suitable for the bumps 11 and coatings 22. Can be used with solder material. further,
It is the intention of the present invention to make the bumps 11 of a conductive epoxy material. The use of an epoxy material for the bumps 11 requires the placement of protrusions on the pads 13, 21 in order to bond the pads 5 (of the chip 3) or the solder bumps 17 (of the chip 15) to the carrier 23.
The additional method of providing the conductive epoxy bumps on the carrier 23 requires the use of an applicator or the like.

The connection pad 5 of the chip 3 is the bump 1 if
If conductive epoxy is used in # 1, it must contain a metal compatible with the use of conductive epoxy bumps. Furthermore, if solder is used for the bumps 11, the chip connection pads 5 must be solderable.
The use of other materials for the protrusion 11 is also contemplated by the present invention. The solder paste material can be used and applied in a manner similar to that used for conductive epoxies. Gold bumps,
It can also be formed and used by vapor deposition techniques, and the chips are then mounted on a carrier by thermocompression bonding, such as is done with the TAB technique where each chip is vibrated while applying heat to form a bond. In short, any bond between the input / output terminals of the chips 3,15 and the pads 13,21 of the substrate carrier 23 that provides suitable electrical and mechanical properties is considered compatible with the present invention, and Is intended.

Also shown in FIG. 5 is a dual inline package type chip 25 having pins 27 used for input / output interconnection points. The board 23 is also pin 2
A dual in-line package with pin-in-hole connection structure with holes or vias 31 aligned with 7 is combined with the chip connection technique shown and described in FIG. Further, passive components 40, such as resistors and / or capacitors, can be mounted on substrate 23 by pads 44 and protrusions 42 using exactly the same technique. The dual in-line package may be surface mount, in which case the carrier does not require vias.

The C4 bump is a back end of the final manufacturing process or line when manufacturing a silicon chip.
Note that the line; EBOL) is placed on each chip. If necessary, the EBOL process can be omitted.
As described in (b), it can be provided on the carrier in the same process as the C4 chip or the pad input / output chip. Therefore, in combination with the use of pad I / O chip technology, the C4 type chip manufacturing process is reduced, that is, the process of providing the protrusions on the chip is eliminated.
It can have the advantage of packaging density obtained by using four chips.

The projection 11 has a protrusion, as described with reference to FIGS.
It can also be formed during the manufacture of the carrier substrate 23. For the purposes of this example, the carrier 23 has a signal single reference plane (one si
gnal-one reference plane; 1S1P) substrate. Referring to FIG. 6, a single substrate material, such as copper-invar-copper, used to control the thermal expansion of the carrier is used, which substrate material is the copper thin film layer 41 shown.
And a second copper thin film layer 43, and one invar 45 provided between the copper thin films 41 and 43. Invar is an alloy of nickel and iron and is known to have a very low coefficient of thermal expansion. Next, photosensitivity (photoimageabl
e) A layer 47 of insulating material is provided on the outer surface of the copper thin film layer 43. A mask or artwork (not shown) is placed on the photosensitive layer 47 and exposed to actinic radiation to form recesses 49 in the insulating layer 47. Then, a conductive material 51 such as copper is electrodeposited in the recess 49. Next, the connection pad 21 is formed on the conductive material 51 in the recess 49. The connection pad 21 (or C3) can be formed by repeating the same process as described above. For example, a thin layer of copper can be provided, such as by sputtering, on the outer surface of the insulating layer 47, and additional insulating material can be laminated thereover, and then exposed to actinic radiation to form the recesses, The connection pad 21 is filled in the concave portion to be formed. After forming the pad 21, the insulating thin layer is removed by cleaning or the like, and the copper thin layer is removed by a method such as instantaneous etching. FIG. 6 shows a substrate 23 having pads 21 and 13 formed thereon, and the pads 21 and 13 may be provided with solder balls 11 or solder coating 22 as shown in FIG. ..

A chip having a connection pad is used as a carrier 23.
In order to bond to, the solder balls or epoxy or the like must be provided on the connection pads 13 and 21, and this process is shown in FIG. For example, if the thin copper layer previously deposited by sputtering has not yet been removed by flash etching, it is possible to provide an additional photosensitive insulating layer on the sputtered copper outer surface and form a recess in the insulating layer through a mask. it can. These recesses can then be filled with a suitable bonding metal or solder by plating or electrodeposition techniques. The outer insulating layer can then be removed by washing and the thin copper layer can be removed by flash etching. The remaining solder bumps can be rounded as shown in FIG. 7 by heating the substrate 23 until the solder reflows, thereby creating a smooth surface. Similarly, low temperature eutectic solder coating 2
2 can be provided on the pad 21 or the pad 13 by the electrodeposition technique. Additionally, the methods described above may be used to form protrusions 11 of other interconnect material, such as by vapor deposition of gold material, or an applicator may be used to provide conductive epoxy, solder paste, or the like.

If a complete module repair is required to replace a defective chip, then only one process is required. For example, if a solder interconnect is used to make a mixed MCM, heat can be applied to the defective chip to reflow the solder connecting the chip to the carrier and remove the chip. After the solder is put on the pad and the bump is reshaped, a normal chip is placed on the pad and the chip can be connected to the pad by heating. A similar process can be developed for any of the interconnect methods described above, but only one process is required to manufacture or repair chips on mixed MCMs.

Therefore, it will be explained how chips having mixed type input / output interconnection points can be joined using a similar process to make a mixed multi-chip module with differently formed chips. Was done.

[Brief description of drawings]

FIG. 1 is a diagram illustrating one method of aligning and bonding a chip having an input / output connection pad to a carrier having a connection pad and a solder ball used for input / output interconnection.

FIG. 2 is a view showing a state in which a connection pad and a solder protrusion are provided on a carrier and a solder ball is provided on a chip, as in FIG.

FIG. 3 illustrates a chip bonded with a solder ball to a carrier having connection pads and a solder coating,
(A) is a figure before solder reflow, (b) is a figure which shows after solder reflow, respectively.

FIG. 4 shows a chip having only input / output electrical connection pads,
It is a figure which shows the state joined to the carrier which has a pad and a solder ball, (a) is a figure before solder reflow, and (b) is a figure respectively after solder reflow.

FIG. 5 is a diagram showing a carrier on which a large number of chips each having a different input / output interconnection structure can be mounted.

FIG. 6 shows a cross-sectional view of a carrier substrate having electrical interconnect pads formed on its surface.

FIG. 7 is a cross-sectional view of the same carrier substrate as in FIG. 6, showing the interconnection protrusions formed on the connection pads of the carrier.

[Explanation of symbols]

 1 Chuck 3,15,25 Chip 5 Input / Output Connection Pad 7 Prism 9,19,23 Carrier 11,17,42 Electrical Interconnection Protrusion 13,21,44 Electrical Connection Pad 22 Solder Coating 40 Passive Device

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Charles Taylor Randolph 331 Endicott Antoinette Street, New York, United States 331 (72) Inventor Gustub Schrock, Austin, Texas, USA Spicewood PEK Double Wai 1101

Claims (2)

[Claims] 1. A multi-chip module manufacturing method for manufacturing a multi-chip module by bonding a plurality of integrated circuit devices having differently formed input / output interconnection points on a single substrate carrier. Forming a pattern of electrical interconnect pads on the carrier corresponding to the input / output interconnection points of a circuit device, and compatible with one input / output interconnection point of the integrated circuit device. Manufacturing a multi-chip module comprising: a mounting step of mounting a bonding material that bonds to an output interconnection point on a pattern of the pad; and a bonding step of bonding the integrated circuit device to the substrate carrier. Method. 2. A module comprising a plurality of integrated circuit devices having differently formed input / output interconnection points, wherein the substrate carrier has a plurality of patterns of conductive pads on its surface, and as an input / output interconnection point. At least one integrated circuit device having a conductive pad and fully bonded to a corresponding pad of the substrate carrier, and a solder ball protrusion as an input / output interconnection point, A module comprising at least one integrated circuit device fully bonded to a corresponding pad of the module.