JPH04362692A - Multi-port memory - Google Patents

Abstract

PURPOSE:To speed up a system and reduce its size by using a frame memory which enables access to an optimum rectangular area for reading and writing from the side of a computer while horizontal serial access for a display device is still enabled. CONSTITUTION:When respective memory cell arrays 1 in a block are accessed in series, a transfer gate 2 selects the cell array by a transfer gate control circuit 4 by using some of column addresses 32 and data in the (y)-coordinate is latched in a serial register 3 for the display device.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of Industrial Application The present invention relates to a multi-port memory for temporarily storing display data of a cathode ray tube (hereinafter abbreviated as CRT) used for display in computers and the like.

0002

2. Description of the Related Art A 1M bit dual port memory will be described as an example of a conventional multiport memory. Figure 2 shows its block diagram. The cycle of reading and writing drawing data will hereinafter be abbreviated as random access. Further, a cycle in which data from a memory cell array is transferred to a serial register in a memory in order to supply data to a display device will hereinafter be abbreviated as serial access.

Memory cell array 20 with 512 rows and 512 columns
1 by a 512-bit serial register 21 and a column decoder 22 that selects the bit to be randomly accessed.
The dual port memory is composed of four blocks 11a to 11d.

In random access, 512 bits of data in the memory cell 20 corresponding to the row address in each block are sensed, and the column decoder 22 selects one of the 512 bits.
By selecting 1 bit and connecting it to the random port 24, reading and writing 4 bits at a time is performed.

In serial access, 512 bits of data in a memory cell corresponding to a row address in each block are sensed and latched into each serial register 21. Using a clock obtained by dividing the pixel display speed of the display device by 1/4, 4 bits are sequentially read out from the serial register 21 through the serial port 23 and displayed on the display device.

[0006]

When a multi-port memory is used for display on a computer or the like, random access is very often performed locally to the display device. Therefore, to show the drawing ability of a computer, the drawing speed of a straight line of about 10 to 20 pixels or 10x
A drawing speed of about 10 pixels is used.

However, in the conventional technology, the column data of the serial register 21 and the memory cell 20 have a one-to-one correspondence, and since the display device scans in the horizontal direction, random access also occurs in the horizontal direction with respect to the display device. Generally, this could only be done by bit placement. Although it is possible to configure one plane using a plurality of small-capacity memories, there are problems such as an increase in the number of external circuits.

The present invention provides a multi-port memory that realizes system miniaturization and speedup by enabling horizontal serial access for a display device and random access of a rectangular area that is optimal for computer drawing. The purpose is to

[0009]

[Means for Solving the Problems] A multi-port memory of the present invention has a plurality of input/output terminals for reading and writing drawing data, an output terminal for displaying drawing data, and a plurality of memory cell arrays for storing drawing data. and a multi-port memory having a serial register for temporarily storing data to be output to the output terminal, a transfer gate for transferring data from the memory cell array to the serial register, and a transfer gate for transferring data from the memory cell array to the serial register according to an address. control means for selectively transferring data to the serial register via the serial register, and outputting data in the horizontal direction of the display device from the output terminal for display while reading and writing drawing data in units of rectangular areas. The feature is that it can be accessed with .

0010

According to the present invention, with the above-described configuration, random access can be performed in a rectangular area while supplying drawing data to the display device in the horizontal direction. Therefore, when random access is performed in a 4x4 rectangular area, compared to when it is performed in a 16x1 line area, the memory access speed alone is 3 times faster and 10 times faster when 15 dots are generated in a straight line in any direction.
By filling in a rectangular area of x10, the speed can be increased by about twice. Furthermore, considering the calculation time for straight line generation, when accessing in a 4x4 rectangular area, the calculation time is required for a maximum of 4 points, but when accessing in a 16x1 area, a maximum of 16 points calculation time is required. The load on the external circuit can be reduced by accessing the data using . Therefore, by using the present invention, the system can be made smaller and faster.

[0011]

[Example] Specific examples will be described in detail below. As an example, a case will be described in which a 1M bit memory with 16 bits of random access is used as a frame buffer of a 1024x1024 pixel display device. FIG. 1 is a block diagram showing the configuration of a multiport memory in one embodiment of the present invention.

A memory cell array 1 of 512 rows and 128 columns, four column decoders 5 each, a transfer gate 2 for selecting one cell array from each memory cell array, a transfer gate control circuit 4 for determining the selected cell array, and a serial The register 3 forms one block 10, and the multiport memory consists of four blocks 10a to 10d.
Consists of.

Random access is performed as follows. Each 128-bit data is sensed from the 16 cell arrays 1 of 512 rows and 128 columns connected to the word line selected by the given row address. Furthermore, the column decoder 5 selects 1 bit each from the given column address and connects it to the random port 6, making it possible to read and write 16 bits.

FIG. 3 is a detailed circuit diagram of the transfer gate 2, serial register 3, and transfer gate control circuit 4 of a certain block shown in FIG. Serial access is performed as follows. 128 bits of data are sensed for each cell array 1 from 16 cell arrays 1 of 512 rows and 128 columns connected to the word line selected by the given row address. Next, for each block, the transfer gate control circuit 4 operates the 128 transfer gates in the transfer gates 2 using the two bits of the given column address 32 and the transfer timing signal 30. Further, the data selected by the transfer gate is written into the serial register 3 according to the transfer timing signal 30. The serial register 3 for each block outputs 4 bits at a time from the serial port 7, 1 bit at a time, in response to a serial read signal 31 using an externally applied clock.

In a system configured using the multi-port memory configured as described above, a conceptual diagram showing the relationship between the (x, y) coordinates of the actual display device and the address of the multi-port memory of the present invention is shown. 4. 40 shows how it looks on a display device, and 41 is an arrangement of one word of data at the time of random access.

In the display device 40, a small area surrounded by a square is 1
This is an area that is accessed by random access once, and the number inside is the address that indicates the word. The upper 8 bits are the row address and the lower 8 bits are the column address. 41 is the arrangement of data accessed in one word on the display device, and the numerical value therein indicates which bit of the data.

In the case of random access, one memory cell is selected from each memory cell array 1 based on the address. Each bit of data that is randomly accessed is
Each cell array is arranged so that data of the same x coordinate is stored in each block. For example, the block 10a in FIG. 1 corresponds to the 15th, 11th, 7th, and 3rd bit data. rd[N] in FIG. 1 indicates N bits of the random access data line (N is 0 to 15).

In the case of serial access, two bits of the column address 32 are used to determine which memory cell to select for each block. The data of each memory cell array selected in each block is displayed on the display device.
Since the coordinates are entered with the same value, the serial register 3 of each block can be accessed for writing using the same y-coordinate.

Although a 1M 16-bit dual port memory is used in this embodiment, it goes without saying that it does not depend on the memory capacity.

[0020]

As described above, according to the present invention, by controlling writing to the serial register using part of the column address in the serial access section,
By configuring a multiport memory that can access a rectangular area and using the multiport memory in a display device such as a computer, the device can be made smaller and faster.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a multiport memory in an embodiment of the present invention.

FIG. 2 is a block diagram showing the configuration of a conventional multiport memory.

FIG. 3 is a detailed circuit diagram of a transfer gate, a serial register, and a transfer gate control circuit of a certain block shown in FIG. 2;

FIG. 4 is a conceptual diagram showing addresses in a memory and addresses on a display device in an embodiment of the present invention.

[Explanation of symbols]

1 Cell array 2 Transfer gate 3 Serial register 4 Transfer gate control circuit 5 Column decoder 6 Random port 7 Serial port 30 Transfer timing signal 31 Serial read signal 32 Column address signal

Claims (1)

[Claims] 1. A plurality of input/output terminals for reading and writing drawing data, an output terminal for displaying drawing data, a plurality of memory cell arrays for storing drawing data, and temporarily storing data to be output to the output terminals. A multi-port memory having a serial register, a transfer gate for transferring data from the memory cell array to the serial register, and a transfer gate for selectively transferring data from the memory cell array to the serial register via the transfer gate according to an address. 1. A multi-port memory, characterized in that the multi-port memory has a control means for controlling the display, and accesses in units of rectangular areas when reading and writing drawing data while outputting data in the horizontal direction of a display device from the output terminal for display.