JPH04352057A - Interruption information circuit - Google Patents

Abstract

PURPOSE:To make it possible to surely execute the whole interrupting processing even when the generation of plural kinds of interruption requests generated at optional timing is informed to a CPU through one signal line. CONSTITUTION:This interruption informing circuit is provided with an OR circuit 3 to be an informing circuit for informing the generation of plural kinds of interruption requests generated at optional timing through one signal line, flip-flops(FFs) 11 to 13 to be storing circuits for storing the contents of the kinds of the generated interruption requests and a gate circuit 10 to be a sending circuit for sending the contents of the FFs 11 to 13 to the CPU in response to an interruption receiving signal 8 outputted from the CPU. Since plural interruption requests are informed through one signal line, the number of signal lines is not increased and the system can be compacted.

Description

[Detailed description of the invention]

0001

TECHNICAL FIELD The present invention relates to an interrupt notification circuit, and more particularly to an interrupt notification circuit in a microcomputer system.

0002

2. Description of the Related Art In microcomputer systems, high priority processing is generally processed by interrupting the CPU. The CPU has an interrupt request input and an interrupt acceptance output, and when a processing request occurs, an interrupt signal is generated to the CPU, and when accepted by the CPU, an interrupt acceptance output is output from the CPU and the interrupt signal is cleared.

Conventionally, when notifying the CPU of the interrupt signal, multiple signal lines were used to notify the CPU, which hindered miniaturization of the system. To solve this problem, a method of notification using a single signal line can be considered.

However, in interrupt processing in a microcomputer system, when multiple interrupt factors are notified together via a single interrupt signal line, the interrupts occur asynchronously with respect to the CPU. There is a drawback that when an acceptance signal and an interrupt request due to other factors occur almost simultaneously, the interrupt request that occurs later may not be processed.

[0005]

[Object of the Invention] The present invention has been made to solve the above-mentioned conventional drawbacks, and its purpose is to ensure that all interrupts are processed even if the CPU is notified through a single interrupt signal line. An object of the present invention is to provide an interrupt notification circuit that can perform interrupt notifications.

[0006]

SUMMARY OF THE INVENTION The interrupt notification circuit according to the present invention includes a notification circuit that notifies a CPU of the occurrence of multiple types of interrupt requests that occur at arbitrary timing, and a notification circuit that notifies the CPU of the occurrence of multiple types of interrupt requests that occur at arbitrary timings, and The present invention is characterized by comprising a holding circuit that holds contents, and a sending circuit that sends out the contents of the holding circuit to the CPU in response to an interrupt acceptance signal output from the CPU in response to a notification from the notification circuit.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of an interrupt notification circuit according to the present invention. In the figure, an interrupt notification circuit according to an embodiment of the present invention receives three types of interrupt request trigger signals 51 to 53 as input and notifies them to a CPU (not shown) through a single signal line.

Interrupt request flip-flops (hereinafter abbreviated as interrupt request F/F) 11, 12, and 13 hold corresponding interrupt trigger signals 51 to 53, respectively. And each interrupt request signal 61 to 6 which is the output
3 are put together by the OR circuit 3 and notified to the CPU through a single signal line.

[0010] Also, the interrupt request latch register 2 is CP
The interrupt request signals 61 to 63 are held at the rising timing of the interrupt acceptance signal 8 from U, and the values are sent to the gate circuit 1.
In addition to being sent to the data bus of the CPU via 0, it is also input to NAND circuits 41-43.

The NAND circuits 41 to 43 are circuits that initialize the corresponding interrupt request F/F when each NAND condition is satisfied.

The gate circuit 10 has an enable terminal EN, and when the input to this enable terminal becomes low level, the gate circuit 10 enters the enabled state and transfers the contents of the latch register 2 to C.
This is a circuit that sends data to the PU data bus. Note that 80 is an inverter.

In this configuration, the interrupt request trigger signals 51 to 53 are respectively turned on when an interrupt factor occurs, and this is used as a trigger to trigger the corresponding interrupt request F/F 11.
Interrupt request signals 61 to 63, which are the outputs of signals 1 to 13, become high level. Each interrupt request signal 6 is logically summed by an OR circuit 3, and is combined into one signal as an interrupt signal 7 to be sent to the CPU.
will be notified. When a CPU (not shown) receives the interrupt request signal 7, it outputs an interrupt acceptance signal 8. The interrupt acceptance signal 8 is normally a pulse, and in this case also is a high level pulse.

The interrupt request latch register 2 latches each of the interrupt request signals 61 to 63 at the rising timing of the interrupt acceptance signal 8. The latched signals are NANDed with the interrupt acceptance signal 8, and their outputs are input to the clear terminals of the interrupt request F/Fs 11-13. Interrupt request F/F11 whose interrupt request signal is on
13, since the NAND output of the interrupt request latch register 2 and the interrupt acceptance signal 8 becomes low level, the interrupt request F/F is initialized by this signal and the interrupt request signal 6 is turned off. Interrupt request F/F where interrupt request signal 6 is off at the time when interrupt acceptance signal 8 is input
Since the initialization signal remains off for , it is not initialized. An interrupt request that occurs while the interrupt acceptance signal 8 is on is normally output as an interrupt signal 7.

Next, using the time chart of FIG.
The operation of the circuit will be explained in more detail. FIG. 2 shows interrupt request trigger signals 51 to 5, which are signals of each part of the circuit in FIG.
3, interrupt request signals 61 to 63, interrupt signal 7 to the CPU, interrupt acceptance signal 8 from the CPU, outputs 91 to 93 of the interrupt request latch register 2, and the NAND circuit 4.
The outputs 410 to 430 of the outputs 1 to 43 and the values of the data bus of the CPU are shown.

First, when the interrupt request trigger signal 53 is input after the interrupt request trigger signal 51 is input, the following operation occurs.

That is, when the interrupt request trigger signal 51 is input, in response, the interrupt request signal 61 which is the output of the interrupt request F/F 11 becomes high level, and is notified to the CPU as the interrupt signal 7 ( ■). When the interrupt acceptance signal 8 is input from the CPU in response to this notification, the output 91 of the interrupt request latch register 2 becomes high level, the NAND condition is satisfied, the output 410 becomes low level, and the interrupt signal 7 becomes The level becomes low (■).

When the output 410 is at a low level, the contents of the outputs 91 to 93, that is, ON, OFF, OFF, are notified to the CPU on the data bus. This allows the CPU to recognize the contents of the interrupt request.

When the interrupt request trigger signal 53 is input while the output 410 is at a low level, in response, the interrupt request signal 6 which is the output of the interrupt request F/F 13 is input.
3 becomes high level and is notified to the CPU as an interrupt signal 7 (■). When the interrupt acceptance signal 8 is input from the CPU in response to this notification, the NAND condition is satisfied, the output 430 becomes low level, and the interrupt signal 7 becomes low level (■).

When the output 430 is at a low level, the CPU is notified of the contents of the outputs 91 to 93, that is, off, off, and on in this order, on the data bus. This allows the CPU to recognize the content of the type of interrupt request.

Next, when the interrupt request trigger signals 51 and 52 are input almost simultaneously, the following operation occurs.

That is, when the interrupt request trigger signal 51 is input, the interrupt request signal 61 which is the output of the interrupt request F/F 11 becomes high level in response, and is notified to the CPU as the interrupt signal 7 ( ■). Further, when the interrupt request trigger signal 52 is input immediately after that, the interrupt request signal 62 which is the output of the interrupt request F/F 12 also becomes high level (■) in response. In this case, the CPU has already been notified as the interrupt signal 7, and the interrupt signal 7 remains at a high level.

When the interrupt acceptance signal 8 is input from the CPU in response to the notification of the interrupt signal 7, the outputs 91 and 92 of the interrupt request latch register 2 become high level, and the NAND condition is satisfied, so that the outputs 410 and 420 becomes low level, and interrupt signal 7 becomes low level (■
).

When the outputs 410 and 420 are at a low level, the contents of the outputs 91 to 93, that is, ON, ON, OFF, are notified to the CPU on the data bus. This allows the CPU to recognize the content of the type of interrupt request.

As described above, no matter what timing multiple types of interrupt requests occur, it is possible to notify the CPU of the occurrence through a single signal line, and also to notify the contents. be. Furthermore, since the content of the interrupt request is notified using the data bus originally provided in the CPU, there is no need to increase the number of signal lines.

Although the present embodiment has been described for the case where there are three types of interrupt requests, it is clear that the same effect can be obtained if the same configuration is applied to cases where there are more types of interrupt requests.

[0027]

As explained above, the present invention notifies the occurrence of an interrupt request that occurs at an arbitrary timing through a single signal line, and also detects the type of interrupt request in response to an acceptance signal from the CPU. By sending the contents to the CPU, not only can all interrupts be processed reliably, but also the microprocessor system can be made smaller.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an interrupt notification circuit according to an embodiment of the present invention.

FIG. 2 is a time chart showing the operation of each part in FIG. 1;

[Explanation of symbols]

2 Interrupt request latch register 3 OR circuit 10 Gate circuits 11, 12, 13 Interrupt request flip-flop 41
,42,43 NAND circuit

Claims (1)

[Claims] 1. A notification circuit that notifies a CPU through a single signal line of the occurrence of multiple types of interrupt requests that occur at arbitrary timing, and a holding circuit that holds the contents of the types of interrupt requests that have occurred. An interrupt notification circuit comprising: a sending circuit that sends the contents of the holding circuit to the CPU in response to an interrupt acceptance signal output from the CPU in response to the notification by the notification circuit.