KR950014185B1 - Interript processing apparatus for multi trouble source system - Google Patents

Abstract

The interrupt processing device in a system with a plurality of obstacle sources comprises: an obstacle state holding unit for outputting a signal for holding an active state of an interrupt signal; an obstacle generation collecting unit for inputting an obstacle source signal, a reset signal, a clear signal, a clock used to remove noise and the active holding signal and outputting an interrupt signal to the obstacle state holding unit; and an obstacle generation source reading unit for inputting a control signal for reading an obstacle source, and the obstacle information and interrupt signal from the obstacle generation collecting unit and outputting a data line signal for reading the obstacle source.

Description

Interrupt handler in systems with multiple fault sources

1 is a block diagram of an interrupt processing apparatus in a system having a plurality of fault sources according to the present invention.

FIG. 2 is a detailed configuration diagram of a failure state maintaining unit employed in the interrupt processing apparatus shown in FIG.

FIG. 3 is a detailed configuration diagram of the fault collection unit employed in the interrupt processing apparatus shown in FIG.

4 is a detailed configuration diagram of a failed reading unit employed in the interrupt processing apparatus shown in FIG.

5 is a pulse waveform diagram of various signals according to the present invention.

* Explanation of symbols for main parts of the drawings

1: Failure state maintaining unit 11: OR gate

2: Failure occurrence collecting unit 12,31: Inverter

3: Faulty buffer.

The present invention relates to an interrupt processing apparatus that is adapted to read a corresponding interrupt source using a data line after processing one interrupt for a total fault in a system having a plurality of fault sources.

Conventionally, when a failure occurs, the CPU handles each failure as an interrupt. However, when the failure occurs in any one of a plurality of failure sources, the present invention generates this to the CPU as one interrupt, and each failure after interrupt processing in the CPU. This allows the source to be read and cleared over the data line.

Accordingly, the present invention is intended to eliminate the disadvantages of the equivalent of the interrupt processing line, the increase of the load due to the plurality of interrupt processing by interrupt processing a plurality of conventional failure sources, respectively, in the fault source line using a flip-flop It is an object of the present invention to provide an interrupt processing apparatus in a system having a plurality of fault sources, which are implemented to remove even noise that may occur.

In order to achieve the above object, the present invention provides a device for processing interrupts in the event of a failure, wherein a plurality of fault source signals, a reset signal, and a signal for clearing after a fault source signal are read are received until the clear signal is activated. Fault state maintaining means for outputting a signal for keeping the interrupt signal to the CPU active; The fault source signal, the reset signal, the clear signal, and a clock used to remove noise on the interrupt line are input, and an active sustain signal from the fault state maintaining means is input to provide an interrupt signal to the fault state maintaining means. Collecting means for generating a fault at the same time; And faulty reading means for receiving a control signal for reading a fault source and receiving fault information and an interrupt signal from the fault occurrence collecting means and outputting a data line signal for reading the fault source. Is an logic sum processing means for receiving the fault source signal and performing an OR operation, an inverter for inverting and transmitting the interrupt signal, and an interrupt inputted to a data input terminal from an output of the OR operation means, and inverted through the inverter. A flip-flop that receives a signal at a clock terminal and a clear signal as a clear terminal, and performs an AND operation on the outputs of the clear signal, the reset signal, and the flip-flop to output the active sustain signal. Means for collecting said fault occurrence: said reset signal, First logical product processing means for receiving and logically processing any one of a rear signal and the plurality of disturbance source signals, and performing an AND operation on the other of the reset signal, the clear signal, and the plurality of disturbance source signals; Second logical product processing means, third logical product processing means for receiving an AND signal from one of the reset signal, the clear signal, and the plurality of faulty source signals, and performing logical AND processing; and the first to third logical products; A logic sum processing means for receiving an output of the processing means and the active holding signal and performing a logical sum processing; an output of the logic sum processing means is input to a data input terminal, a clock signal is input to a clock terminal, and the reset signal is input to a preset terminal; And a flip-flop for receiving and outputting the interrupt signal, wherein the faulted reading means comprises: a fault from the fault state maintaining means The first to third flip-flops and the output terminal of the first to third flip-flops receiving the beam through the data input terminal, the inverting the interrupt signal through the inverter, and the clock terminal and the clear signal into the clear terminal. And an input terminal connected to each other and a control terminal including the first to third tri-state buffers for receiving the control signal and outputting the data line signal. to provide.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention. First, before describing the operation, the signals used in the description of the present invention will be defined as follows.

RSTB: Hardware Reject Signal (Active Low Signal)

-FRDB: Control signal (active low signal) to read the fault source

-FRSTB: Signal to clear after reading the fault source (active low signal)

-FINTB: Interrupt signal (active low signal) to CPU in case of failure

-FR: Signal to keep FINTB signal active until FRSTB signal is active (Active High signal)

-CHKCLK: Clock used by removing noise on interrupt lines

-Flt0-Flt2: Fault Source Signal (Active High Signal)

D0 to D2: data line signal for reading the fault source

FIG. 1 is a block diagram of an interrupt processing apparatus according to the present invention. As shown in the drawing, the present invention inputs a fault source signal Flt0-Flt2, a reset signal RSTB, and a clear signal FRSTB. And a fault state maintaining part 1 for outputting a signal FS for keeping the interrupt signal FINTB active for the CPU active until the clear signal FRSTB is activated, and the fault source signal Flt0-Flt2. After receiving the reset signal RSTB, the clear signal FRSTB and the clock CHKCLK for clearing the fault source, and receiving the FS from the fault state maintaining unit 1, FINTB is inputted to the fault state maintaining unit 1. ) And a data line signal for reading the fault source by receiving the fault collection unit 2 which outputs to the outside and the control signal (F0, F1, F2) for reading the fault source and the interrupt signal for the CPU. And a failed reading unit 3 for outputting D0, D1, D2.

FIG. 2 is a detailed configuration diagram of the fault state maintaining unit 1 shown in FIG. 1, and as shown in FIG. 1, the fault state maintaining unit 1 receives an OR gate that receives an OR source signal and performs an OR operation. 11), the inverter 12 which inverts and transfers the FINTB, and the output of the OR gate 11 are input to the D input terminal, and the FINTB which is inverted through the inverter 12 is input to the clock stage, and the FRSTB is cleared. And an AND gate 13 for receiving the output of the FRSTB, the RSTB, and the D flip-flop 14, and performing an AND operation on the output of the FS.

FIG. 3 is a detailed configuration diagram of the failure collecting unit 2 shown in FIG. 1, and the failure generating unit 2 receives the RSTB, FRSTB, and Flt0 as shown in FIG. AND gate 21 for receiving AND TBRS, FRSTB and Flt1, AND gate 22 for logical AND processing, and NOR gate 24 for ORing the outputs and FS of AND gates 21, 22, and 23, respectively. And a D flip-flop 25 which receives the output of the NOR gate 24 as the D input terminal, receives the CHKCLK as the clock terminal, receives the RSTB as the preset terminal, and outputs FINTB.

FIG. 4 is a detailed configuration diagram of the failed reading unit 3 shown in FIG. 1, and as shown in the same figure, the failed reading unit 3 is separated from the failed state maintaining unit 2. As shown in FIG. The first to third D flip-flops 32 which receive the fault information (F0, F1, F2) of the input terminal D, inverts FINTB through the inverter 31, receives the clock terminal, and receives the FRSTB as the clear terminal. 33, 34, and an input terminal is connected to the output terminals of the first to third D flip-flops (32, 33, 34), respectively, and the control terminal receives the FRDB and outputs D0 to D2. Tri-state buffers 35, 36 and 37 are provided.

When the basic operation of the present invention configured as described above is explained, the initial state of the circuit is that FINTB is " 1 " due to the RSTB signal, so that there is no interruption for the occurrence of a failure. '' Is not reading the fault state.

In this state, any one of Flt0-Flt2 becomes '' 1 '' and when a fault occurs, the FINTB signal is activated in response to the rising of the fault check clock (CHKCLK). After accepting an interrupt, activate the FRDB signal to "0" to identify the source that failed. At this time, the source of the failure is read as "1" through the D0-D1 data line so that the source of the failure can be known. The fault state is maintained until the FRSTB is activated and the fault state is cleared.

After the FRSTB signal is activated, the fault state is cleared and when another fault occurs, the above process is repeated.

Next, the operation of the present invention will be described in detail. When initialization is performed by RSTB and FRSTB, FINTB is activated while any one of the fault generating signals Flt0-Flt2 is activated.

At this time, the FS signal, which is a signal for maintaining the fault state, is also active and keeps the FINTB active until the CPU generates a fault clear signal, FRSTB.

In the case of the FINTB signal, the clock is clocked at the rising edge of CHKCLK. Therefore, in case of noise that does not occur and is maintained for more than one cycle of CHKCLK, do not activate the FINTB signal.

5 is a pulse waveform diagram of various signals according to the present invention, showing in detail the timing relationship of each signal according to the operation of the present invention described above.

Therefore, the present invention configured as described above can monitor the state of a number of fault sources using the interrupt generation line of the HA, and there is an effect that can prevent the interrupt that may be recognized by the cycle of CHKCLK.

Claims (1)

An apparatus for processing interrupts when a fault occurs, wherein a plurality of fault source signals, a reset signal, a fault source signal are read, a signal for clearing is input, and an interrupt signal for the CPU is kept active until the clear signal is activated. Disturbance state holding means (1) for outputting a signal for causing a signal to be received: The fault state holding means (1) receives a clock used to remove noise for the disturbance source signal, the reset signal, the clear signal, and the interrupt line A fault generating collecting means (2) which receives an active holding signal from the same and provides an interrupt signal to the fault state maintaining means (1) and outputs it to the outside; And faulted reading means 3 for receiving a control signal for reading a fault source and receiving fault information and an interrupt signal from the fault occurrence collecting means 2 and outputting a data line signal for reading the fault source. The fault state maintaining means 1 includes: a logic sum processing means 11 for receiving the fault source signal and performing a logic sum processing, an inverter 12 for inverting and transmitting the interrupt signal, and the logic sum processing means 11. A flip-flop (14) which receives the output of the data input terminal and receives the interrupt signal inverted through the inverter 12 as the clock terminal and the clear signal as the clear terminal, and the clear signal and the reset signal. And a logic product processing means (13) for receiving a signal and an output of the flip-flop (14) and performing an AND operation to output the active sustain signal. Step (2) comprises: first logical product processing means (2l) for receiving and logically processing any one of the reset signal, the clear signal and the plurality of disturbance source signals, and the reset signal, the clear signal and the Second logical product processing means 22 for receiving and logically processing the other one of the plurality of disturbance source signals, and performing an AND operation receiving the reset signal, the clear signal, and another signal of the plurality of disturbance source signals; Third logical product processing means 23, logical OR processing means 24 for receiving an output of the first to third logical product processing means 21, 22, and 23 and the active holding signal and performing logical OR processing; And a flip-flop (25) for receiving the output of the logic sum processing means (24) as a data input terminal, receiving a clock signal as a clock terminal, and receiving the reset signal as a preset terminal and outputting the interrupt signal. Occur The reading means 3 receives the fault information from the fault state maintaining means 1 through the data input terminal, receives the interrupt signal through the inverter 31, receives the clock signal, and clears the clear signal to the clear stage. Input terminals are respectively connected to the first to third flip-flops 32, 33, and 34, and output terminals of the first to third flip-flops 32, 33, and 34, and a control terminal receives the control signal. And first to third tri-state buffers (35, 36, 37) for outputting said data line signal.