JPH04350743A - Cache memory - Google Patents

Abstract

PURPOSE:To reduce the use ratio of a common bus in a close-coupling multiprocessor system where plural processors having peculiar cache memories are coupled to a shared memory through the common bus. CONSTITUTION:When a processor reads out a lock bit after failing to acquire a snoop lock, a register 23 is set by the processor. If a miss occurs in a comparator 18 in this state, a control circuit 25 detects it to execute an undividable cycle. When the processor starts the undividable cycle, it is detected by an undividable cycle detector 24, and the register 23 is reset, and the control circuit 25 terminates the control of the undividable cycle.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] This invention relates to a tightly coupled multiprocessor system in which a plurality of processors are coupled to a shared memory via a shared bus. This is related to cache memory.

0002

2. Description of the Related Art The configuration of a conventional tightly coupled multiprocessor system using a cache memory will be described with reference to FIG. FIG. 6 is a block diagram showing a conventional tightly coupled multiprocessor system. In FIG. 6, 1 to 4 are processors, 5 to 8 are cache memories that are uniquely connected to the processors 1 to 4, respectively, and 9 is a shared memory that is connected to the cache memories 5 to 8 via a shared bus 10. be. Note that the cache memories 5 to 8 all have the same configuration.

Next, the operation of a conventional tightly coupled multiprocessor system will be explained with reference to FIG. The cache memories 5 to 8 monitor the respective processors 1 to 4 and the shared bus 10, for example, as outlined in "Parallel Processing Mechanism" by Yoshizo Takahashi et al. published by Maruzen Co., Ltd., pages 180 to 199. , the processors 1 to 4 and the shared bus 10, and operates according to a predetermined procedure (cache coherency protocol). Cache coherency protocols are used, for example, in ``computer''. 1
990.6 (COMPUTER, June, 1990)
Gary Graunke,
Sh-reekant Soccer
``Synchronization Algorithm for Shared Memory Multiprocessors''
n Algorithms for Shared-M
(hereinafter referred to as Document B). Note that here, the processors 1 to 4 have equal priority over the shared bus 10.

In a tightly coupled multiprocessor system, processors 1 to 4 must exercise exclusive control when using shared resources. The lowest level exclusive control algorithm is called spinlock. A spinlock is exclusive control that determines whether a shared resource can be used by locking or clearing a lock bit present in the shared resource. If the lock bit is clear, the spinlock is free and the shared resource is not in use, so any processor has the right to lock the lock bit and use the shared resource (acquiring the spinlock ). If the lock bit is locked, the spinlock has been acquired by one of the processors, the shared resource is being used, and no other processor can obtain the right to use the shared resource ( (Failed to acquire spinlock)
.

[0005] Spinlocks are usually controlled by busy waits, and acquisition and release of spinlocks are usually executed in indivisible cycles. In addition, an indivisible cycle is a cycle in which a processor spins A processor cycle that reads, performs a logical operation, and writes a lock bit from a shared resource without interrupting the bus cycle to the shared bus to ensure locking. At this time, a signal indicating an indivisible cycle is output from the processor.

[0006] Here, the configuration of a conventional cache memory will be explained based on FIG. 7. FIG. 7 is a block diagram showing a conventional cache memory. In FIG. 7, 11 is a cache data memory, 12 is a tag memory, 13 is connected to the cache data memory and the tag memory 12, and is connected to the processor through a processor control bus a,
It is also a control circuit connected to the shared bus via a shared bus control bus b.

A buffer 14 is connected to the processor through the processor address bus c and a shared bus through the shared bus address bus d; and 15 is a buffer whose input side is connected to the processor and the shared bus through the processor address bus c and the shared bus address bus d. a selector 16 connected to the tag memory 12 and having an output side connected to the tag memory 12;
17 is a selector whose input side is connected to the processor and the shared bus through a processor address bus c and a shared bus address bus d; 17 is a selector whose input side is connected to the output side of the selector 16 and whose output side is connected to the tag memory 12; The input side of the buffer 18 is the tag memory 12 and the selector 16.
a comparator 1 connected to the output of the buffer 17 and to the buffer 17;
Reference numeral 9 denotes a selector whose input side is connected to the processor and the shared bus through the processor address bus c and the shared bus address bus d, and whose output side is connected to the cache data memory 11.

20 is a transceiver connected to the cache data memory 11 and to the processor through a processor data bus h; 21 is a transceiver connected to the cache data memory 11 and to the shared bus through a shared bus data bus i; The transceiver 22 is a buffer whose input side is connected to the control circuit 13 and whose output side is connected to the tag memory 12. Note that control lines connecting the selectors 15, 16, and 19, the buffers 14, 17, and 22, and the transceivers 20 and 21 to the control circuit 13 are omitted.

Next, the operation of a conventional cache memory will be explained with reference to FIG. Cache data memory 11 stores data in the shared memory. Also,
The tag memory 12 holds address information of data (cache entry) stored in the cache data memory 11 and a control bit indicating whether the cache entry is valid or invalid.

The control circuit 13 constantly monitors the processor control bus a and the shared bus control bus b, detects accesses from the processor through the processor control bus a, accesses the shared bus through the shared bus control bus b, and Detects accesses on the shared bus by other processors. When the control circuit 13 detects an access from the processor or the shared bus, it controls the buffer 14 and the selector 15, and sends the address information and control bits held in the tag memory 12 to the comparator 18 via the control line e. read out. Also, the control circuit 13 controls the selector 16 and the buffer 17.
is controlled and the address to be accessed from the processor via the processor address bus c or from the shared bus via the shared bus address bus d is determined by the comparator 1.
8 is input.

The comparator 18 compares the address information with the address to be accessed. As a result of the comparison, if they match and the control bit indicates valid, it is a hit, and in this case the comparator 18 makes the hit determination line f valid. Also, these match,
If the control bit does not indicate valid, it is a miss, and in this case, the comparator 18 invalidates the hit determination line f.

The control circuit 13 controls the selector 19 and the transceivers 20 and 21, accesses the shared bus through the shared bus control bus b according to the validity or invalidity of the hit determination line f, and accesses the cache data memory through the control line g. 11 for writing or reading. Thereby, data is exchanged between the processor and the shared bus through the processor data bus h, the transceiver 20, the cache data memory 11, the transceiver 21, and the shared bus data bus i.

Then, the control circuit 13 generates information for validating or invalidating the written or read cache entry, outputs it to the buffer 22 through the generation control bit line j, and inputs the information to the control bit of the tag memory 12. Enable or disable is written through the control line e, and the shared bus is accessed through the shared bus control bus b as necessary.

[0014] When such a conventional cache memory is used in a tightly coupled multiprocessor system to perform a spinlock, a processor that fails to acquire a spinlock continues to access the shared bus until it succeeds in acquiring a spinlock. . For this reason, spinlocks have the disadvantage of increasing the load on the shared bus. Therefore, spinlock has been improved and there is an algorithm called snooplock.

Next, the operation of the snoop lock when a conventional cache memory is connected will be explained with reference to FIG. FIG. 8 is a flowchart showing the snoop lock operation of a processor connected to a conventional cache memory, as shown in Document B, for example, in which (a) shows the snoop lock acquisition operation, and (b) shows the snoop lock operation. Indicates a lock release operation.

(a) Snoop Lock Acquisition Operation In step S1, the processor starts an atomic cycle and reads the lock bit. In step S2, the processor writes to the lock bit to put it into a locked state and ends the atomic cycle. In step S3, the processor checks whether the read lock bit is in a locked state, and if the lock bit is in a locked state and the snoop lock has been acquired by another processor (in the case of YES), step S4
Proceed to.

In step S4, the processor reads the lock bit by normal reading. At this time, a cache entry including a lock bit is created in the cache memory of the processor. In step S5, the processor checks whether the read lock bit is in the locked state, and if the lock bit is in the locked state and the snoop lock has been acquired by another processor (in the case of YES), the process returns to step S4. Further, if the lock bit is in a clear state and the snoop lock is in a released state (in the case of NO), the processor returns to step S1.

Note that when the snoop lock is released by another processor, the cache entry including the lock bit is invalidated in the cache memory of the processor. Until this point, the processor has performed steps S4 to S5.
This loop is repeated and the lock bit is read from the processor's cache memory, and the shared bus is not accessed during this time. Further, after the snoop lock is released by another processor and the cache entry including the lock bit is invalidated in the processor's cache memory, the processor accesses the shared bus and reads the lock bit from the shared memory in step S4.

In step S3, the processor checks whether the lock bit is in the locked state, and if the lock bit is in the clear state and the snoop lock is in the released state (if NO), the operation ends.

(b) Snoop lock release operation The processor acquires a snoop lock through the snoop lock acquisition operation (a), and after completing the operation of the shared resource, clears the lock bit and releases the snoop lock in step S6. .

Next, in a tightly coupled multiprocessor system using a conventional cache memory, the bus cycle on the shared bus occurs when processors 1 to 4 simultaneously request a snoop lock and a conflict occurs on the shared bus. , will be explained with reference to FIG. FIG. 9 is a timing chart showing access to a shared bus when a snoop lock is executed by processors 1 to 4 in a conventional tightly coupled multiprocessor system using a cache memory. In FIG. 9, RE is exclusive read and R is read.

In the initial state, there are no cache entries including lock bits in the cache memories 5-8 of the processors 1-4, respectively.

At time t1, processor 1 acquires the right to use the shared bus, starts an atomic cycle, and reads the lock bit by exclusive reading. At this time, a cache entry including a lock bit is created in the cache memory 5 of the processor 1.

Note that by exclusive reading, the processor obtains the right (ownership) to write to the lock bit. In addition, when exclusive reading is performed, if a cache entry containing a lock bit exists in the cache memory of another processor, and this is in a valid state, the cache entry containing the lock bit in the cache memory of the other processor is invalidated. be done.

Therefore, at time t1, processor 1
obtains ownership of the lock bit, and also cache memory 6 of processor 2 and cache memory 7 of processor 3
And in the cache memory 8 of the processor 4, there is no cache entry including the lock bit, so
Cache memory 6, cache memory 7, and cache memory 8 do nothing. Processor 1 then writes to the lock bit to acquire the snoop lock and completes the atomic cycle. At this time, the cache entry including the lock bit is validated in the cache memory 5. Processor 1 then begins operating the shared resource.

At time t2, processor 2 acquires the right to use the shared bus, starts an atomic cycle, and reads the lock bit by exclusive reading. At this time, a cache entry including a lock bit is created in the cache memory 6. Also, at this time, the cache entry including the lock bit in the cache memory 5 is invalidated. Processor 2 then writes to the lock bit to end the atomic cycle. At this time, the cache entry including the lock bit is validated in the cache memory 6. Since processor 1 has already acquired the snoop lock, processor 2 fails to acquire the snoop lock.

At time t3, processor 3 acquires the right to use the shared bus, starts an atomic cycle, and reads the lock bit by exclusive reading. At this time, a cache entry including a lock bit is created in the cache memory 7. Also, at this time, the cache entry including the lock bit in the cache memory 6 is invalidated. Processor 3 then writes to the lock bit to end the atomic cycle. At this time, the cache entry including the lock bit in the cache memory 7 is validated. Since processor 1 has already acquired the snoop lock, processor 3 fails to acquire the snoop lock.

At time t4, processor 4 now acquires the right to use the shared bus and starts an atomic cycle.
Read the lock bit using exclusive read. At this time, a cache entry including a lock bit is created in the cache memory 8. Also, at this time, the cache entry including the lock bit in the cache memory 7 is invalidated. Processor 4 then writes to the lock bit to end the atomic cycle. At this time, the cache entry including the lock bit is validated in the cache memory 8. Since processor 1 has already acquired the snoop lock, processor 4 fails to acquire the snoop lock.

Further, processor 4 reads the lock bit from cache memory 8 by normal reading (step S4 in FIG. 8). In the cache memory 8, the cache entry including the lock bit in the locked state is in the valid state, so the processor 4 performs steps S4 to S5 in FIG. 8 until the snoop lock is released.
This loop is repeated to continue reading the lock bit from the cache memory 8.

At time t5, processor 2 acquires the right to use the shared bus and reads the lock bit from the shared memory by normal reading (step S4 in FIG. 8).
. At this time, a cache entry including a lock bit is created in the cache memory 6. Since the lock bit is in the locked state, the processor 2 performs step S5 in FIG.
The process then proceeds to step 4, and the loop of steps S4 to S5 in FIG. 8 is repeated until the snoop lock is released, and the lock bit is continued to be read from the cache memory 6.

At time t6, processor 3 acquires the right to use the shared bus and reads the lock bit from the shared memory by normal reading (step S4 in FIG. 8).
. At this time, a cache entry including a lock bit is created in the cache memory 7. Since the lock bit is in the locked state, the processor 3 performs step S5 in FIG.
The process then proceeds to step S4, and the loop of steps S4 to S5 in FIG. 8 is repeated until the snoop lock is released, and the lock bit continues to be read from the cache memory 7.

At time t7, when processor 1 finishes operating the shared resource and reads the lock bit from cache memory 5 to release the snoop lock, the lock bit on cache memory 5 has already been invalidated at time t2. Therefore, the cache memory 5 causes a miss. To this end, processor 1 starts an atomic cycle and reads the lock bit from the shared memory by exclusive read. At this time, a cache entry including a lock bit is created in the cache memory 5. Also, at this time, cache memory 6, cache memory 7
In the cache memory 8, the cache entry including the lock bit is invalidated. Processor 1 then writes to the lock bit to clear the lock bit and completes the atomic cycle. As a result, processor 1 releases the snoop lock.

At time t8, since the cache entry including the lock bit on the cache memory 6 has already been invalidated at time 7, the processor 2 repeating the loop of steps S4 to S5 in FIG. When reading the lock bit in S4, the cache memory 6 causes a miss. Therefore, processor 2 acquires the right to use the shared bus and reads the lock bit from the shared memory by normal reading. At this time, a cache entry including a lock bit is created in the cache memory 6. Since the lock bit has already been cleared, the operation of the processor 2 proceeds from step S5 to step S1 in FIG.

At time t9, the cache entry including the lock bit on the cache memory 7 has already been invalidated at time t7, so steps S4 to S5 in FIG.
When the processor 3 repeating the loop reads the lock bit in step S4 of FIG. 8, a miss occurs in the cache memory 7. For this reason, processor 3
acquires the right to use the shared bus and reads the lock bit from shared memory using a normal read. At this time, a cache entry including a lock bit is created in the cache memory 7. Since the lock bit has already been cleared, the operation of the processor 3 is to proceed to step S5 in FIG.
The process then proceeds to step S1.

At time t10, cache memory 8
Since the cache entry containing the above lock bit has already been invalidated at time 7, steps S4 to S5 in FIG.
When the processor 4 repeating the loop reads the lock bit from the cache memory 8 in step S4 of FIG. 8, the cache memory 8 causes a miss. Therefore, processor 4 acquires the right to use the shared bus,
Read the lock bit with a normal read from shared memory. At this time, a cache memory including a lock bit is created in the cache memory 8. Since the lock bit has already been cleared, the operation of the processor 4 proceeds from step S5 to step S1 in FIG.

At time t11, processor 2 acquires the right to use the shared bus, starts an atomic cycle, and reads the lock bit by exclusive reading. At this time, a cache entry including a lock bit is created in the cache memory 6. Further, at this time, cache entries including lock bits are invalidated in the cache memory 7 and the cache memory 8. Processor 2 then writes to the lock bit to put it into a locked state and completes the atomic cycle. At this time, the cache entry including the lock bit is validated in the cache memory 6. As a result, processor 2 acquires the snoop lock. Processor 2 then begins operating the shared resource.

At time t12, processor 3 acquires the right to use the shared bus, starts an indivisible cycle, and reads the lock bit by exclusive reading. At this time,
A cache entry including a lock bit is created in the cache memory 7. Also, at this time, the cache entry including the lock bit in the cache memory 6 is invalidated. Processor 3 then writes to the lock bit and ends the atomic cycle. At this time, the cache entry including the lock bit in the cache memory 7 is validated. Processor 2 already
has acquired the snoop lock, processor 3 fails to acquire the snoop lock.

At time t13, processor 4 acquires the right to use the shared bus, starts an indivisible cycle, and reads the lock bit by exclusive reading. At this time,
In the cache memory 8, a cache entry including a lock bit is created. Also, at this time, the cache entry including the lock bit in the cache memory 7 is invalidated. Processor 4 then writes to the lock bit to end the atomic cycle. At this time, the cache entry including the lock bit in the cache memory 8 is validated. Processor 2 already
has acquired the snoop lock, processor 4 fails to acquire the snoop lock.

Further, processor 4 reads the lock bit from cache memory 8 by normal reading (step S4 in FIG. 8). Since the cache entry including the lock bit is valid in the cache memory 8, the processor 4 repeats the loop of steps S4 to S5 in FIG. 8 until the snoop lock is released, and continues reading the lock bit from the cache memory 8. .

At time t14, processor 3 acquires the right to use the shared bus and reads the lock bit by normal reading (step S4 in FIG. 8). At this time,
In the cache memory 7, a cache entry including a lock bit is created. Since the lock bit is in the locked state, the processor 3 proceeds from step S5 to step S4 in FIG. 8, repeats the loop of steps S4 and S5 in FIG. 8 until the snoop lock is released, and continues reading the lock bit from the cache memory 7. .

[0041]

[Problem to be Solved by the Invention] When a snoop lock is executed in a tightly coupled multiprocessor system using conventional cache memory as described above, accesses from multiple processors are simultaneously shared in order to acquire the snoop lock. The cache entry containing the lock bit is invalidated in the cache memory of the processor that is output to the bus and cannot acquire the snoop lock, so the shared bus must be accessed again to enable the cache entry containing the lock bit. Therefore, there was a problem in that the usage rate of the shared bus was high.

The present invention has been made to solve these problems, and an object of the present invention is to provide a cache memory that can reduce the usage rate of a shared bus in a tightly coupled multiprocessor system.

[0043]

SUMMARY OF THE INVENTION A cache memory according to a first aspect of the present invention is provided with a register for instructing whether or not access to a shared bus is performed in atomic cycles.

Further, the cache memory according to claim 2 of the present invention detects a predetermined access cycle to a register and a lock bit on the shared bus for instructing whether or not access to the shared bus is performed in atomic cycles. sometimes,
If the corresponding cache entry exists in an invalid state, control means is provided for changing the corresponding cache entry to a valid state.

[0045]

In the cache memory according to claim 1 of the present invention, the register instructs whether or not access to the shared bus is performed in atomic cycles.

In the cache memory according to claim 2 of the present invention, the register instructs whether or not to access the shared bus in atomic cycles, and the control means controls whether or not to access the lock bit on the shared bus. If a corresponding cache entry exists in an invalid state when a predetermined access cycle is detected, the corresponding cache entry is changed to a valid state.

[0047]

【Example】

Example 1. The configuration of Embodiment 1 of this invention will be described with reference to FIG. FIG. 1 is a block diagram showing a first embodiment of the present invention. In FIG. 1, 1 to 12 and 14 to 22
is the same as the conventional example. 23 is a register connected to the processor through a register selection line k, 24 is an indivisible cycle detector whose output side is connected to the register 23 and whose input side is connected to the processor through a processor control bus a, and 25 is a conventional control. This is a control circuit connected in place of the circuit 13. Note that the selectors 15, 1
6 and 19, buffers 14, 22 and 23, and control lines connecting the transceivers 20 and 21 to the control circuit 25 are omitted. Further, the indivisible cycle detector 24 is omitted in the conventional example.

Next, the operation of the first embodiment described above will be explained with reference to FIG. The register 23 is set and makes the status line r valid when a predetermined address is output from the processor and the register selection line k becomes valid. When state line r becomes valid, control circuit 25 executes an atomic cycle. Further, the register 23 is reset by the atomic cycle detector 24 detecting that the signal indicating the atomic cycle output from the processor via the processor control bus a is valid and making the atomic cycle detection line m valid. state line r is invalidated. The processor asserts a signal indicating an atomic cycle and executes the atomic cycle to access the shared bus. Therefore, if the status line r is valid, the control circuit 25 executes the non-divisible cycle even if the signal indicating the non-divisible cycle from the processor is invalid.

Next, the operation of the snoop lock by the processor connected to the first embodiment of the present invention will be explained with reference to FIG. FIG. 2 is a flowchart showing the snoop lock operation of a processor connected to the first embodiment of the present invention, in which (a) shows a snoop lock acquisition operation, and (b) shows a snoop lock release operation.

(a) Snoop Lock Acquisition Operation In step u1, the processor executes an atomic cycle and reads the lock bit. In step u2, the processor writes to the lock bit to put it in the locked state and ends the atomic cycle. In step u3, the processor checks whether the read lock bit is in the locked state, and if the lock bit is in the locked state and the snoop lock has been acquired by another processor (in the case of YES), the processor advances to step u4.

In step u4, the processor reads the lock bit using a normal read. At this time, a cache entry including a lock bit is created in the cache memory of the processor. At step u5, a register is set in the processor's cache memory.

In step u7, the processor checks whether the read lock bit is in the locked state, and if the lock bit is in the locked state and the snoop lock has been acquired by another processor (in the case of YES), the processor executes step u6. Proceed to. In step u6, the processor reads the lock bit using a normal read. In step u7, the processor checks whether the read lock bit is in a locked state,
If the lock bit is in the clear state and the snoop lock is in the released state (in the case of NO), the process proceeds to step u1.

Note that when the snoop lock is released by another processor, the cache entry including the lock bit is invalidated in the processor's cache memory. Processor 2 has performed steps u6 to u up to this point.
7 is repeated to continue reading the lock bit from the cache memory of the processor, and the shared bus is not accessed during this time. After the snoop lock is released by another processor and the cache entry containing the lock bit is invalidated in the processor's cache memory,
Processor 2 reads the lock bit from the shared memory, and the cache entry containing the lock bit is validated in the processor's cache memory.

In step u3, the processor checks whether the lock bit is in the locked state, and if the lock bit is in the clear state and the snoop lock is in the released state, terminating the operation.

(b) Snoop lock release operation The same operation as in the conventional example is performed.

Next, in the tightly coupled multiprocessor system using the first embodiment of the present invention, processors 1 to 1
Figure 3 shows the bus cycles that occur on the shared bus when 4 requests the snoop lock at the same time and a conflict occurs.
This will be explained with reference to. FIG. 3 is a timing chart showing accesses on a shared bus when a snoop lock is executed in a tightly coupled multiprocessor system using the first embodiment of the present invention. In FIG. 3, RE is exclusive read and R is read.

In the initial state, there are no cache entries including lock bits in cache memories 5 to 8 of processors 1 to 4, respectively.

At time t1, processor 1 acquires the right to use the shared bus, starts an atomic cycle, and reads the lock bit by exclusive reading. As a result, the processor 1 obtains the right (ownership) to write to the lock bit, and a cache entry including the lock bit is created in the cache memory 5 of the processor 1. At this time, since there is no cache entry including the lock bit in the cache memory 6 of the processor 2, the cache memory 7 of the processor 3, and the cache memory 8 of the processor 4, the cache memory 6, the cache memory 7, and the cache memory 8 are empty. Do not work.

Processor 1 then writes to the lock bit and ends the atomic cycle. At this time,
The cache entry including the lock bit is validated in the cache memory 5. As a result, processor 1 acquires the snoop lock. And processor 1
begins manipulating shared resources.

At time t2, processor 2 acquires the right to use the shared bus, starts an atomic cycle, and reads the lock bit by exclusive reading. At this time, a cache entry including a lock bit is created in the cache memory 6. Also, at this time, the cache entry including the lock bit in the cache memory 5 is invalidated. Processor 2 then writes to the lock bit to end the atomic cycle. At this time, the cache entry including the lock bit is validated in the cache memory 6. Since processor 1 has already acquired the snoop lock, processor 2 fails to acquire the snoop lock.

At time t3, processor 3 acquires the right to use the shared bus, starts an indivisible cycle, and reads the lock bit by exclusive reading. At this time, a cache entry including a lock bit is created in the cache memory 7. Also, at this time, the cache entry including the lock bit in the cache memory 6 is invalidated. Processor 3 then writes to the lock bit to end the atomic cycle. At this time, the cache entry including the lock bit in the cache memory 7 is validated. Since processor 1 has already acquired the snoop lock, processor 3 fails to acquire the snoop lock.

At time t4, processor 4 now acquires the right to use the shared bus and starts an indivisible cycle.
Read the lock bit using exclusive read. At this time, a cache entry including a lock bit is created in the cache memory 8. Also, at this time, the cache entry including the lock bit in the cache memory 7 is invalidated. Processor 4 then writes to the lock bit to end the atomic cycle. At this time, the cache entry including the lock bit is validated in the cache memory 8. Since processor 1 has already acquired the snoop lock, processor 4
fails to acquire the snoop lock.

Subsequently, processor 4 reads the lock bit from cache memory 8 by normal reading (step u4 in FIG. 2). In the cache memory 8, the cache entry including the lock bit in the locked state is in the valid state, so the processor 4 reads the lock bit from the cache memory 8. Subsequently, the processor 4 sets the register of the cache memory 8 (step u5 in FIG. 2). Further, since the lock bit is in the locked state, the processor 4 proceeds to step u6 at step u7 in FIG. 2, repeats the loop of steps u7 to u8 in FIG. Continue reading the lock bit from .

At time t5, processor 2 acquires the right to use the shared bus and reads the lock bit from the shared memory by normal reading (step u6 in FIG. 2).
. At this time, a cache entry including a lock bit is created in the cache memory 6. Subsequently, the processor 2 sets the register of the cache memory 6. Further, since the lock bit is in the locked state, the processor 2 proceeds to step u6 in step u7 of FIG. 2 until the snoop lock is released.
The loop from ~u7 is repeated to continue reading the lock bit from the cache memory 6.

At time t6, processor 3 acquires the right to use the shared bus and reads the lock bit from the shared memory by normal reading. At this time, a cache entry including a lock bit is created in the cache memory 7. Subsequently, the processor 3 sets the register of the cache memory 7. Subsequently, since the lock bit is in the locked state, the processor 3 proceeds to step u6 at step u7 in FIG. 2, repeats the loop of steps u6 to u7 in FIG. Continue reading bits.

At time t7, when processor 1 finishes operating the shared resource and reads the lock bit to release the snoop lock, the cache entry containing the lock bit on cache memory 5 has already been invalidated at time t2. Therefore, the cache memory 5 causes a miss. To this end, processor 1 starts an atomic cycle and reads the lock bit from the shared memory by exclusive read. At this time, a cache entry including a lock bit is created in the cache memory 5. Also, at this time, cache entries including lock bits are invalidated in cache memory 6, cache memory 7, and cache memory 8.

[0067] Subsequently, processor 1 writes to the lock bit, clears the lock bit, and ends the atomic cycle. As a result, processor 1 releases the snoop lock.

At time t8, since the cache entry including the lock bit on the cache memory 6 has already been invalidated at time 7, the processor 2 repeating the loop of steps u6 to u7 in FIG. When u7 reads the lock bit from the cache memory 6, the cache memory 6 causes a miss. Subsequently, processor 2 acquires the right to use the shared bus and reads the lock bit from the shared memory by normal reading. At this time, a cache entry including a lock bit is created in the cache memory 6. Since the lock bit has already been cleared, the operation of processor 2 proceeds from step u7 of FIG. 2 to step u1.

At time t9, processor 2 begins an atomic cycle and reads the lock bit from shared memory by exclusive read. At this time, a cache entry including a lock bit is created in the cache memory 6. Also, at this time, the registers in the cache memory 6 are reset. Next, processor 2
writes the lock bit to end the atomic cycle. At this time, the cache entry including the lock bit is validated in the cache memory 6. As a result, processor 2 acquires the snoop lock.

Note that the normal reading at time 8, the exclusive reading at time 9, and the writing at time 9 by the processor 2 are performed inseparably, and the shared bus is not released during this time.

At time t10, cache memory 7
Since the cache entry containing the lock bit above has already been invalidated at time 7, steps u6 to u7 in FIG.
When the processor 3 repeating the loop reads the lock bit from the cache memory 7 in step u6 of FIG. 2, the cache memory 7 causes a miss. Subsequently, processor 3 acquires the right to use the shared bus and reads the lock bit from the shared memory. At this time, a cache entry including a lock bit is created in the cache memory 7. Since the lock bit is already in the locked state, the operation of the processor 3 is as shown in step u of FIG.
7, the process advances to step s6, and the loop of steps u6 to u7 in FIG. 2 is repeated until the snoop lock is released, and the lock bit continues to be read from the cache memory 7.

At time 11, since the cache entry containing the lock bit on cache memory 8 has already been invalidated at time 7, processor 4, which is repeating the loop of steps u6 to u7 in FIG. When the lock bit is read from the cache memory 8 in step 4, the cache memory 8 causes a miss. Subsequently, processor 4 acquires the right to use the shared bus and reads the lock bit from the shared memory by a normal read. At this time, a cache entry including a lock bit is created in the cache memory 8. Since the lock bit is already in the locked state, the operation of the processor 4 proceeds from step u7 of FIG. 2 to step u6, repeats the loop of steps u6 to u7 of FIG. Continue reading the lock bit from .

As explained above, the first embodiment includes the register 23, and if a mistake occurs while the register is being set after the snoop lock is released, the control circuit executes an indivisible cycle. In a tightly coupled multiprocessor system using Embodiment 1, when contention occurs on a shared bus among multiple processors, accesses to the shared bus can be reduced compared to when conventional cache memory is used. .

Example 2. The configuration of a second embodiment of the present invention will be described with reference to FIG. 4. FIG. 4 is a block diagram showing a second embodiment of the invention. In FIG. 4, 1 to 12,
14-17 and 19-24 are the same as in Example 1 shown in FIG. 26 is a control circuit connected in place of the control circuit 25 in FIG. 1, and 27 is a comparator connected in place of the comparator 18 in FIG. Note that the control means of the present invention is the control circuit 26 and the comparator 27 in the second embodiment.

Next, the operation of the second embodiment described above will be explained with reference to FIG. The comparator 27 enables the hit determination line f in the case of a hit, based on the result of comparison between the address information in the tag memory 12 and the address to be accessed, and whether the control bit is valid or invalid. In this case, the hit determination line f is invalidated, and based only on the comparison between the address information and the address to be accessed, if they match, that is, the cache data memory 11 is determined to be the target to be accessed. If there is a cache entry containing data with
Tag hit line n is enabled, and if they do not match, tag hit line n is disabled.

When a cache entry including data to be accessed exists in the cache data memory 11 and the tag hit line n is valid, the control circuit 26 controls the tag memory 12 when writing to the shared bus. If the control bit of indicates invalid, valid information is written there. Further, if a cache entry including data to be accessed exists in the cache data memory 11 and the tag hit line n is valid, the control circuit 26 detects exclusive readout of the indivisible cycle by another processor on the shared bus. When the control bit of the tag memory 12 indicates valid, nothing is done; if the control bit of the tag memory 12 indicates invalid, valid information is written to this and the data exists in the cache data memory 11. Validate the cache entry that contains the data that is being accessed.

[0077] If a cache entry containing the data to be accessed exists in the cache data memory 11 and the tag hit line n is valid, the control circuit 26 controls the atomic cycle on the shared bus by other processors. When exclusive read without accompanying is detected, if the control bit of the tag memory 12 indicates valid, invalidation information is written to the control bit of the tag memory 12 to invalidate the cache entry on the cache data memory 11. . Operations other than those described above are the same as in the first embodiment.

Next, in a tightly coupled multiprocessor system using the second embodiment of the present invention, processors 1 to 1
Figure 5 shows the bus cycles that occur on the shared bus when 4 requests the snoop lock at the same time and a conflict occurs.
This will be explained with reference to. FIG. 5 is a timing diagram showing accesses on a shared bus when a snoop lock is executed in a tightly coupled multiprocessor system using a cache memory according to a second embodiment of the present invention. In FIG. 5, RE is exclusive read and R is read.

In the initial state, there are no cache memory entries including lock bits in the cache memories 5 to 8 of the processors 1 to 4, respectively.

At time t1, processor 1 acquires the right to use the shared bus, starts an atomic cycle, and reads the lock bit by exclusive reading. As a result, the processor 1 obtains the right (ownership) to write to the lock bit, and a cache entry including the lock bit is created in the cache memory 5 of the processor 1. At this time, since there is no cache entry including the lock bit in the cache memory 6 of the processor 2, the cache memory 7 of the processor 3, or the cache memory 8 of the processor 4, the cache memory 6, the cache memory 7, and the cache memory 8 are empty. Do not work.

Processor 1 then writes to the lock bit and ends the atomic cycle. This time,
The cache entry including the lock bit is validated in the cache memory 5. As a result, processor 1 acquires the snoop lock. And processor 1
begins manipulating shared resources.

At time t2, processor 2 acquires the right to use the shared bus, starts an atomic cycle, and reads the lock bit by exclusive reading. At this time, a cache entry including the lock bit is created in the cache memory 6, and ownership of the lock bit is transferred to the cache memory 6. Further, at this time, even if the cache memory 5 detects exclusive reading of the indivisible cycle on the shared bus by the processor 2, the cache entry including the lock bit is not invalidated in the cache memory 5. Processor 2 then writes to the lock bit to end the atomic cycle. At this time, the cache entry including the lock bit is validated in the cache memory 6. Since processor 1 has already acquired the snoop lock, processor 2 fails to acquire the snoop lock.

At time t3, processor 3 acquires the right to use the shared bus, starts an indivisible cycle, and reads the lock bit by exclusive reading. At this time, a cache entry including the lock bit is created in the cache memory 7, and ownership of the lock bit is transferred to the cache memory 7. Further, at this time, even if the cache memory 5 and the cache memory 6 detect exclusive reading of the indivisible cycle on the shared bus by the processor 3, the cache entry including the lock bit in the cache memory 5 and the cache memory 6 is not invalidated. Processor 3 then writes to the lock bit to end the atomic cycle. At this time, the cache entry including the lock bit in the cache memory 7 is validated. Since processor 1 has already acquired the snoop lock, processor 3 fails to acquire the snoop lock.

At time t4, processor 4 now acquires the right to use the shared bus and starts an indivisible cycle.
Read the lock bit using exclusive read. At this time, a cache entry including the lock bit is created in the cache memory 8, and ownership of the lock bit is transferred to the cache memory 8. Also, at this time, cache memory 5, cache memory 6, and cache memory 7
Even if processor 4 detects an exclusive read of an indivisible cycle on the shared bus, cache entries containing lock bits in cache memory 5, cache memory 6, and cache memory 7 are not invalidated. Processor 4 then writes to the lock bit to end the atomic cycle. At this time, the cache entry including the lock bit is validated in the cache memory 8. Since processor 1 has already acquired the snoop lock, processor 4 fails to acquire the snoop lock.

Further, processor 2, processor 3, and processor 4 read the lock bit by normal reading (step u4 in FIG. 2). Since the cache entry including the lock bit in the locked state is in the valid state in the cache memory 6, cache memory 7, and cache memory 8, the processor 2, processor 3, and processor 4 are in the cache memory 6, cache memory 7, and cache memory 8, respectively. Read the lock bit from 8.

Processor 2, processor 3, and processor 4 then set the registers of cache memory 6, cache memory 7, and cache memory 8, respectively (step u5 in FIG. 2). Since the lock bit is in the locked state, step u7 of FIG. 2 proceeds to step u6, and processor 2, processor 3, and processor 4 perform step u6 of FIG. 2 until the snoop lock is released.
The loop from ~u7 is repeated to continue reading the lock bits from cache memory 6, cache memory 7, and cache memory 8, respectively.

At time t5, processor 1 finishes manipulating the shared resource and clears the lock bit to release the snoop lock. At this time, the ownership of the lock bit is in the cache memory 8, so the processor 1
First, exclusive read without involving atomic cycles is performed to acquire ownership of the lock bit. At this time, a cache entry including a lock bit is created in the cache memory 5. Subsequently, processor 1 writes to the lock bit to clear the lock bit.

On the other hand, cache memory 6, cache memory 7, and cache memory 8 detect an exclusive read by processor 1 that does not involve an indivisible cycle on the shared bus, and lock bits are set in cache memory 6, cache memory 7, and cache memory 8. The cache entry containing the cache entry is invalidated.

At time t6, since the cache entry including the lock bit on the cache memory 6 has already been invalidated at time t5, steps u6 to u7 in FIG.
The processor 2 repeating the loop reads the lock bit from the cache memory 6 in step u6 of FIG. 2, causing a mistake. Processor 2 then acquires the right to use the shared bus and reads the lock bit from the shared memory by normal reading. At this time, a cache entry including a lock bit is created in the cache memory 6. Since the lock bit has already been cleared, the process proceeds from step u7 in FIG. 2 to step u1.

At time t7, processor 2 starts an atomic cycle and reads the lock bit from the shared memory by exclusive reading. At this time, a cache entry including a lock bit is created in the cache memory 6. Also, at this time, the registers are reset in the cache memory 6, and a cache entry including a lock bit is created. Also, at this time, the cache memory 5, the cache memory 7, and the cache memory 8 detect the exclusive read of the indivisible cycle on the shared bus by the processor 2, and the cache memory 5, the cache memory 7, and the cache memory 8 include the lock bit. Cache entry is enabled.

Subsequently, since the cache entry including the lock bit has been validated in the cache memory 7 and the cache memory 8, the processor 3 and the processor 4 repeating the loop of steps u6 to u7 in FIG.
reads the lock bit from each cache memory 7 and cache memory 8 in step u6 of FIG. Since the lock bit is in the locked state, processor 3 and processor 4 proceed to step u6 at step u7 in FIG. 2, and repeat the loop of steps u6 to u7 in FIG. Continue reading the lock bit from memory 8.

[0092] Processor 2 then writes to the lock bit to acquire a snoop lock and ends the atomic cycle. At this time, the cache entry including the lock bit is validated in the cache memory 6. Processor 2 then begins operating the shared resource.

Note that the normal read at time 6, the exclusive read at time 8, and the write at time 8 by processor 2 are performed inseparably, and the shared bus is not released during this time.

As explained above, the second embodiment includes the register 23, the comparator 27, and the control circuit 26, and performs control when a mistake occurs while the register is set after the snoop lock is released. The circuit executes an atomic cycle. Furthermore, if a cache entry including a lock bit exists and is in an invalid state, the cache entry including the lock bit is enabled when an atomic cycle is written to the shared bus. Furthermore, if a cache entry including a lock bit exists and is in an invalid state, the cache entry including the lock bit is enabled when exclusive reading of an indivisible cycle on the shared bus by another processor is detected. Based on these facts, in the tightly coupled multiprocessor system using the second embodiment, when contention occurs on the shared bus among multiple processors, access to the shared bus is reduced compared to when using the cache memory of the conventional example. can be reduced.

[0095]

Effects of the Invention As explained above, the cache memory according to claim 1 of the present invention is equipped with a register for instructing whether or not to access the shared memory in an atomic cycle, so that it can be used in a tightly coupled multiprocessor. It is possible to reduce the usage rate of the shared bus in the system.

Further, the cache memory according to claim 2 of the present invention includes a register for instructing whether or not access to the shared bus is to be performed in atomic cycles, and when a predetermined access cycle to the shared bus is detected, By providing the control means for changing the corresponding cache entry to a valid state if the corresponding cache entry exists in an invalid state, it is possible to further reduce the usage rate of the shared bus in a tightly coupled multiprocessor system. .

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a flowchart showing a snoop lock operation by a processor connected to the first embodiment of the present invention.

FIG. 3 is a timing chart showing access to a shared bus during a snoop lock operation by a processor connected to the first embodiment of the present invention.

FIG. 4 is a block diagram showing a second embodiment of the invention.

FIG. 5 is a timing chart showing access to a shared bus during a snoop lock operation by a processor connected to the second embodiment of the present invention.

FIG. 6 is a configuration diagram showing a tightly coupled multiprocessor system using a conventional cache memory.

FIG. 7 is a block diagram showing a conventional cache memory.

FIG. 8 is a flowchart showing a snoop lock operation by a processor connected to a conventional cache memory.

FIG. 9 is a timing chart showing access to a shared bus during a snoop lock operation by a processor connected to a conventional example.

[Explanation of symbols]

1 to 4 Processor 5-8 Cache memory 9 Shared memory 10 Shared bus 11 Cache data memory 12 Tag memory 23 Register 24 Indivisible cycle detector 25, 26 Control circuit 18, 27 Comparator

Claims (2)

[Claims] 1. In a tightly coupled multiprocessor system, in a cache memory that is uniquely connected to each of a plurality of processors and connected to a shared memory via a shared bus, access to the shared bus is performed in an atomic cycle. A cache memory characterized by comprising a register for instructing whether or not to perform a cache memory. 2. In a tightly coupled multiprocessor system, in a cache memory that is uniquely connected to each of a plurality of processors and connected to a shared memory via a shared bus, access to the shared bus is performed in an atomic cycle. When a predetermined access cycle is detected to the lock bit on the shared bus and the register that instructs whether or not to perform the operation, if the corresponding cache entry exists in the invalid state, the corresponding cache entry is set to the valid state. A cache memory characterized by comprising a control means for changing the cache memory.