JPH04296951A - Cache memory - Google Patents

Abstract

PURPOSE:To reduce the using rate of a shared bus and to prevent such a case where plural memories success the spin lock at one time for a tight coupling type multiprocessor by providing a means which detects the write of an indivisible cycle from a processor and a control means which invalidates the corresponding entry when the preceding write is detected. CONSTITUTION:A cache data memory 11 stores the entries of data read out of a shared memory 4 by the processors 1A and 1B. When the requests are produced for the spin lock bits which are written into the memory 4 from both processors 1A and 1B, an indivisible cycle write detector 15 detects the indivisible cycle write requests given from the processors 1A and 1B. Then a shared bus access control circuit 17 writes the data into a shared bus, and a control circuit 14 writes the invalid information into a control bit of a cache directory memory 7. Thus the entry of the pin lock bit is invalidated in the memory 11.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] This invention relates to a cache memory that is placed between a main memory device and a processor in order to bridge the difference between the access time and the cycle time between the two. Sometimes it concerns a cache memory that performs an atomic cycle write and invalidates the spinlock bit entry on which the write was performed.

0002

2. Description of the Related Art FIG. 7 is a block diagram showing a tightly coupled multiprocessor system using a conventional cache memory. In the figure, (1A) and (1B) are processors, (2A) is a cache memory connected to processor (1A), (2B) is a cache memory connected to processor (1B), and (4) is a shared memory. , (5) is a synchronization memory. In addition, cache memory (2A)
and (2B), shared memory (4) and synchronization memory (
5) is connected to the shared bus (3). In addition, processors (1A) and (1B) and cache memory (2
Although there are a plurality of A) and (2B), two sets are shown here as examples.

Next, the operation of a tightly coupled multiprocessor system will be explained. In a tightly coupled multiprocessor system, it is necessary to perform exclusive control when using shared resources. The lowest level of exclusive control is called a spinlock. Here, this spinlock will be explained as an example. A spinlock is a device that determines whether or not shared resources in a shared area can be used, depending on the value of a predetermined bit (hereinafter referred to as a spinlock bit) present in the shared area. Specifically, if the spinlock bit is not set, the spinlock is in a released state and shared resources can be used; if it is set, the spinlock is in a locked state and shared resources cannot be used. I can't. Spinlocks are usually busy-wait controlled and executed in atomic cycles. The non-divisible cycle refers to a processor cycle for reliably performing a spin lock, for example, and refers to a cycle that cannot be interrupted while the processor reads, processes, and writes data.

[0004] Here, a specific spinlock operation is shown in FIG.
This will be explained with reference to FIG. FIG. 8 is a state transition diagram when a spin lock is executed using the shared memory (4). The cache memory consistency protocol here is a write-through algorithm, and all writes from processors (1A) and (1B) are performed on the shared bus (3
) shall be output on the top.

In the initial state (state 601), the processors (1A) and (1B) are performing other operations, and the cache memories (2A) and (2B) do not contain spinlock bits (no entries exist). (no), shared memory (4
) shall be in the released state.

[0006] When the processor (1A) requests a spinlock, it executes an indivisible cycle read and reads the spinlock bit from the shared memory (4). At this time, a spinlock bit indicating a release state is entered in the cache memory (2A), and the cache memory (2A)
The spinlock bit entry becomes valid. (State 602) The processor (1A) knows that the spinlock is successful because the spinlock bit is in the released state, and executes an atomic cycle write to set the spinlock bit on the shared memory (4) to the locked state. Make it. At this time, the spinlock bit on the cache memory (1A) is also locked. Note that cache memory (
The spinlock bit entry at 2A) remains valid. (State 603) The processor (1A) that has successfully acquired the spinlock in this way processes the shared data. (State 604)

When the processor (1A) finishes processing the shared data, it performs a normal write operation and writes the spinlock bit on the cache memory (2A) and the shared memory (4).
) to release the spinlock bit on the top. Note that the spinlock bit entry on the cache memory (2A) remains valid. (State 605) After this, the processor (1A) performs other operations. (state 606)

Next, a case will be described in which processors (1A) and (1B) simultaneously request spinlocks from cache memories (2A) and (2B), respectively. The processor (1A) executes an atomic cycle read to read the spinlock bit from the cache memory (2A). The processor (1B) also executes an atomic cycle read to read the spinlock bit from the shared memory (4). In the cache memory (2B), the spinlock bit entry becomes valid. (Status 607
) Processors (1A) and (1B) both know that the spinlock bit is in the released state, determine that the spinlock has been successfully acquired, and execute an atomic cycle write to release the spinlock on the shared memory (4). Lock the bit. (State 608) In this way, the shared memory (4
) to perform a spinlock, a contradiction arises in that multiple processors (1A) and (1B) successfully acquire a spinlock at the same time.

[0009] Conventionally, therefore, spin locking has been performed using a synchronization memory (5). Synchronization memory (5)
If the area is designated as a cache-inhibited area, a situation in which spinlock bits in the released state exist in multiple locations, here, in the cache memory (2A) and the shared memory (4), does not occur.

0010

[Problems to be Solved by the Invention] When performing a spinlock using the conventional cache memories (1A) and (1B), the area of the synchronization memory (5) must be designated as a cache-inhibited area, and software Restrictions on clothing arise. In addition, all access to that area is via the shared bus (3
), which puts pressure on the bandwidth of the shared bus (3). Furthermore, since a spinlock is a busy-wait operation, for example, a processor (1A) that has failed to acquire a spinlock will not be able to acquire a spinlock (1A).
shared memory (
4) continues to be accessed (spinlock request), the shared bus (3) is used in vain, and there is a problem in that it interferes with access by other processors.

[0011] The present invention was made to solve these problems, and it realizes a spin lock in the shared memory, eliminates wasteful access from the processor to the shared memory, and reduces the usage rate of the shared bus. The purpose is to obtain cache memory for

0012

[Means for Solving the Problems] A cache memory according to the present invention includes the following means. [1] Detection means for detecting writing of an indivisible cycle from the processor. [2] A control means for invalidating the entry when writing of the indivisible cycle is detected.

[0013]

In the present invention, the detection means detects writing of an indivisible cycle from the processor. Further, the control means invalidates the entry when writing of the indivisible cycle is detected.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure of a first embodiment of the present invention will be described with reference to FIG. FIG. 1 shows a first embodiment (2A) of the present invention.
It is a block diagram showing A), (2BA). In the figure, (6), (8) and (10) are selectors, which include a processor address bus (1a) and a shared address bus (1a).
3a) is connected. (7) is a cache directory memory connected to the output side of the selector (6). (9) is a comparator connected to the output side of the selector (8) and the output side of the cache directory memory (7). (11) is the selector (10)
This is a cache data memory connected to the output side of the (12) and (13) are transceivers, which are a processor data bus (1c) and a shared data bus (1c), respectively.
3c) is connected to the cache data memory (11). (14) is a control circuit, which is a processor control bus (
1b) and the shared control bus (3b), and the control line (
14a), hit determination line (9a) and control line (14b)
respectively through cache directory memory (7)
, a comparator (9) and a cache data memory (11). (15) is an atomic cycle write detector, which is connected to the processor control bus (1b) via the processor write line (15b) and the processor atomic cycle line (15c), and is connected to the atomic cycle write detection line (15a). It is connected to the control circuit (14) via the control circuit (14). (16) is a buffer connected to the cache directory memory (7) and a generation control bit bus (1
4d) to the control circuit (14). (17
) is a shared bus access control circuit to which a processor control bus (1b) is connected and is connected to a control circuit (14) via a control line (14c). Note that control lines from the control circuit (14) to the selectors (6), (8), and (10) are omitted. In addition, a processor address bus (1a), a processor control bus (1b)
and the processor data bus (1c) is connected to the processor (1A
) and (1B), and the shared address bus (3a)
, a shared control bus (3b) and a shared data bus (3c) are connected to the shared memory (4).

By the way, the detection means of the present invention is the indivisible cycle write detector (15) in the first embodiment.

Next, normal read and write operations in the first embodiment described above will be explained with reference to FIG. The cache data memory (11) includes a processor (
1A) and (1B) read from the shared memory (4) are stored. The cache directory memory (7) has cache directory information indicating the address of an entry in the cache data memory (11), and control bits having valid/invalid information of the entry.

Normal read and write operations according to the write-through algorithm are divided into the following cases. (a) In the case of a read hit, (b) In the case of a write hit, (c) In the case of a read miss, (d) In the case of a write miss, (e) In the case of a write to the shared bus by another processor. (f) if the written data exists in the cache data memory; and (f) in the same case, the written data exists in the cache data memory (11);
This is the case when it does not exist. Note that in the case of reading from the shared bus by another processor, the control circuit (14) does not perform any operation even if the reading operation to the shared bus is detected. Each case will be explained below.

(a) In case of read hit, the control circuit (1
4) selector (6) when detecting a read request from the processor via processor control bus (1b).
, (8) and (10) are connected to the processor address bus (1a
) and further instructs the cache directory memory (7) to read through the control line (14a). As a result, the cache directory memory (7) outputs cache directory information and control bit validity/invalidity information to the comparator (9) in accordance with the processor address output from the selector (6). Comparator (9)
compares the processor address and the cache directory information, determines whether the entry of data D0 on the cache data memory (11) is valid or invalid, and if the entry of data D0 is valid, it is controlled via the hit determination line (9a). The circuit (14) is notified of the hit. Upon receiving the notification, the control circuit (14) controls the transceiver (12).
from the cache data memory (11) to the processor data bus (1c), instructs the cache data memory (11) to read through the control line (14b), and outputs data D0 to the processor data bus (1c). At the same time, the processor is notified through the processor control bus (1b) that data D0 has been output. This data D0 is read by the processor. Once the processor has finished reading, the control circuit (14) closes the transceiver (12) and places the cache directory memory (7) and cache data memory (11) in an inactive state (control) via control lines (14a) and (14b). Circuit (1
No writing or reading is performed until instructions are given from 4).

(b) In case of write hit, the control circuit (14
) is notified of a hit in the same way as in the case of a read hit described above, when it detects a write request from the processor via the processor control bus (1b). The control circuit (14) connects the transceiver (12) from the processor data bus (1c) to the cache data memory (
11) and instructs writing to the cache data memory (11) through the control line (14b). and,
The processor writes data D1 via a processor data bus (1c) and a transceiver (12). When the processor has finished writing, the control circuit (14)
The transceiver (12) is closed and the cache data memory (11) and cache directory memory (7) are rendered inactive. On the other hand, the shared bus access control circuit (17) also detects a write request from the processor through the processor control bus (1b) and writes data D1 from the processor to the shared bus. When writing to the shared bus is completed, the shared bus access control circuit (17) notifies the processor through the processor control bus (1b).

(c) In the case of a read miss In the case of a read hit described above In the same manner as in (a), the cache directory information and the valid/invalid information of the control bits are cached according to the processor address output by the selector (6). It is input from the directory memory (7) to the comparator (9). The comparator (9) compares the processor address and the cache directory information and compares the cache data memory (1
1) Determine the validity/invalidity of the entry of the data D2 above,
If the entry of data D2 is invalid, the hit judgment line (
9a) to notify the control circuit (14) of the mistake. As a result, the control circuit (14) connects the control line (1
4c) to the shared bus access control circuit (17);
At the same time as instructing reading of data D2 from the shared bus, information ( enablement information) to the generation control bit bus (14d) to enable the buffer (16). When reading data D2 from the shared bus, the control circuit (14) opens the transceiver (13) from the shared data bus (3c) toward the cache data memory (11), and at the same time opens the transceiver (12) to read the cache data memory (11). Memory (11)
to the processor data bus (1c), instructs writing of data D2 to the cache data memory (11) through the control line (14b), and further writes the control bit to the cache directory memory (7) through the control line (14a). Instructs to write valid information. As a result, data D2 is written to the cache data memory (11), and the control bit corresponding to data D2 indicates validity.

Next, the control circuit (14) instructs the cache data memory (11) to read data, and sends the data D2 to the processor data bus (12) via the transceiver (12).
1c) and notifies the processor that data D2 has been output. The processor reads data D2. Once this is done, the control circuit (14) closes the transceivers (12) and (13), disables the buffer (16) and connects the cache directory memory (7) and the cache data memory via control lines (14a) and (14b). (11) is made inactive.

(d) In the case of a write miss In the same way as in the case of a write hit (b) described above, the cache directory information and the valid/invalid information of the control bits are checked by the comparator ( 9). A comparator (9) compares the processor address and cache directory information, determines whether the entry of data D3 on the cache data memory (11) is valid or invalid, and if the entry of data D3 is invalid, the hit determination line is (9a) through the control circuit (1
4) Notify of the mistake. On the other hand, the shared bus access control circuit (17) connects the processor control bus (1b
) detects a write request from
Write 3 to the shared bus. After writing is completed, the shared bus access control circuit (17) accesses the processor control bus (
1b) to notify the processor of this.

(e) In the case where another processor writes to the shared bus, the written data D
4 exists in the cache data memory (11). When the control circuit (14) detects a write operation from the shared control bus (3b) to the shared bus, the selector (6), (8)
and (10) to select the shared address bus (3a),
Furthermore, in the same manner as in cases (a) to (d) above, the cache directory information and the valid/invalid information of the control bits are compared from the cache directory memory (7) according to the shared address output from the selector (6). Vessel (9
) is output. The comparator (9) compares the shared address and the cache directory information and determines whether the entry of the data D4 on the cache data memory (11) is valid or invalid. Since the entry of the data D4 is valid,
The control circuit (14) is notified through the hit determination line (9a) that the data D4 written to the shared bus by another processor exists in the cache data memory (11). Upon receiving the notification, the control circuit (14) controls the cache directory memory (14a) through the control line (14a).
7) to an inactive state and cache data memory (11) to an inactive state.
) is outputted to the generation control bit bus (14d) to output the information (invalidation information) for invalidating the data D4 on the buffer (1
6). Then, the control circuit (14) causes invalidation information to be written in the cache directory memory (7) through the control line (14a). Therefore, the entry for data D4 on the cache data memory (11) is invalidated, and the control bit corresponding to data D4 indicates invalidity. When the writing to the cache data memory (7) is completed, the control circuit (14) disables the buffer (16) and deactivates the cache directory memory (7) via the control line (14a).

(f) In the case where another processor writes to the shared bus, the written data D
5 does not exist in the cache data memory (11). When the control circuit (14) detects a write operation to the shared bus from the shared control bus (3b), the selector (6), (8
) and (10) to select the shared address bus (3a), and in the same manner as in the cases (a) to (d) above, cache directory information and The valid/invalid information of the control bits is transferred from the cache directory memory (7) to the comparator (
9). The comparator (9) compares the shared address with the cache directory information, determines whether the entry for data D5 on the cache data memory (11) is valid or invalid, and since the entry for data D5 is invalid, the hit determination line is set. Through (9a), the control circuit (14) is notified that the data D5 written to the shared memory (4) by another processor does not exist in the cache data memory (11). Upon receiving the notification, the control circuit (14) makes the cache directory memory (7) inactive through the control line (14a). In this case, nothing is done to the cache data memory (11) and cache directory memory (7).

The write operation of the indivisible cycle in the first embodiment of the present invention will now be described with reference to FIG. The processor reads the atomic cycle, performs data processing, and then writes the atomic cycle.

When the control circuit (14) detects a write request from the processor from the processor control bus (1b), it instructs the selectors (6), (8) and (10) to select the processor side. Then, it also instructs the cache directory memory (7) to read through the control line (14a). At the same time, the atomic cycle write detector (15) detects that the processor write line (15b) and the processor atomic cycle line (15c) are enabled at the same time, and an atomic cycle write request is issued from the processor. The control circuit (
14). Cache directory memory (7
) outputs cache directory information and control bit validity information to a comparator (9) in accordance with the processor address output from the selector (6). The comparator (9) compares the processor address and the cache directory information, and since the entry of data D6 in the cache data memory (11) is valid, the control circuit (14) detects a hit through the hit determination line (9a). Notify. In this case, since it is after reading an indivisible cycle, there is always a hit. Upon receiving the notification, the control circuit (14) controls the cache directory memory (14) through the control line (14a).
7) is made inactive. Then, the control circuit (14) outputs invalidation information to the generation control bit bus (14d) to enable the buffer (16), and the control circuit (14)
Through a), the cache directory memory (7) is instructed to write invalidation information to the control bits. As a result, invalidation information is written to the control bit of the cache directory memory (7), and the entry of data D6 is invalidated. After this, the control circuit (14) connects the control line (1
4d) disabling the buffer (16);
The cache directory memory (7) is made inactive through the control line (14a). On the other hand, the shared bus access control circuit (17) also detects a write request from the processor and writes data D6 to the shared bus. When writing to the shared bus is completed, the shared bus access control circuit (17) notifies the processor via the processor control bus (1b).

Next, a spinlock operation in a tightly coupled multiprocessor system using the first embodiment of the present invention will be explained with reference to FIGS. 2 and 3. 2 and 3 are state transition diagrams illustrating spinlock operations in a tightly coupled multiprocessor system using the first embodiment of the present invention. Here, the first embodiment described above is realized by cache memories (2AA) and (2BA).

[0028] In the initial state, the processor is performing other operations, and the spinlock bit is stored in the cache memory (2
AA) and (2BA) (the entries are invalid), and the spinlock bit on the shared memory (4) is released. (Status 201)

When the processor (1A) requests a spinlock, the processor (1A) executes an atomic cycle read and transfers data from the shared memory (4) to the cache memory (
2AA) to read the spinlock bit. At this time,
The spinlock bit enters the cache memory (2AA) in a released state, and the entry of the spinlock bit becomes valid in the cache memory (2AA). (state 2
02)

When the processor (1A) learns that the spinlock has been successfully acquired because the spinlock bit is in the released state, it executes an indivisible cycle write and sets the spinlock bit on the shared memory (4) in the locked state. Make it. At the same time, the cache memory (2AA) detects the atomic cycle write from the processor (1A) to the shared memory (4) and invalidates the entry of the spinlock bit. (State 203).

The processor (1A) that has successfully acquired the spinlock in this way processes the shared data. (Status 204)

[0032] After finishing processing the shared data, the processor (1A) releases the spinlock. At this time, since the entry in the cache memory (2AA) has already been invalidated, the processor (1A) again executes the atomic cycle read and reads the spinlock bit from the shared memory (4). And cache memory (
The spinlock bit is entered in the locked state in the cache memory (2AA), and the entry becomes valid in the cache memory (2AA). (State 205)

Processor (1A
) performs an atomic cycle write and the shared memory (4
), the cache memory (2AA) detects the atomic cycle write from the processor (1A) and invalidates the spinlock bit entry. (State 206)

[0034] The processor (1A) then performs other operations. (state 2
07) Next, a case where processors (1A) and (1B) request a spinlock at the same time will be described. At this time, the processor (1B) acquires the shared bus through arbitration on the shared bus, reads the atomic cycle, and reads the spinlock bit from the shared memory (4). The spinlock bit enters the cache memory (2BA) in a released state, and the entry of the spinlock bit in the cache memory (2BA) becomes valid. During this time, the cache memory (2AA) waits until the shared bus is released. (Status 208)

When the processor (1B) learns that the spinlock bit is in the released state, it knows that the spinlock has been successfully acquired, and executes an atomic cycle write to update the spinlock bit on the shared memory (4). Lock state. At this time, the cache memory (2BA) detects writing of the atomic cycle by the processor (1B) and invalidates the spinlock bit entry. (Status 209
)

[0036]The processor (1B) then processes the shared data. During this process, the cache memory (
2AA) acquires the shared bus and reads the spinlock bit from shared memory (4). At this time, the spinlock bit is entered in the cache memory (2AA) in a locked state, and the entry becomes valid in the cache memory (2AA). (state 210)

[0037] The processor (1A) has a cache memory (
Reads the spinlock bit from 2AA), knows that the spinlock has failed because it is in the locked state, and stores the spinlock bit in the cache memory (2AA) until the spinlock succeeds.
Continue reading the spinlock bit from 2AA). Therefore, the processor (1A) never accesses the shared bus. (State 211)

Next, the processor (1B) finishes processing the shared data and releases the spinlock. First, since the entry in the cache memory (2BA) has been invalidated, the processor (1B) again executes an atomic cycle read and reads the spinlock bit from the shared memory (4). The spinlock bit enters the cache memory (2BA) in a locked state, and the cache memory (2BA)
), the entry becomes valid. (state 212)

Next, the processor (1B) executes the atomic cycle write again and releases the spinlock bit on the shared memory (4). At this time, the cache memory (2BA) detects an indivisible cycle write request from the processor (1B) and invalidates the spinlock bit entry. During this time, the cache memory (
2AA) detects the write of an atomic cycle by the processor (1B) and invalidates the entry of the spinlock bit in the cache memory (2AA). (State 21
3)

The processor (1B) performs other operations after releasing the spinlock bit. During this time, the processor (1A) continues to request a spinlock. Since the spinlock bit entry on the cache memory (2AA) is invalidated, the processor (1A) reads the spinlock bit from the shared memory (4). At this time, a spinlock bit in a released state is entered in the cache memory (2AA), and the entry becomes valid. (state 214)

From this point on, the process is the same as from (state 203) to (state 207) described above. (State 215) to (State 219) In the above first embodiment,
A processor with atomic cycle instructions is assumed.

Next, a second embodiment will be described, which is connected to a processor that does not have an indivisible cycle instruction. For processors that do not have atomic cycle instructions, for example, M
One example is R3000 from IPS. In this case, a specific address area is designated as a lock area, and a spinlock is achieved by implementing an atomic cycle on the shared bus by enabling the lock line when accessing that address area, as described below. Realize. The lock line is used, for example, in Intel's Multibus II.

The configuration of a second embodiment of the present invention will now be described with reference to FIG. 4. In this second embodiment, the first
Instead of the selector (6) in the embodiment, a selector (18) with an output latch is connected, and instead of the atomic cycle write detector (15) a lock area access detector (
20) is connected to the control circuit (19) via the lock area access detection line (20a). Further, the control circuit (19) is connected to the shared bus access control circuit (17) via a control line (19a). By the way, the detection means of the present invention is the lock area access detector (20) in the second embodiment.

Next, the operation of the second embodiment described above will be explained with reference to FIG. Since no atomic cycles are generated from the processor connected to the second embodiment, there is no operation related to atomic cycles in the second embodiment, but instead there is an operation related to accessing the lock area. Operations related to access to the lock area include (a) in the case of a read hit to the lock area, (b) in the case of a write hit to the lock area, (c) in the case of a read miss to the lock area, and ( d) There may be a write error in the lock area. Each case will be explained below.

(a) In the case of a read hit to the lock area, the same operation as in the case of a normal read hit is performed.

(b) In the case of a write hit to the lock area When the control circuit (19) detects a write request from the processor from the processor control bus (1b), the control circuit (19) activates the selector (18) with output latch and the selector. (8) and (10
) to select the processor side, and further connects the cache directory memory (7) through the control line (14a).
) to start reading. At the same time, the lock area access detector (20)
Decodes the processor address bus (1a) to detect access to the lock area, and controls that the processor has issued an access request to the lock area by enabling the lock area access detection line (20a). Notify the circuit (19). The cache directory memory (7) outputs cache directory information and control bit validity/invalidity information to the comparator (9) in accordance with the processor address output by the output latch selector (18). The comparator (9) compares the processor address and the cache directory information, determines whether the entry of data D7 on the cache data memory (11) is valid or invalid, and if the entry is valid, the hit determination line (9a)
The control circuit (19) is notified of the hit. Upon receiving the notification, the control circuit (19) connects the control line (14).
Through a), the cache directory memory (7) is rendered inactive. Then, the control circuit (19) outputs invalidation information to the generation control bit bus (14d) to enable the buffer (16), and sends the invalidation information to the control bit to the cache directory memory (7) via the control line (14a). Instructs to write information. As a result, invalidation information is written to the control bit of the cache directory memory (7), and the entry of data D7 is invalidated. After this, the control circuit (19) disables the buffer (16) through the control line (14d) and disables the buffer (16) through the control line (14d).
14b) to inactivate the cache data memory (11). On the other hand, the shared bus access control circuit (17) also detects a write request from the processor and writes data D7 to the shared bus. When writing to the shared bus is completed, the shared bus access control circuit (17) notifies the processor via the processor control bus (1b).

(c) In case of read error to locked area When the control circuit (19) detects a read request from the processor from the processor control bus (1b), the control circuit (19) selects the output latch selector (18) and the selector. Container (8) and (10
) to select the processor side, and further connects the cache directory memory (7) through the control line (14a).
) to start reading. At the same time, the lock area access detector (20)
Decodes the processor address bus (1a) to detect access to the lock area, and controls that the processor has issued an access request to the lock area by enabling the lock area access detection line (20a). Notify the circuit (14). The cache directory memory (7) outputs cache directory information and control bit validity/invalidity information to the comparator (9) in accordance with the processor address output by the output latch selector (18). A comparator (9) compares the processor address and cache directory information, determines whether the entry of data D8 on the cache data memory (11) is valid or invalid, and if the entry of data D8 is invalid, the hit determination line is (9a) through the control circuit (19)
Notify. Upon receiving the notification, the control circuit (19) instructs the shared bus access control circuit (17) to read data from the shared bus in atomic cycles through the control line (19a), and at the same time The control line (18) is instructed to latch the output, and the control line (
14a) and (14b), the cache directory memory (7) and the cache data memory (11) are rendered inactive. The control circuit (19) then controls the generation control bit bus (1
4d) to enable the buffer (16) by outputting enabling information. When reading data D8 from the shared bus, the control circuit (19) transfers the transceiver (13) from the shared data bus (3c) to the cache data memory (11).
and at the same time transfer the transceiver (12) from the cache data memory (11) to the processor data bus (1c).
), instructs the cache data memory (11) to write data D8 through the control line (14b), and further instructs the cache directory memory (7) to write valid information to the control bit through the control line (14a). do.

Next, the control circuit (19) instructs the cache data memory (11) to read data, and sends the data D8 via the transceiver (12) to the processor data bus (
1c) and notifies the processor that data D8 has been output. The processor reads data D8. Once this is done, the control circuit (19) closes the transceivers (12) and (13), disables the buffer (16) and connects the cache directory memory (7) and the cache data memory via control lines (14a) and (14b). (11) is made inactive. Then, if the read data D8 (spin lock bit) indicates a locked state, the control circuit (19) connects the control line (19a
) to instruct the shared bus access control circuit (17) to abort the indivisible cycle, and at the same time instruct the output latched selector (18) to release the latch. Further, if the data D8 indicates a released state, the control circuit (19
) outputs data D8 indicating the locked state to the shared data bus (3c) and instructs the shared bus access control circuit (17) to write an atomic cycle through the control line (19a). At the same time, the control circuit (19) outputs invalidation information to the generation control bit bus (14d), enables the buffer (16), and instructs writing to the cache directory memory (7) through the control line (14a). do. When writing to the cache data memory (7) and the shared bus is completed, the control circuit (19) connects the control line (14) to the cache data memory (7) and the shared bus.
a) makes the cache directory memory (7) inactive, stops outputting to the shared data bus (3c), and connects the shared bus control circuit (17) to the shared bus control circuit (17) through the control line (19a).
to end the indivisible cycle, and instruct the selector with output latch (18) to release the latch.

(d) In the case of a write error in the lock area, the same operation as in the case of a normal write error is performed.

Next, a spinlock operation in a tightly coupled multiprocessor system using the second embodiment of the present invention will be explained with reference to FIGS. 5 and 6. 5 and 6 are state transition diagrams illustrating spinlock operations in a tightly coupled multiprocessor system using the second embodiment of the present invention.

[0051] Here, the second embodiment described above is realized by cache memories (2AB) and (2BB). It is also assumed that processors (1A) and (1B) do not have atomic cycle instructions.

[0052] In the initial state (state 401), processors (1A) and (1B) are performing other operations, and the spin lock bit is used for cache memories (2AB) and (2B).
B), and the spinlock bit on shared memory (4) is in the released state.

When the processor (1A) requests a spinlock, it executes reading to the lock area and reads the spinlock bit from the shared memory (4). At this time,
The cache memory (2AB) executes atomic cycle reads to the shared bus, and
AB), the entry of the spinlock bit indicating the released state becomes valid. (Status 402)

The processor (1A) and the cache memory (2AB) know that the spinlock was successful because the spinlock bit is in the released state. The cache memory (2AB) writes atomic cycles to the spinlock bit on the shared memory to lock the spinlock bit, and at the same time invalidates the entry of the spinlock bit. (Status 403)

[0055] Processor (1A) that succeeded in spinlocking
) handles shared data processing. (Status 404)

00
56] When the processor (1A) finishes processing the shared data, it writes to the lock area and stores it in the shared memory (4).
Release the upper spinlock bit. At this time,
Since the spinlock bit entry has already been disabled in the cache memory (2AB), the processor (1AB)
A) does nothing to the cache memory (2AB). (Status 405)

After releasing the spinlock, the processor (1A) performs other operations. (Status 406)

Next, a case will be described in which processors (1A) and (1B) request a spinlock at the same time. The cache memories (2AB) and (2BB) perform an atomic cycle read on the shared bus and attempt to read the spinlock bit from the shared memory (4). Arbitration on shared bus (3) allows cache memory (2B
B) acquires the shared bus and reads the spinlock bit. At this time, the entry of the spinlock bit indicating the release state becomes valid in the cache memory (2BB). During this time, the cache memory (2AB) waits until the cache memory (2BB) releases the shared bus. (Status 407)

The processor (1B) and the cache memory (2BB) know that the spinlock bit is in the released state, and the cache memory (2BB) performs an atomic cycle write to release the spinlock on the shared memory (4). Locks the bit and disables the spinlock bit entry at the same time. (Status 408)

[0060] The processor (1B) then processes the shared data. During this time, cache memory (2AB)
acquires the shared bus, performs an atomic cycle read on the shared bus, and reads the spinlock bit on the shared memory (4). At this time, cache memory (2
AB), the spinlock bit entry indicating the lock status becomes valid. Now the cache memory (2AB
) ends the atomic cycle for the shared bus. (Status 409)

The processor (1A) and cache memory (2AB) know that the spinlock has failed. The processor (1A) then continues reading the spinlock bit until the spinlock is successfully acquired. At this time, since the spinlock bit entry indicating the lock state is valid in the cache memory (2AB), the processor (1A) reads the spinlock bit from the cache memory (2AB) and cannot access the shared bus. do not have. (Status 410)

Next,
The processor (1B) finishes processing the shared data and writes to the lock area to release the spinlock bit on the shared memory (4). At this time, the cache memory (2BB) does nothing because the spinlock bit entry has already been invalidated. During this time, the cache memory (2AB) detects writing to the shared bus by the processor (1A) and invalidates the spinlock bit entry. (Status 411)

[0063]
After releasing the spinlock, the processor (1B) performs other operations. During this time, processor (1A) continues to request a spinlock. Since the entry of the spinlock bit in the cache memory (2AB) is invalidated, the processor (1A) executes an atomic cycle read to read the spinlock bit from the shared memory (4). At this time, in the cache memory (2AB),
The spinlock bit entry indicating the released state becomes valid. (State 412) From this point on, the process is the same as (state 403) to (state 406). (state 413) to (state 416)

As described above, the first embodiment of the present invention includes a non-divisible cycle write detector (15) for detecting a non-divisible cycle write request from the processor, and the second embodiment of the present invention includes , is equipped with a lock area access detector (20) that detects access to the lock area from the processor, realizes a spin lock in the shared memory (4), and when writing an atomic cycle to the shared bus, the write is Invalidate any data entries made. That is, for example, in a tightly coupled multiprocessor system using the first embodiment, when the processor (1B) performs an atomic cycle write and releases the spinlock, the cache memory (2BA) stores the spinlock bit entry. Therefore, even if the processor (1A) reads the spinlock bit, there is no state in which the entry of the spinlock bit in the released state is valid in the cache memories (2AA) and (2BA) at the same time.
Problems can be prevented. In addition, the processor (1A) that has failed to acquire the spinlock will use the cache memory (2AB) of the processor (1A) until the spinlock is released.
The shared bus will not be accessed in vain because it continues to request a spinlock. Furthermore, the same applies to the tightly coupled multiprocessor system using the second embodiment.

Although the consistency protocols in the first and second embodiments are write-through algorithms, similar effects can be obtained even with other algorithms that have an invalid state.

Furthermore, in the first and second embodiments described above, the case where there is one cache directory memory (7) is shown, but if a plurality of cache directory memories (7) are provided, access to other processors caused by access to the shared bus can be prevented. Disturbance can be reduced.

[0067]

[Effects of the Invention] As explained in detail above, the present invention includes a detection means for detecting writing of an indivisible cycle from a processor, and a control means for invalidating the entry when detecting writing of the indivisible cycle. ,
Since the usage rate of the shared bus can be reduced, access by other processors is not obstructed, and problems in tightly coupled multiprocessors can be solved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a first embodiment of the invention.

FIG. 2 is a state transition diagram illustrating a spinlock operation in a tightly coupled multiprocessor system using the first embodiment of the present invention.

FIG. 3 is a state transition diagram illustrating a spinlock operation in a tightly coupled multiprocessor system using the first embodiment of the present invention.

FIG. 4 is a block diagram showing a second embodiment of the invention.

FIG. 5 is a state transition diagram illustrating a spinlock operation in a tightly coupled multiprocessor system using a second embodiment of the present invention.

FIG. 6 is a state transition diagram illustrating a spinlock operation in a tightly coupled multiprocessor system using a second embodiment of the present invention.

FIG. 7 is a block diagram showing a conventional tightly coupled multiprocessor system.

FIG. 8 is a state transition diagram illustrating spinlock operation in a conventional tightly coupled multiprocessor system.

[Explanation of symbols]

(1A), (1B) Processor (1a)
Processor address bus (1b) Processor control bus (1c) Processor data bus (2AA), (
2BA), (2AB), (2BB) Cache memory (3a) Shared address bus (3b) Shared control bus (3c) Shared data bus (4) Shared memory (6), (8), (10) Selector (7) )
Cache directory memory (9) Comparator (9a) Hit determination line (11) Cache data memory (12), (
13) Transceiver (14), (19)
Control circuits (14a), (14b), (14c), (19a)
Control line (14d) Generation control bit bus (1
5) Indivisible cycle write detector (15a)
Indivisible cycle write detection line (15b)
Processor write line (15c) Processor indivisible cycle line (16) Buffer

Claims (1)

[Claims] 1. A cache memory comprising: detection means for detecting writing of an indivisible cycle from a processor; and control means for invalidating the entry when the write of the indivisible cycle is detected.