JPH04291084A - Memory control system - Google Patents

Abstract

PURPOSE:To simplify an error correction processing by interrupting the transmission of a processing end signal and conducting the correction processing after the completion of reading when the error is detected at the time of burst reading out of a memory. CONSTITUTION:When a burst reading actuation signal is given to a memory control circuit, the burst reading state is brought about and at the same time, a page mode sequencer circuit 4 is actuated. The following operation is directed by an internal actuation/end signal generation circuit based on any of three error discrimination result signals...NOERR (no error), ERR123 (the occurrence of an error which can be corrected with a first to third long words), and ERR4 (the occurrence of an error which can be corrected with a fourth long word)...given by an external error detection circuit corresponding to the operation of the memory control circuit. In the case of NOERR, the burst reading state is completed and an idling state shall be brought about; in the case of, ERR123 or ERR4, a writing access sequence circuit 5 is actuated and the error correction is made.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to a memory system having error detection and correction functions, and is particularly applicable to main memory systems that require high speed in small computer systems such as personal computers and workstations. Regarding memory control methods.

0002

2. Description of the Related Art In a memory system having memory content error detection and correction functions, the invention described in Japanese Patent Publication No. 57-46158 is a known example of a conventional memory control technique for shortening read cycle time. Can be mentioned. Conventionally, as a means of realizing burst reading, the high-speed access mode of the memory is not used, or the high-speed access mode is terminated at the point of error occurrence, or even when the high-speed access mode is used, errors can be detected and corrected for each data item. We take measures to facilitate error correction, such as allowing some margin in the timing.

0003

[Problems to be Solved by the Invention] In the conventional method, when applied to burst reading, error detection and correction are processed for each data item, so reading of the next data is continued until the error determination result of the current data is known. Processing cannot be started, and the high-speed access mode of the memory element cannot be effectively utilized.

SUMMARY OF THE INVENTION An object of the present invention is to provide a memory control method that can effectively utilize the high-speed access mode of a memory element and perform high-speed burst reading in a memory system having an error correction function.

[0005]

[Means for Solving the Problems] In order to achieve the above object, the present invention interrupts sending of a processing end signal when a correctable error is detected during burst reading of a memory using a high-speed access mode. By performing correction processing after completing burst read processing for a specified amount of data and restarting transmission of the processing end signal, the circuit realized is more efficient than the conventional method that detects and corrects errors for each data item. This makes it possible to perform simple and high-speed burst reading. According to the present invention, it is possible to start reading the next data without waiting for the result of error detection for the current data, so a high-speed burst read sequence optimized for the high-speed access mode of the memory element can be performed in one. It becomes possible to design memory control circuits that operate as building blocks.

[0006]

[Operation] The focus of the present invention is to correct errors with a low probability of occurrence by processing them after burst reading of a specified amount of data is completed, optimizing the processing for normal operation, that is, when no errors occur, and improving the performance of the memory system. The aim is to achieve improvement. By providing a means for realizing parallel operations of error detection/correction and next data read without impairing the error detection/correction functions of the memory system, the high-speed access mode of memory elements can be utilized. is possible. In a memory system to which the present invention is applied, the time required for burst reading when a correctable error occurs is not necessarily shorter than in the conventional method, although it depends on the implementation method and the probability of error occurrence. . However, in reality, the probability that correctable errors will regularly occur is extremely low, and the performance of the entire memory system is improved. especially,
When using the high-speed access mode of the memory element, great effects can be obtained by performing error detection/correction and reading next data in parallel.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows the positioning of a memory control circuit to which the present invention is applied in a computer system. This memory control circuit starts operating in response to a memory access request signal based on a signal on the processor bus, and generates an address for the memory element, a control signal, and an access completion signal to the processor bus. An error detection/correction circuit is provided in the data path between the processor bus and the memory element, and when an error occurs during memory reading, the information is sent to the memory control circuit.

FIG. 2 shows a block diagram of a memory control circuit to which the present invention is applied, and FIG. 2 shows a state transition diagram. Here, the specified number of burst read data is 4 long words, 1 long word is 4 bytes, and 1 word is 2 bytes. One long word read/write is one read/write each.
For write access, 1 word and 1 byte writes are both achieved by one read-modify-write access, and burst reads and burst writes are achieved by page mode read/write access, which is a high-speed access mode of the memory element used. ing.

[0009] This memory control circuit starts from an idle state.
From the outside, it is treated as transitioning to six types of states in response to six types of activation signals, but internally it is treated as transitioning to eight types of states depending on the presence or absence of error correction, and there are six states. It consists of a holding circuit 1, six sequencer circuits 2, and an internal start/end signal generation circuit 3 during error correction.

When a burst read activation signal is applied to this memory control circuit, the page mode read sequencer circuit 4 is activated simultaneously with the transition to the burst read state. Three types of error judgment result signals NOER are given from an external error detection circuit according to the operation of the memory control circuit.
Internal activation based on R (no error), ERR123 (correctable error occurred in the 1st to 3rd long word), and ERR4 (correctable error occurred in the 4th long word)
The end signal generation circuit 3 instructs the next operation. NOERR
(No error), exit the burst read state and
Transition to the idle state, and in the case of ERR123 (a correctable error occurs in the first to third long words) and ERR4 (a correctable error occurs in the fourth long word), the write access sequencer circuit 5 is activated and error correction is performed. . If ERR123 (a correctable error occurs in the first to third long words), the page mode read sequencer circuit 4 is restarted after the write access is completed, and if ERR4 (a correctable error occurs in the fourth long word), the write access is restarted. After completion, the burst read state ends and transitions to the idle state. If an uncorrectable error occurs, no internal activation signal is generated, and a signal indicating the occurrence of an uncorrectable error is sent out simultaneously with the processing end signal, and the system transitions to an idle state. In this way, error processing is performed by the internal start/stop signal generation circuit 3, which is realized by a simple combinational circuit.
Since the memory control circuit automatically performs this, the processor does not need to consider the presence or absence of a correctable error.

As described above, in this memory control circuit, an internal start/end signal generation circuit 3 is added using a simple combinational circuit, and an optimized page mode read sequencer circuit 4 and write access sequencer circuit 5 are integrated. The combination realizes error-correctable burst read.

FIG. 4(a) shows the burst read timing of this memory control circuit. The next read process is started without waiting for the error determination result for each long word, making effective use of the page mode read of the memory element. In the conventional method, as shown in FIG. 4B, the next read process cannot be started until the error determination result is known for each long word, and page mode read cannot be used effectively.

In FIG. 4, the time required to obtain a response signal for the fourth long word is T in the present invention.
(a) = 4 (reading time) + (error detection time), and in the conventional method, T(b) = 4 (reading time) + 4 (error detection time)
becomes. Here, if (reading time) = 90ns and 4 (error detection time) = 60ns, T(a) = 420
ns, T(b) = 600ns, and in the present invention, approximately 2/
The burst reading is completed at time 3.

FIG. 5 shows the burst read timing when an error occurs in this memory control circuit. In the conventional method, as shown in FIG. 6, it is possible to insert a correction write process for a long word in which an error has occurred without interrupting the page mode read, but in this embodiment,
It takes time to restart page mode read after correction write access. In the worst case, an error will occur in all 4 longwords, and it will take a considerable amount of time to restart the page mode read four times, but if a computer is in a state where correctable errors occur regularly, The probability that the system will continue to operate is low and is not considered to be a problem in practice. In addition, if there is enough circuit scale, it is possible to store the error longword number and correction write data during page mode read, and perform control to realize error correction by page mode write, or when multiple longword errors occur. However, it is also possible to perform error correction using page mode write.

[0015]

As described above, the present invention provides a high-speed burst read sequence optimized for the high-speed access mode of a memory element, and a memory write sequence that is activated when a correctable error is detected. In combination, it is possible to improve the performance of the entire memory system by optimizing processing for normal operation, that is, when no errors occur, and by simplifying error correction processing, which has a very low probability of actually being necessary. be.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of a memory system that is an embodiment of the present invention.

FIG. 2 is a block diagram of a memory control circuit that is an embodiment of the present invention.

FIG. 3 is a state transition diagram of a memory control circuit that is an embodiment of the present invention.

FIG. 4 is a burst read timing diagram of a memory control circuit according to an embodiment of the present invention.

FIG. 5 is a burst read timing diagram during error correction in a memory control circuit according to an embodiment of the present invention.

FIG. 6 is a burst read timing diagram during error correction in a conventional memory control circuit.

[Explanation of symbols]

1... State holding circuit, 2... Sequencer circuit, 3... Internal start/end signal generation circuit during error correction, 4...
Page mode read sequencer circuit, 5... write access sequencer circuit.

Claims (2)

[Claims] 1. A memory system that starts operation in response to a memory access request from a processor and instructs completion of the access by sending a processing end signal, the system comprising: error detection;
In a memory system with a correction function, if a correctable error is detected during burst read, the transmission of the processing end signal is interrupted, and after the burst read processing for the specified data is completed, the correction processing is performed and the processing end signal is sent. A memory control method that enables high-speed burst data reading using the high-speed access mode of memory elements by restarting the transmission of data. [Claim 2] A combination of a high-speed burst read sequence optimized for a high-speed access mode of a memory element that is activated as a unit, and a memory write sequence that is subsequently activated when a correctable error is detected. A memory control method characterized by performing error correction processing during burst reading.