JPH0426742B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention is directed to a communication control device that uses a high-level data link control procedure and a communication control device that uses a high-level data link control procedure.
This relates to a method for transferring information between two devices.

(Prior art) Conventionally, this technology has been used as one of the methods for transferring information between a communication control device (layer 2 device) and its higher-level device (layer 3 device) that uses high-level data link control procedures (HDLC). , a common memory (hereinafter referred to as shared memory) is provided between both devices,
Some methods perform this by accessing the shared memory from both layer 2 devices and layer 3 devices.

This type of information transfer method is described in Matsunaga et al., "Data Communication LSI with Increasingly Enhanced HDLC Functions (Microprocessor Peripheral LSI Series No. 8)" (Nikkei Electronics, 1984, 10).
8, P131-158). This will be explained below.

Figure 2 shows an example of a system configuration in a conventional information transfer method, where 10 is layer 2.
Devices L2 and 20 are layer 3 devices L3 and 30 are shared memories, and layer 2 device 10 includes a serial data interface (SDI) 11, a processor (CPU) 12, and a read-only memory (ROM).
13 and random access memory (RAM) 14
and a direct memory access controller (DMAC) 15.

Further, FIG. 3 shows an example of the internal configuration of the shared memory 30 and the contents of the register 151 in the DMAC 15. That is, the shared memory 30
is a transmission lookup table (TLOOK: 8 bytes x
8) 31 and a reception lookup table (RLOOK: 8 bytes x 8) 32, and separately from this, a plurality of transmission data buffers 33 and reception data buffers 33 for storing actual transfer information. It has a buffer 34.

The data buffers 33 and 34 are common memories partitioned into fixed sizes, and when transfer information exceeds one data buffer, the subsequent transfer information is stored in another free data buffer 33 or 34. (hereinafter referred to as "chaining") to cope with long transfer information.

When the chain is assembled, the following data buffer 33 (or 34) is displayed as information.
A transfer address indicating the address of the data buffer 33 (or 34) is placed at the end of the data buffer 33 (or 34).

Next, the operation will be described using information transfer from the layer 3 device 20 to the layer 2 device 10 as an example.

(1) The layer 3 device 20 writes transfer information to the transmission data buffer 33 of the shared memory 30. If it is necessary to form a chain, write transfer information one after another while writing the transfer address.

(2) The layer 3 device 20 writes the start address of the data stored in the transmission data buffer 33 and the length of the transmission data in segment 0 of the TLOOK 31, and sets the transmission data buffer ready flag to "1". do.

(3) The layer 3 device 20 notifies the layer 2 device 10 of a transmission request by setting the information frame transmission bit to “1”.

(4) The DMAC 15 in the layer 2 device 10 is
Read the contents of segment 0 of TLOOK31.

(5) After confirming that the transmission data buffer ready flag is "1", the DMAC 15 sends the information frame to the SDI 11 while putting the transfer information in the transmission data buffer 33 into the information field. The data is then sent to a layer 1 device such as a modem that constitutes the physical layer.

(6) The DMAC 15 counts the number of bits of the transfer information, compares it with the length of the transmission data written in segment 0, and checks whether the transfer is complete.

(7) When the information in one transmission data buffer 33 has been transferred, if the transfer is not completed, that is, the length of the transmission data and the count number do not match, the information is concatenated according to the transfer address. The information in the transmitted data buffer 33 is transferred.

(8) In this way, operations (6) and (7) above are repeated until the transfer is completed.

(Problems to be Solved by the Invention) However, in the above information transfer method, since the shared memory is divided into a lookup table section and a data buffer section, 1. In order to transfer information, two places must be accessed. 2. Shared memory cannot be configured with only data buffers, making memory partitioning complicated. 3. Data buffer free space management and table management. There were problems such as the need for double management of segment free space management.

SUMMARY OF THE INVENTION An object of the present invention is to provide an information transfer method that eliminates the above-mentioned problems, reduces the number of operations involved in information transfer, and makes it possible to easily configure and manage a shared memory.

(Means for Solving the Problems) In order to achieve the above object, the present invention provides two devices via a shared memory that can be accessed by the two devices.
In an information transfer method that transfers information between two devices, the shared memory is configured only with a plurality of data buffers that have the same capacity and whose positions are known, and the data buffer that has accumulated transfer information is means for directly transmitting/receiving a transfer request consisting of number information indicated between the two devices, and each data buffer is provided with length information indicating the length of the transfer information and other control information for controlling transfer. A control information area for storing and a transfer information area for storing transfer information are set consecutively.

(Operation) According to the present invention, data storing transfer information
A transfer request can be issued simply by sending number information indicating the buffer, and by reading the contents of the data buffer, length information indicating the length of the transfer information as well as other transfers can be controlled. Control information can be obtained.

(Example) Figure 1 shows an example of the method of the present invention.
In the figure, the same components as in FIG. 2 are denoted by the same reference numerals. That is, 10a is a layer 2 device, 20 is a layer 3 device, and 40 is a shared memory.

The layer 2 device 10a includes a serial data interface (SDI) 11 and a processor (CPU) 1.
2, read-only memory (ROM) 13, random access memory (RAM) 14, and direct memory access controller (DMAC) 1
5, an output port 16, and an input port 17.

The output port 16 and the input port 17 are for directly exchanging commands between the layer 2 device 10a and the layer 3 device 20, and each notify the layer 3 device 20 of the received request RRQ, and the layer 3 device 20 Receive the transmission request SRQ notified by. The received request
The contents of the RRQ and transmission request SRQ are number information indicating a data buffer in which transfer information is stored in the shared memory 40, here a data buffer number to be described later.

FIG. 4 shows the configuration of the shared memory 40.
A plurality of data buffers 4 each having the same capacity and each having a known starting address.
1-0, 41-1, 41-2, ...41-n, and each data buffer 41-0, 41
-1, 41-2, ...41-n have data buffer numbers (DBNO) to distinguish between them.
0, 1, 2,...n are assigned. Further, each data buffer 41-0 to 41-n consists of control information areas 42-0 to 42-n and transfer information areas 43-0 to 43-n.

The control information areas 42-0 to 42-n contain length information L indicating the length of the transfer information, and information such as the link type required when the layer 2 device 10a is performing multiple link processing. Interlayer information, which is information between layers, is stored. Further, transfer information is accumulated in the transfer information areas 43-0 to 43-n. It is assumed that the shared memory 40 does not have any other information areas, tables, etc. for transfer.

Next, the operation will be described using information transfer from the layer 3 device 20 to the layer 2 device 10a as an example.

(1) The layer 3 device 20 has an empty data buffer, for example, the transfer information area 43-0 of 41-0.
Write transfer information to.

(2) Layer 3 device 20 writes the length of transfer information and interlayer information.

(3) The layer 3 device 20 requests the layer 2 device 10a to receive the request via the input port 17.
SRQ, here the DBNO where the transfer information is written
Notify "0".

(4) The layer 2 device 10a receives the notified DBNO.
Read “0” and then write that data buffer 4
The length information L in the control information area 42-0 of 1-0 is read.

(5) While inserting the information in the transfer information area 43-0 of the data buffer 41-0 into the link indicated by the interlayer information or into the information field with the content according to that information, insert the information frame into the SDI1
1 to a layer 1 device (not shown).

(6) At this time, while transmitting, the number of bits of the transmitted information is counted and compared with the length information L to check whether the transfer is completed.

In this way, according to this embodiment, control information such as length information L and interlayer information is stored in the data buffer, and transfer requests are made by directly sending a DBNO, so that the control information such as length information L and interlayer information is does not need to be provided in the shared memory, which simplifies the configuration of the shared memory.Also, the control information can be obtained along with the transfer information just by accessing the data buffer, and only one memory access is required. Data buffer 41-0 to 41-n
The burden of memory management is reduced.

Note that in the embodiment described above, the transfer request is sent via the input (or output) port, but the present invention is not limited to this. Furthermore, the arrangement of the control information area and transfer information area within each data buffer can be arbitrarily determined and is not limited to what is shown in the drawings.

FIG. 5 shows another embodiment of the present invention, in which a page memory is used as the shared memory. That is, in the figure, 50-0 to 50-n are mutually independent page memories (PM), which have the same capacity and each location (in this case, page address) is known. It comes from memory. In addition, each PM50-0 to 50-n
has a number to distinguish each
#0 to #n are assigned. Further, 11 is a serial data interface (SDI), 12 is a processor (CPU), and 18 and 19 are input/output ports (port0, port1). Input/output port 18,
Reference numeral 19 is a combination of the output port and the input port in the above embodiment, and each is connected to two layer 3 devices (not shown). Also,
11a, 12a, 18a, 19a are data buses of each device; data buses 11a, 18a, 19
a are all connected to the data bus 12a. Further, each of the PMs 50-1 to 50-n is controlled by the CPU 12 to switch independently (rotary switch-like) which of the data buses 11a, 12a, 18a, and 19a they operate under. ing.

Next, the operation will be explained using information transfer from layer 3 device to layer 2 device as an example.

(1) The layer 3 device that has received the request for information transfer controls a vacant PM, for example 50-0, to operate under its data bus 18a via the connected input/output port, for example 18. death,
Write the information to be transferred. Further, according to the present invention, length information L and interlayer information are written.

(2) When the layer 3 device finishes writing information,
To the CPU 12 via the input/output port 18,
The transfer request, that is, the page memory number in which the information is written, here "#0", is notified.

(3) When the CPU 12 receives a notification from the input/output port 18, it switches the page memory 50-0 to operate under its own data bus 12a.

(4) The CPU 12 processes the contents of the PM 50-0 according to the present invention.

In this way, the present invention provides a layer 2 device and a layer 3 device.
This is effective not only when the means of transfer between devices is DMAC, but also when other means are used, and it can be configured with only a data buffer.
This is particularly effective in a case where it is appropriate to configure each data buffer only, such as in the transfer method using the page memory.

Up to now, information transfer between layer 2 devices and layer 3 devices has been explained, but layer 2
It is also effective for information transfer between a device below and a layer 3 device or above, or between a layer 3 device or below and a layer 4 device or above, and can be applied to all other devices.

(Effects of the Invention) As explained above, according to the present invention, length information indicating the length of transfer information and other control information for controlling transfer are stored in the data buffer, and transfer requests are directly sent to the data buffer.・Since this is done by sending number information indicating the buffer, there is no need to provide a table in the shared memory as in the past, which simplifies the configuration of the shared memory and reduces the amount of data in the transfer request. Even when there is a large amount of transferred information, that is, when multiple data buffers are used, the burden of sending and receiving it is small, and by simply accessing the data buffer, the length of the transferred information can be changed along with the transferred information. Length information indicating the transfer and other control information for controlling the transfer can be obtained, and only one memory access is required.
Furthermore, all you need to do is manage the data buffer.
This has the advantage of reducing the burden of memory management.

[Brief explanation of drawings]

FIG. 1 is a system configuration diagram showing an embodiment of the information transfer method of the present invention, FIG. 2 is a diagram showing an example of a system configuration using a conventional information transfer method, and FIG. 3 is a diagram showing the configuration of a conventional shared memory. 4 are diagrams showing the configuration of a shared memory according to the present invention, and FIG. 5 is a system configuration diagram showing another embodiment of the present invention. 10a...Layer 2 device, 11...Serial data interface, 12...Processor, 15
...Direct memory access controller, 1
6...Output port, 17...Input port, 20...
...Layer 3 device, 40...Shared memory, 41-0
~41-n...Data buffer, 42-0~4
2-n...Control information area, 43-0 to 43-n
...Transfer information area.

Claims (1)

[Claims] 1. In an information transfer method for transferring information between two devices via a shared memory accessible by the two devices, the shared memory has the same capacity and each location is Consisting only of a plurality of known data buffers, a means is provided for directly transmitting and receiving a transfer request consisting of number information indicating a data buffer that has accumulated transfer information between the two devices, and each of the data buffers Information characterized in that a control information area for storing length information indicating the length of the transfer information and other control information for controlling the transfer, and a transfer information area for storing the transfer information are successively set. Transfer method.