JPH04261589A - Graphic display device - Google Patents

Abstract

PURPOSE:To smoothly display animation pictures without rewriting graphic display data written in an overlay frame buffer. CONSTITUTION:By making the capacity of an overlay frame buffer 3 larger than a display area of a one-screen portion, and also, changing a position of a display area 8 in the overlay frame buffer 3 by an overlay scan address generating circuit 6 independently of a main frame buffer 2, graphic display data written in the overlay frame buffer 5 can be moved smoothly by a scan timing on a screen of a CRT 1.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a graphic display device used in computer systems and the like.

0002

[Prior Art] FIG. 2 shows, for example, an "interface" 19.
October 1984 issue P236-237 (Published by CQ Publishing)
1 is a schematic block diagram of the graphic display device shown in FIG. In the figure, 1 is a CRT, and 2 and 3 are a main frame buffer and an overlay frame buffer, respectively, which store graphic data. 4 is main frame buffer 2 and overlay frame buffer 3
This is a display control circuit that receives a scan data signal 11 which is the output of the , and generates RGB display data 13 after synthesizing the signals. 5 is a scan address generation circuit, which generates scan address 10; A scan timing generation circuit 7 generates a scan timing signal 12.

Next, the operation will be explained. It is assumed that graphic display data has been written into the main frame buffer 2 and overlay frame buffer 3, respectively. In synchronization with the scan timing signal 12 outputted by the scan timing generation circuit 7 for displaying on the CRT 1, the scan address generation circuit 5 generates a scan address signal 10 and supplies it to the main frame buffer 2 and overlay frame buffer 3. The main frame buffer 2 and the overlay frame buffer 3 output a scan data signal 11 corresponding to the scan address signal 10, which is input to the display control circuit 4. The display control circuit 4 synthesizes the scan data signals 11, performs processing such as display color conversion, and then generates RGB display data 13. RGB display data 13 is input to CRT1,
On RT1, the graphic display data written to the main frame buffer 2 and the graphic display data written to the overlay frame buffer 3 are displayed in a superimposed manner.

0004

[Problems to be Solved by the Invention] Conventional graphic display devices are configured as described above, so when displaying moving images such as animation, it is necessary to convert graphic display data in the main frame buffer or overlay frame buffer into motion. The video must be rewritten accordingly, and as this process takes time, the rewriting cycle becomes long, making it difficult to display videos smoothly.

[0005] The present invention was made to solve the above-mentioned problems, and its purpose is to provide a graphic display device that can display smooth moving images without rewriting the graphic display data in the frame buffer. do.

[0006]

[Means for Solving the Problems] A graphic display device according to the present invention provides an overlay scan address that changes the position of a display area in an overlay frame buffer having an area larger than one screen, independently of the main frame buffer. It is equipped with a generating circuit.

[0007]

[Operation] The overlay scan address generation circuit of the present invention can move the display area in the overlay frame buffer independently of the main frame buffer in response to commands from the host. Graphic display data can be moved smoothly on a CRT screen.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG. In the figure, parts that are the same as or corresponding to those in FIG. 2 are designated by the same reference numerals. In FIG. 1, the overlay frame buffer 3 has a size larger than one screen of the CRT 1. Overlay scan address generation circuit 6 generates scan address signal 10 corresponding to display area 8 in overlay frame buffer 3 based on display area control signal 9 .

Next, the operation will be explained. When the graphic display data written in the overlay frame buffer 3 is moved on the CRT 1, it is executed by controlling the overlay scan address generation circuit 6 using the display area control signal 9. The overlay scan address generation circuit 6 generates the scan address signal 10 for the overlay frame buffer 3 independently of the scan address signal 10 for the main frame buffer 2 according to the instructions, and moves the display area 8 in the overlay frame buffer 3. can be done. As a result, the graphic display data in the overlay frame buffer 3 is displayed on the CRT 1 with the graphic display data in the main frame buffer 2 as the background as if it had been moved. Since the display area 8 of the overlay frame buffer 3 can be moved in scan synchronization, smooth video display can be achieved.

[0010] In the above embodiment, a case has been described in which only the capacity of the overlay frame buffer 3 is increased and the display area is changed, but the capacity of the main frame buffer 2 can also be similarly expanded and the display area changed. The main frame buffer 2 may be configured so that the graphic display data in the main frame buffer 2 can be displayed as a moving image.

[0011]

As described above, according to the present invention, the display area in the overlay frame buffer can be changed by the overlay scan address generation circuit. This has the effect of smoothly displaying videos of graphic display data in the overlay frame buffer.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram of a graphic display device according to an embodiment of the present invention.

FIG. 2 is a schematic block diagram of a conventional graphics display device.

[Explanation of symbols]

1 CRT 2 Main frame buffer 3 Overlay frame buffer 4 Display control circuit 5 Scan address generation circuit 6 Overlay scan address generation circuit 7
Scan timing generation circuit 8 Display area 9 Display area control signal 10 Scan address signal 11 Scan data signal 12 Scan timing signal 13 RGB display data

Claims (1)

[Claims] 1. In a graphic display device that reads graphic display data written in a main frame buffer and an overlay frame buffer at scan timing, synthesizes the data in a display control circuit, and outputs the data to a CRT, the overlay frame buffer is used for one screen. 1. A graphic display device comprising an overlay scan address generation circuit that is larger than the display area of the main frame buffer and that can change the display area independently of the display area of the main frame buffer.