JPH04259179A - Video signal recording method - Google Patents

Abstract

PURPOSE:To easily reproduce a video signal without increasing the circuit scale of a subordinate system when a recording medium with a video signal recorded in a host system using a sampling clock with a high frequency is reproduced in the subordinate system using a sampling clock of a low frequency. CONSTITUTION:A camera section 10 picks up an object to form a picture data whose sampling frequency is 6fsc. A still picture signal processing section 30 applies interpolation processing to a picture data whose sampling frequency is 6fsc to generate a picture data whose sampling frequency is 4fsc. Simultaneously, the section 30 generates a 6fsc reproduction data to reproduce the picture data whose sampling frequency is 6fsc from the picture data whose sampling frequency is 4fsc. A head section 40 records the picture data whose sampling frequency is 4fsc and the reproduced picture data whose sampling frequency is 6fsc onto a magnetic tape 1. Thus, the compatibility in the recording medium between the host system and the subordinate system is ensured.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal recording method, and more particularly, to a video signal recording method for recording still images as digital video signals in a so-called PCM audio area of a magnetic tape used in a so-called 8 mm video tape recorder. .

0002

2. Description of the Related Art Apparatuses for recording video signals on a recording medium, such as a magnetic recording medium, include a so-called electronic still camera that uses a so-called still video floppy disk, and a so-called camera-integrated 8mm video tape recorder (hereinafter referred to as "camera-integrated video tape recorder" that uses, for example, a magnetic tape). A camera-integrated 8mm VTR) is known.

Specifically, for example, a camera-integrated 8mmV
In TR, a magnetic tape is wound around a so-called rotating head drum at an angle of 211 degrees, and a pair of heads (hereinafter referred to as rotating heads) spaced apart by 180 degrees scans the magnetic tape helically, as shown in Figure 14. Then, a diagonal track 151 is formed on the magnetic tape 150. and 180 of the rotating head drum of each track 151.
In the video region 152 corresponding to the frequency, a luminance signal is FM-modulated, a carrier color signal is converted to a low frequency, an audio signal is FM-modulated, and a tracking signal for tracking servo, for example, a so-called ATF (Automatic Tr.
(ack finding) is frequency-multiplexed and recorded together with a pilot signal for control. In addition, in the PCM audio area 153 corresponding to approximately 30 degrees of the remaining rotating head drum of each track 151, a nonlinear quantized 8-bit/sample digital audio signal (hereinafter referred to as PCM audio signal) is After being subjected to so-called cross-interleave code processing for correction, a synchronization signal, parity, ID, etc. are added and recorded. In addition, magnetic tape 150
A cue track 154 and an audio track 155 are formed on both sides of the track by scanning the fixed heads respectively. In the cue track 154, for example, a cue signal used for the address or beginning of the recorded content is recorded, and in the audio track 155, for example, an after-recording (af
Audio signals for ter recording) are recorded.

[0004] Furthermore, as disclosed in, for example, Japanese Patent Laid-Open No. 164383/1983, in order to display (superimpose) the title, cast, explanation, etc. on the moving image recorded in the video area 152. , a technique is known in which still images such as text information are photographed and recorded (dubbed) in the PCM audio area 153.

[0005]

By the way, the above-mentioned electronic still camera is generally known as a device for recording still images, but the above-mentioned camera-integrated 8mm VTR is
It is conceivable that the present invention be used as a video signal recording and reproducing device that records still images as digital video signals in the PCM audio area.

In this case, in order to obtain a high-resolution still image, it is necessary to use, for example, a CCD image sensor (hereinafter referred to as CCD) with a large number of optical/electrical conversion elements, and to increase the frequency of the so-called sampling clock. Such devices (hereinafter referred to as upper system) are generally expensive. In other words, for example, a relatively inexpensive 8mmV camera integrated
In a TR (hereinafter referred to as a lower system), a CCD with a small number of optical/electric conversion elements, that is, a sampling clock with a low frequency is used.

As a result, a problem arises in magnetic tape compatibility between an upper system that uses a high frequency sampling clock and a lower system that uses a low frequency sampling clock. In other words, in order to make a magnetic tape recorded by a higher-level system playable by a lower-level system, the lower-level system had to perform interpolation processing to form image data with a low-frequency sampling clock and play it back. . Specifically, for example, FIG.
As shown in , the pixel data of the upper system and the lower system are respectively ai and bi, and the frequencies of the sampling clocks of the upper system and the lower system are 6 times (hereinafter referred to as 6fSC) and 4 times (hereinafter referred to as 6fSC) the so-called subcarrier, respectively.
(hereinafter referred to as 4fSC), for example, pixel data b2 in the lower system can be determined by the following formula. b2 = (a2 + a3 )/2 or b2 = (a1 +3a2 +3a3 +a4)/8

[0008] Therefore, a signal processing circuit and memory for performing the above-described interpolation processing are required in the lower system, resulting in an increase in the number of parts in the lower system and an increase in cost.

The present invention has been made in view of the above circumstances, and is intended to reproduce a recording medium on which a video signal is recorded by a higher-order system using a high-frequency sampling clock by a lower-order system using a low-frequency sampling clock. An object of the present invention is to provide a video signal recording method that allows video signals to be easily reproduced without increasing the circuit scale of a lower-order system.

0010

[Means for Solving the Problems] In order to solve the above problems, in the present invention, a video signal is sampled by a first sampling clock to form first image data, and the frequency of the first sampling clock is The second image data of the second sampling clock having a lower frequency is formed by interpolating the first image data, and the formed second image data is used to generate the first image data.
The present invention is characterized in that third image data for reproducing the image data of is formed from the first image data, and the second image data and the third image data are recorded on a recording medium.

[0011]

[Operation] In the video signal recording method according to the present invention, the video signal is sampled by the first sampling clock to form the first image data, and the second image data of the second sampling clock is used as the first image data. Third image data is formed by interpolating the data, and third image data for reproducing the first image data using the second image data is formed from the first image data. 2
image data and third image data are recorded on a recording medium.

[0012] When reproducing the recording medium on which the video signal is recorded as described above in a lower system using the second sampling clock, the video signal can be easily reproduced by reproducing only the second pixel data. to be played.

[0013] Furthermore, when reproducing a recording medium on which a video signal is recorded as described above in a host system using the first sampling clock, the first image is derived from the second image data and the third image data. To reproduce data and reproduce a video signal.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the video signal recording method according to the present invention will be described below with reference to the drawings. In this embodiment, the present invention is applied to a so-called camera-integrated 8mm VTR (hereinafter simply a VTR).
FIG. 1 is a block circuit diagram showing the circuit configuration of this VTR.

[0015] This VTR is a device (
(hereinafter referred to as the upper system), and as shown in Figure 1,
A camera unit 10 that converts an imaging signal into a digital video signal using a sampling clock SCK1 and performs signal processing such as so-called knee processing and gamma processing, a video video signal processing unit 20 that processes a video signal of a video, and the above-mentioned Digital video signal of sampling clock SCK1 (
(hereinafter referred to as a 6fSC video signal) to a frequency of 4fSC
A still image video signal processing unit 30 that forms a digital video signal (hereinafter referred to as a 4fSC video signal) of sampling clock SCK2 by interpolation processing, and an analog video signal from the moving image signal processing unit 20 and the still image video signal processing unit a head unit 40 for time-division multiplexing digital video signals from the unit 30 and recording them in a so-called video area and a so-called PCM audio area of the magnetic tape 1, respectively, and reproducing a reproduced RF signal; the moving image signal processing unit 20;
It is composed of a control section 50 that controls the still image video signal processing section 30 and the like.

The camera unit 10 has a CCD image sensor (hereinafter referred to as CCD) 11, and samples an image signal from the CCD 11 using a sampling clock SCK1, and also uses a so-called AGC (Automatic Ga
an analog/digital (hereinafter referred to as A/D) converter 13 that converts the sampled video signal from the S/H & AGC circuit 12 into a digital signal; The camera processing circuit 14 is configured to perform signal processing such as knee and gamma processing on the digital video signal as described above.

The moving video signal processing section 20 converts the digital video signal from the camera section 10 into an analog video signal and supplies it to the head section 40, and also converts the reproduced RF signal from the head section 40 into a so-called so-called analog video signal. It is designed to play back analog video signals that comply with the NTSC system. The moving image signal processing section 20 includes a video RAM 22 that sequentially stores the image signals from the camera process circuit 14 or the head section 40, and a video RAM 22 that sequentially stores the image signals from the camera process circuit 14 or the head section 40, and an image read out from the video RAM 22 based on the address from the control section 50. In addition to converting the signal into a video signal compliant with the NTSC system, the luminance signal is converted to FM using a predetermined carrier wave.
After modulating and converting the carrier color signal to a low frequency, frequency multiplexing (hereinafter, this frequency multiplexed signal is referred to as video data) is supplied to the head section 40, and conversely, a video signal is reproduced from the video data. a process circuit 21 and the video process circuit 21 or the still image video signal processing section 3;
A digital/analog (hereinafter referred to as D/A) converter 23 that converts a video signal (digital signal) compliant with the NTSC system supplied from 0 through a changeover switch 27 into an analog signal, and a The video data is converted into an analog video signal and sent to the head section 4.
0, and an A/D converter 25 that converts an analog video signal obtained as a reproduced RF signal from the head section 40 into moving image data.

The still image video signal processing unit 30 forms a 4fSC video signal by interpolating the 6fSC video signal from the camera unit 10, and also forms a 4fSC video signal.
Image data for reproducing a 6fSC video signal (hereinafter referred to as 6fSC reproduction data) is formed from the SC video signal, and these 4fSC video signals and 6fSC reproduction data are supplied to the head unit 40, and conversely, the head Part 4
The 4fSC video signal obtained from the reproduced RF signal of 0 and 6
A 6fSC video signal is reproduced using fSC reproduction data. This still image video signal processing section 30 is connected to the camera process circuit 14 or the head section 4.
6fSC video signal from 0 to 1 field or 1
A video RAM 32 that stores frames, and a video RAM 32 that stores frames.
The 6fSC video signal read from M32 is interpolated to form a 4fSC video signal and 6fSC reproduction data, and if necessary, a predetermined data compression process is performed (
(Hereinafter, this compressed video signal will be referred to as compressed data), and conversely, if necessary, data decompression processing is applied to the compressed data to convert the 4fSC video signal and 6fSC reproduction data into 6fSC
Still image video processing circuit 31 that reproduces the video signal of C
, a RAM 34 that temporarily stores the compressed data, and the R
A synchronization signal, an error correction code, an identification code (hereinafter referred to as ID) for identifying the 4fSC video signal from the control unit 50 and the 6fSC reproduction data, etc. are added to the compressed data read from the AM34 (hereinafter referred to as ID). Compressed data to which an ID, etc. is added is referred to as still image data), and conversely, the still image data is subjected to error correction processing and supplied to the RAM 34, and the ID is detected from the still image data and supplied to the control unit 50. It is composed of a PCM process circuit 33.

The head section 40 receives an analog video signal (an analog video signal obtained by converting video data) from the moving image signal processing section 20 and a digital video signal (still image data) from the still image signal processing section 30. Time-division multiplexing is performed and recorded in the video area and PCM audio area of the magnetic tape 1, and the analog video signal and digital video signal are reproduced from the reproduced RF signal to be processed by the moving video signal processing unit 20 and the still image video signal processing unit 20. 30 respectively. This head section 40 is
A MUX 41 that time-division multiplexes the analog video signal from the moving video signal processing section 20 and still image data from the still image video signal processing section 30, and an amplifier 43 that amplifies the time-division multiplexed recording signal from the MUX 41. , an amplifier 44 that amplifies the reproduced RF signal, and the amplifier 43 and the amplifier 44.
a changeover switch 42 for switching between recording and reproduction, and a rotary head 45 that records signals on the magnetic tape 1 based on excitation current from an amplifier 43, reproduces reproduced RF signals, and supplies the reproduced RF signals to the amplifier 44. configured.

The control unit 50 includes a function control circuit 51 for setting various operation modes of the host system, such as still image shooting/playback mode, video shooting/playback mode, etc.; 51 and the ID from the PCM process circuit 33.
ID that identifies the fSC video signal and 6fSC reproduction data
The memory controller 53 includes a system controller 52 that supplies the PCM process circuit 33 with the PCM process circuit 33, and a memory controller 53 that controls the addresses of the video RAMs 22, 32, etc. under the control of the system controller 52.

The magnetic tape 1 is, for example, as shown in FIG.
This tape has the same tape format as the magnetic tape 150 shown in FIG. That is, a track formed diagonally on the magnetic tape 1 by the helical scanning of the rotary head 45 is divided into a video area and a PCM audio area, a moving image is recorded as an analog video signal in the video area, and a still image is recorded in the PCM audio area. is now recorded as a digital video signal.

Next, the operation of the host system having the above configuration will be explained. This upper system is
The video signal of a moving image is recorded as an analog signal in the video area, the video signal of a still image is recorded as a digital signal in the PCM audio area, and the recorded video signal of the moving image and the video signal of the still image are played back. ing. Furthermore, the still image video signal can be converted into a digital signal and sent to a PC.
When recording in the M audio area, a video tape recorder (hereinafter referred to as a lower system) that uses a sampling clock SCK2 with a frequency of 4fSC can easily record video signals of still images without performing signal processing such as interpolation processing. The 6fSC video signal is interpolated to form a 4fSC video signal so that it can be played back.
The video signals and the like are recorded in the PCM audio area. Also, during playback, the recorded 4fS
A still image video signal is reproduced by reproducing a 6fSC video signal from a C video signal or the like.

For example, in a still image shooting mode in which a still image video signal taken by the camera section 10 is recorded in the PCM audio area of the magnetic tape 1, a 6fSC video signal is interpolated to form a 4fSC video signal. At the same time, 6fSC reproduction data necessary to reproduce a 6fSC video signal from this 4fSC video signal is formed, and these 4fSC video signals are
The SC video signal and 6fSC reproduction data are recorded in the PCM audio area of the magnetic tape 1.

Specifically, when the function control circuit 51 is set to a still image shooting mode, the system controller 52 detects a control signal corresponding to the setting and operates each part in the still image shooting mode. Control as follows. Then, when a shutter (not shown) is operated, a shutter signal sent from the shutter via the terminal 54 is detected, and the still image video signal processing section 30 outputs a shutter signal to the camera section 11.
Signal processing is performed on one frame or one field of the video signal photographed at 0, and the processed signal is recorded in the PCM audio area of the magnetic tape 1 via the head section 40.

That is, the imaging signal from the CCD 11 is
After being converted into a 6fSC video signal in the S/H&AGC circuit 12, A/D converter 13, and camera processing circuit 14, signal processing such as knee and gamma processing is performed. The video signal subjected to this signal processing is supplied to a video processing circuit 21 and a still image video processing circuit 31.

The video signal from the camera process circuit 14 is sent to the video R via a still image video process circuit 31.
Supplied to AM32. The video RAM 32 sequentially stores one field or one frame of the video signal according to a write address synchronized with the line sequential scanning of the CCD 11 from the memory controller 53, and then synchronizes with data compression processing etc. also from the memory controller 53. Based on the read address, the video signals are sequentially read out and supplied to the still image video processing circuit 31.

The still image video processing circuit 31 performs interpolation processing on sequentially read out video signals, that is, 6fSC video signals to form 4fSC video signals, and
In addition to forming the 6fSC reproduction data necessary to reproduce the video signal, data compression processing is performed as necessary,
This compressed data is sent to the RA via the PCM process circuit 33.
Supply to M34. Then, the RAM 34 temporarily stores this compressed data.

The PCM process circuit 33 adds a synchronization signal, an error correction code, and an ID to identify the 4fSC video signal and 6fSC reproduction data cm,n supplied from the system controller 52 to the compressed data read out from the RAM 34 in a predetermined order. is added to generate still image data, and this still image data is supplied to the MUX 41.

On the other hand, the video processing circuit 21 converts the video signal from the camera processing circuit 14 into a video signal conforming to, for example, the NTSC system, and supplies it to the D/A converter 23 via the changeover switch 27. The D/A converter 23 is
A video signal (digital signal) conforming to the NTSC system is converted into an analog signal and sent to, for example, a monitor receiver via a terminal 26. As a result, the image being captured can be monitored. The video process circuit 21 also receives a luminance signal from the camera process circuit 14 as needed, for example, when recording a video signal of a moving image shot while recording a video signal of a still image in the video area. and the carrier color signal are frequency-multiplexed to generate moving image data, and this moving image data is supplied to the D/A converter 24. The D/A converter 24 converts the video data into an analog video signal and converts the video data into an analog video signal.
Supply to UX41.

The MUX 41 receives a moving image video signal from the D/A converter 24, ie, an analog video signal obtained by converting the above-mentioned moving image data into an analog signal, and a still image video signal from the PCM process circuit 33, ie, the above-mentioned analog video signal. Still image data is time-division multiplexed, and a changeover switch 42 and an amplifier 43
is supplied to the rotary head 45 via the rotary head 45. As a result, still images are recorded in tens to hundreds of tracks in the PCM audio area of the magnetic tape 1 as a 4fSC video signal and 6fSC reproduction data together with an ID that identifies the 4fSC video signal and 6fSC reproduction data. Further, if necessary, an analog video signal of a moving image shot while recording a video signal of a still image is recorded in a corresponding track of the video area. Note that the number of tracks required to record one still image depends on the data compression rate. Further, when a still image is recorded in the PCM audio area and nothing is recorded in the video area, the operation of the moving image signal processing section 20 is stopped.

Here, the above-mentioned interpolation process performed by the still image video processing circuit 31, that is, the 4fSC video signal and the 6fSC video signal
A specific example of forming fSC reproduction data will be described.

Note that the number of pixels per frame of the video signal supplied from the camera process circuit 14, that is, the 6fSC video signal, is, for example, 115 as shown in FIG.
2 x 484 (sample x line), each pixel data is ai,j (i = 1 to 484; line number is indicated,
j=1 to 1152 (indicates the order on the line). In addition, the number of pixels per frame of a 4fSC video signal is, for example, 768 x 484 (as shown in Figure 3).
sample x line), and each pixel data is bp, q (
p=1-484; Indicates line number, q=1-76
8 ; indicates the order on the line). In addition, the 6fSC reproduction data is cm,n (m=1 to 484
; represents the line number; n = 1 to 384 ; represents the order on the line).

[0033] In the first specific example, pixel data bp,q of a 4fSC video signal is interpolated with pixel data ai,j of a 6fSC video signal, so that, for example, in the spatial arrangement of the 6fSC video signal, the corresponding Pixel data ai at position
, j exists, it is taken as its pixel data ai,j, and when it does not exist, it is obtained by simply averaging the pixel data ai,j adjacent to the corresponding position. Further, pixel data ai,3k (m=i, n=k, k is an integer) is used for the 6fSC reproduction data cm,n.

That is, for example, the pixel data ai of 1152 samples in each line shown in FIG. 4A (note that the figure only shows the pixel data of the first line)
, j, as shown in FIG. 4B, the pixel data bp,q of the 4fSC video signal and the 6fSC reproduction data cm
, n using the following formula, as shown in FIG. 4C,
Pixel data bp,q is sequentially arranged from the beginning of each line, and then 6fSC reproduction data cm,n, that is, pixel data ai,3k, is sequentially arranged on each line. bp, 2k-1=ai, 3k-2 bp, 2k = (ai, 3k-1+ai, 3k)/2
cm,k =ai,3k (p=m=i, k is an integer)

At this time, the pixel data ai,j of the 6fSC video signal is composed of these pixel data bp,q and 6f
It can be reproduced from the SC reproduction data cm,n using the following formula.

In the second specific example, as in the first specific example described above, the pixel data bp,q of the 4fSC video signal is
For example, in the spatial arrangement of the 6fSC video signal by interpolating the pixel data ai,j of the 6fSC video signal,
When pixel data ai,j exists at the corresponding position, that pixel data ai,j is used, and when it does not exist, the pixel data ai,j adjacent to the corresponding position are obtained by simple averaging. In addition, pixel data ai, which is obtained by simply averaging the 6fSC reproduction data cm,n,
It is obtained by the following formula using j.

That is, for example, using 1152 samples of pixel data ai,j in each line shown in FIG. 5A, as shown in FIG. 5B, the pixel data bp,q of the 4fSC video signal and the 6fSC reproduction data cm,n are calculated. After finding it using the following formula, as shown in FIG. 5C, the formed pixel data bp,q are sequentially arranged from the beginning of each line,
Subsequently, 6fSC reproduction data cm,n are sequentially arranged on each line. bp, 2k-1=ai, 3k-2 bp, 2k = (ai, 3k-1+ai, 3k)/2
cm, k = (ai, 3k-1-ai, 3k)/2
(p=m=i, k is an integer)

At this time, the pixel data ai,j of the 6fSC video signal is composed of these pixel data bp,q and 6f
It can be reproduced from the SC reproduction data cm,n using the following formula. ai, 3k-2=bp, 2k-1
ai, 3k-1=bp, 2k+cm, k
=(ai, 3k-1+ai, 3k
)/2+(ai, 3k-1-ai, 3k)/2
ai, 3k = bp, 2k-cm, k
=(ai, 3k-1+ai, 3k
)/2-(ai, 3k-1-ai, 3k)/2
(p=m=i, k is an integer. The above three equations are called the second equation.)

[0039] The third specific example is
6fSC using the strong correlation of video signals in space and time
So-called sub-sampling is performed to thin out the pixel data ai,j of the video signal.
After applying g), the pixel data bp of the 4fSC video signal
, q are interpolated with the pixel data ai,j of the thinned out 6fSC video signal, and for example, in the spatial arrangement of the 6fSC video signal, a weighted average of a plurality of pixel data ai,j near the corresponding position is calculated. This is how you can get it. In addition, the 6fSC reproduction data cm,n is
This is obtained by using the pixel data ai,j used in the weighted average according to the following formula.

That is, for example, the pixel data ai,j of 1152 samples in each line shown in FIG. 6A (the figure only shows pixel data of the first and second lines) is shown in FIG. 6B. , every other line is thinned out at different positions between adjacent lines (the data to be thinned out is indicated by x). Next, using the remaining pixel data ai,j, as shown in FIG. 6C, the pixel data bp,q of the 4fSC video signal and the 6fSC reproduction data cm,n are calculated by the following formula, and then as shown in FIG. 6D. The formed pixel data bp,q are sequentially arranged from the beginning of each line, and then the 6fSC reproduction data cm,n is sequentially arranged on each line. For odd lines (p and m are odd numbers), for even lines (p and m are even numbers),

At this time, the pixel data ai,j of the thinned out 6fSC video signal is composed of these pixel data bp,q and 6fS
It can be reproduced from the C reproduction data cm,n using the following formula. For odd lines (p and m are odd numbers), a
i, 1 = bp, 1 ai, 6k+1
=bp, 4k+1 ai, 6k-3=bp,
4k-1+cm, k =
(ai, 6k-3+ai, 6k-1)/2+(ai, 6
k-3-ai, 6k-1)/2 ai, 6k
-1=bp,4k-1-cm,k
=(ai,6k-3+ai,6k-1)/2
-(ai,6k-3-ai,6k-1)/2 For even lines (p and m are even numbers), ai,6k-
4=bp, 4k-2 ai, 6k-2=bp
,4k+cm,k=(
ai, 6k-2+ai, 6k)/2+(ai, 6k-2
−ai, 6k)/2 ai, 6k = bp
,4k-cm,k=(
ai, 6k-2+ai, 6k)/2-(ai, 6k-2
−ai, 6k)/2 (p=m=i
, k are integers. The above seven equations are called the third equation. )

[
[0042] Also, here, the still image video processing circuit 3
The above-mentioned predetermined data compression processing performed in step 1 will be explained.

[0043] This data compression processing is, for example, adaptive dynamic range coding (ADRC) that utilizes the strong correlation of video signals in space and time.
anmic Range Coding).

In adaptive dynamic range encoding, pixel data is divided into blocks, each pixel data Xt in the block is converted based on the following formula, and the resulting compressed data Qt and the dynamic range DR, which is attribute data of the block, are Data compression is performed using the minimum value MIN. DR=MAX-MIN+1 Δ = DR/(2N-1) Qt = (Xt-MIN)/Δ Xt: t-th original signal data Qt: t-th compressed data DR: Dynamic range N: quantized bits after compression Number (luminance: 3, color difference: 2) MAX: Maximum value within the block MIN: Minimum value within the block

Furthermore, the interpolation processing provided in the still image video processing circuit 31 described above, for example, the circuit for performing the interpolation processing described in the first specific example and the circuit for performing adaptive dynamic range encoding (hereinafter referred to as The specific circuit configuration of the data processing circuit will be explained.

The data processing circuit includes, for example, as shown in FIG. 7, an interpolation processing circuit 60 that forms pixel data of a 4fSC video signal from pixel data of a 6fSC video signal by interpolation processing, and a It is composed of an ADRC circuit 70 that performs adaptive dynamic range encoding on pixel data, and a rearrangement circuit 80 that rearranges the compressed pixel data from the ADRC circuit 70 into a predetermined format.

The interpolation processing circuit 60 is configured to receive a signal from the video RAM 32 shown in FIG.
A delay device 62 that delays, for example, 8-bit pixel data per pixel by one pixel, an adder 63 that adds the pixel data from the terminal 61 and the delayed pixel data, and multiplies the added value by 1/2. It is composed of a multiplier 64 and a selector 65 that switches and selects the output of the multiplier 64 and the output of the delay device 62.

The ADRC circuit 70 includes a RAM 71 that temporarily stores the pixel data from the interpolation processing circuit 60;
A maximum & minimum value detection circuit 72 detects the maximum value MAX and minimum value MIN of pixel data read out in block units in ADRC from the RAM 71, and from the maximum value MAX and minimum value MIN from the maximum & minimum value detection circuit 72. an adder 73 that calculates the dynamic range DR;
It is composed of an adder 74 that subtracts the minimum value MIN from each pixel data read out from the AM 71, and an adaptive encoder 75 that quantizes the output of the adder 74 based on the dynamic range DR.

The reordering circuit 80 processes each quantized data Q obtained by quantization from the ADRC circuit 70.
It consists of a register 81 that stores predetermined 384 items from among them, and a selector 82 that switches and selects the dynamic range DR, minimum value MIN, quantized data Q, and quantized data Q from the register 81 from the ADRC circuit 70. be done.

[0050]Then, the video RAM 3 shown in FIG.
2, that is, each pixel data ai,j for one frame (i=1 to 484; indicates the line number; j=1 to 1152; indicates the order on the line) is transmitted via the terminal 61. For example, as shown in FIG. 8A, the signal is supplied to a delay device 62 and an adder 63 in line sequential order in the NTSC system. As shown in FIG. 8B, the delay device 62 delays the pixel data ai,j by one pixel (here, this delayed pixel data is referred to as ai,j, and the pixel data supplied via the terminal 61 is ai,j+1). The pixel data ai,j+1 supplied via the terminal 61 and the delayed pixel data ai,j are added in an adder 63 and a multiplier 64, as shown in FIG. 8C, and then
1/2 ((ai,j +ai,j+1)/2)
) is supplied to the selector 65. The selector 65 is shown in FIG.
As shown in D, pixel data ai,j from the delay device 62
and pixel data from the multiplier 64 (ai,j +ai,
j+1)/2 at a ratio of 2:1, and the selected pixel data is supplied to the RAM 71.

By sequentially storing pixel data from the selector 65, the RAM 71 stores pixel data of 1152×484 (sample×
(line) pixel data is stored. The stored pixel data is then stored in the memory controller 5 shown in FIG.
For example, a 6×4 (sample×line) block Bm,n (m=1 to 121,n
=1 to 192) and supplied to the maximum & minimum value detection circuit 72 and the adder 74. The maximum & minimum value detection circuit 72 detects the maximum value MAXm,n and the minimum value MINm,n of the 24 pixel data in each block Bm,n.
is detected, the maximum value MAXm,n is supplied to the adder 73, and the minimum value MINm,n is supplied to the adders 73, 74 and the selector 82. The adder 73 adds the maximum value MAXm,n
Subtract the minimum value MINm,n from each block Bm
, n, and supplies this dynamic range DRm,n to the adaptive encoder 75 and the selector 82. Further, the adder 74 subtracts the minimum value MINm,n from each pixel data in the block Bm,n from the RAM 71, and supplies the subtraction result to the adaptive encoder 75.

The adaptive encoder 75 quantizes the subtracted value from the adder 74 into, for example, 0 to 4 bits based on the dynamic range DRm,n, and supplies the quantized value to the register 81 and selector 82 . Specifically, pixel data ai,
Convert j to quantized data Qi,j of 0 to 4 bits, and pixel data (ai,j +ai,j+1)/2
0 to 4 bits of quantized data (Qi,j +Qi,j
+1)/2. That is, the ADRC circuit 70
performs data compression processing on pixel data.

The register 81 has, for example, 4 bits x 384 bits.
The above-mentioned 6fS is
The 6fSC reproduction data necessary to reproduce the pixel data ai,j of the C video signal, that is, the quantized data Qi,3k (k is an integer) that is unnecessary for the lower system, is sequentially stored.

The selector 82 controls the adaptive encoder 75 under the control of the memory controller 53 shown in FIG.
Quantized data Qi,j from , dynamic range DRm,n from adder 73 , maximum & minimum value detection circuit 7
The minimum value MINm,n from 2 is rearranged into a predetermined format. Specifically, for example, as shown in FIG. 10, four lines from the beginning, that is, blocks B1,1 to B1 shown in FIG.
Quantized data Qi,j (i=1 to 4, j=1 to 1152, excluding j=3k) required by the lower system in B1,192, dynamic range DRm,n
(m=1, n=1~192), minimum value MINm, n
are arranged in the order of blocks B1,1 to B1,192, respectively, and then quantized data Qi,3k (k=1
~384) are arranged in order. Similarly, the last 4
up to the line, that is, blocks B121,1 to B1
21,192 quantized data Qi,j (i=48
1 ~ 484, j = 1 ~ 1152), dynamic range DRm, n (m = 121, n = 1 ~ 192),
Arrange the minimum values MINm, n, etc.

The rearranged quantized data Qi,j etc. from the selector 82 are supplied to the RAM 34 via the terminal 83 and the above-mentioned PCM process circuit 33 shown in FIG. 1, and are temporarily stored in the RAM 34. and,
The RAM 34 separates and reads, for example, quantized data Qi,j, etc. required by the lower system and quantized data Qi,3k unnecessary for the lower system, according to a predetermined order according to the read address from the memory controller 53, and The read quantized data Qi,j, etc. are supplied to the PCM process circuit 33.

This PCM process circuit 33 adds "00" as an ID to the quantized data Qi,j, etc. required by the lower system, and adds "01" as an ID to the quantized data Qi,3k that is unnecessary for the lower system. " is added and supplied to the MUX 41 shown in FIG. 1 described above. As a result, the quantized data Qi,j, etc. are recorded in the PCM audio area of the magnetic tape 1 together with the ID. That is, a still image video signal is recorded in the PCM audio area of the magnetic tape 1 as a digital video signal.

Next, the operation of reproducing a still image video signal from the magnetic tape 1 on which the still image video signal has been recorded as a digital video signal in the PCM audio area in this host system will be explained. .

For example, when the function control circuit 51 sets the still image reproduction mode, the system controller 52 detects a control signal corresponding to the setting and controls each section to operate in the still image reproduction mode.

Specifically, the PCM process circuit 33:
From the PCM audio area of the magnetic tape 1 to the head section 40
The synchronization signal, ID, etc. are separated and detected from the still image data reproduced by the system, and error correction is performed, and the compressed data subjected to this error correction is temporarily stored in the RAM 34. The compressed data read from the RAM 34 is then supplied to the still image video processing circuit 31. Also, P
The ID detected by the CM process circuit 33 is supplied to the system controller 52.

The still image video processing circuit 31 performs data expansion processing on the compressed data, reproduces a 6fSC video signal, and supplies it to the video RAM 32. On the other hand, the system controller 52 receives I from the PCM process circuit 33.
Based on D, the memory controller 53 is controlled to store each pixel data constituting the video signal in a predetermined area of the video RAM 32.

The video signal stored in the video RAM 32 is processed by the memory controller 5 at the time when one field or one frame of the video signal is stored in the video RAM 32.
The data is repeatedly read out using a read address synchronized with the NTSC synchronization signal from 3 and supplied to the still image video processing circuit 31. Still image video process circuit 31
After converting the video signal into a video signal compliant with the NTSC system, the switch 27, the D/A converter 23 and the terminal 2
6 to the monitor receiver. As a result, the still image recorded in the PCM audio area of the magnetic tape 1 is displayed on the monitor receiver.

Here, data decompression, that is, an adaptive dynamic range decoding circuit and a circuit for reproducing the pixel data ai,j of the 6fSC video signal (hereinafter referred to as data processing circuit) provided in the above-mentioned still image video processing circuit 31 will be explained. The specific circuit configuration of the following will be explained.

The data processing circuit receives quantized data Q supplied as serial data, for example, as shown in FIG.
i,j, dynamic range DRm,n, minimum value M
A reordering circuit 110 that rearranges INm,n so as to correspond to the spatial positions shown in FIG. 9 described above, an ADRC circuit 120 that performs adaptive dynamic range decoding, and
6f from the decoded pixel data from the RC circuit 120
It is composed of an inverse interpolation processing circuit 130 that reproduces pixel data of an SC video signal.

The reordering circuit 110 receives quantized data Q supplied as serial data via a terminal 111.
an S/P converter 112 that converts i,j, dynamic range DRm,n and minimum value MINm,n into parallel data; quantized data Qi,j converted into the parallel data, dynamic range DRm,n and minimum value MINm,n; It is composed of a RAM 113 that temporarily stores the values MINm and n.

The ADRC circuit 120 generates quantized data Qi, based on the dynamic range DRm,n.
an adaptive decoder 122 that decodes pixel data, an adder 123 that adds a minimum value MINm,n to the data from the adaptive decoder 122 and reproduces pixel data, and the RAM
The quantized data Qi,j and the dynamic range DRm,n read from the adaptive decoder 1
22, and a changeover switch 121 that supplies the minimum value MINm,n to the adder 123.

The inverse interpolation processing circuit 130 includes a delay device 1 that delays the pixel data from the adder 123 by one pixel.
31, and a multiplier 1 that multiplies the output of the delay device 131 by 2.
32, and from this doubled pixel data, the adder 1
23, and a selector 135 that switches between the output of the adder 134 and the output of the delay device 131.

Then, as shown in FIG. 10, the quantized data Qi,j, dynamic range DRm,n and The minimum value MINm,n is converted into parallel data by the S/P converter 112 and supplied to the RAM 113. RAM1
13 is the quantized data Qi,j and the dynamic range DRm,n corresponding to the spatial position shown in FIG.
and the minimum value MINm,n are once stored for every 4 lines. Quantized data Qi read from RAM 113,
j and the dynamic range DRm,n are supplied to the adaptive decoder 122 via the switch 121, and the minimum value MINm,n is supplied to the adder 123 via the switch 121.

The adaptive decoder 122 blocks Bm,
Each quantized data Qi,j in n is adaptively decoded based on the dynamic range DRm,n, and the adder 12
Supply to 3. The adder 123 adds the minimum value MINm,n to the decoded data to obtain pixel data a1,1.
, (a1,2 + a1,3 )/2, a1,3 ,...
. . , and supplies these pixel data to the delay device 131 and the adder 134.

The delay device 131 receives pixel data a1,1,
(a1,2+a1,3)/2, a1,3, . . . are delayed by one pixel and supplied to the multiplier 132 and the selector 135. The multiplier 132 receives the delayed pixel data a1,
1, (a1,2 + a1,3)/2, a1,3,
... is multiplied by 2, and the multiplication result is supplied to the adder 134. Adder 134 converts the output of multiplier 132 into adder 1
23 and supplies the subtraction result to the selector 135. Then, by selectively switching between the output of the delay device 131 and the output of the adder 134 in the selector 135,
Pixel data ai,j (i=1 to 484, j=1 to 11
52) is reproduced. That is, the multiplier 132 and the adder 134 perform a process opposite to the above-described interpolation process to reproduce the pixel data a1,2.

In other words, using the pixel data bp,q of the 4fSC video signal and the 6fSC reproduction data cm,n, the pixel data ai,j of the 6fSC video signal is reproduced according to the first equation described above. The reproduced pixel data ai,j is then supplied to the video RAM 32 shown in FIG. 1 described above via the terminal 136.

[0071] Note that the second mode explained in the still image recording mode
, when pixel data is recorded by the interpolation process of the third specific example, the pixel data bp,q of the 4fSC video signal
and 6fSC reproduction data cm,n to reproduce the pixel data ai,j of the 6fSC video signal according to the second or third equation described above.

As described above, the upper system includes the still image video processing circuit 31 shown in FIG.
0 etc. is required, but since the host system is originally a highly functional and expensive device, it does not affect the cost much, so this is not a problem.

Next, the magnetic tape 1 on which the video signal of a still image is recorded by the above-mentioned host system is processed at a frequency of 4fS.
A case where reproduction is performed in a lower system using the C sampling clock SCK2 will be explained.

For example, as shown in FIG. 12, the lower system uses a sampling clock SCK2 having a frequency of 4fSC.
a camera unit 10a that converts an imaging signal into a digital video signal using a digital video signal and performs signal processing such as so-called knee and gamma processing; a video signal processing unit 20a that processes a video signal of a video; A still image video signal processing section 30a that processes signals, and the moving video signal processing section 2
The head for time-division multiplexing the analog video signal from 0a and the digital video signal from the still image video signal processing section 30a and recording them in the video area and PCM audio area of the magnetic tape 1, respectively, and reproducing the reproduction RF signal. 40a, and a control section 50a that controls the moving image signal processing section 20a, still image signal processing section 30a, and the like.

[0075] In this way, the lower system is as shown in FIG.
It has approximately the same circuit configuration as the upper system shown in . Therefore, the circuits corresponding to the circuits of the upper system are given designation numbers with the same number plus the alphabet "a", and detailed explanations of each part are omitted, but this lower system has the sampling clock SCK2 as described above. It is designed to work with . Therefore, for example, the still image video processing circuit 31a is a 6f
It does not have a function of interpolating an SC video signal to form a 4fSC video signal.

Next, a description will be given of the operation of reproducing, in the lower system, a magnetic tape on which quantized data etc. obtained by interpolation processing or the like in the upper system are recorded together with an ID. A data processing circuit that is provided in the still image video processing circuit 31a shown in FIG. 12 and performs data expansion processing, etc., which is the opposite of the data compression processing described above, performs adaptive dynamic range decoding, as shown in FIG. 13, for example. ADRC circuit 9
0 and the pixel data bi,j required by the lower system
(i = 1 to 484, j = 1 to 768).

The ADRC circuit 90 receives quantized data Qi, which is supplied as serial data via a terminal 91.
j, dynamic range DRm,n and minimum value MI
S/P converter 9 that converts Nm,n into parallel data
2, and an adaptive decoder 94 that decodes the quantized data Qi,j based on the dynamic range DRm,n.
and a minimum value MIN to the data from the adaptive decoder 94.
An adder 95 that adds up the pixel data bi,j and reproduces the pixel data bi,j, and the quantized data Qi,j and the dynamic range DRm,n from the S/P converter 92 are sent to the adaptive decoder 94 to obtain the minimum value. Adder 95 adds MINm,n
It is composed of a changeover switch 93 that supplies power to the

The control circuit 100 includes a gate circuit 1 for gating a clock supplied through a terminal 101.
03, and a counter 104 that is reset by a reset pulse supplied via a terminal 102, counts the clock, and controls the gate circuit 103.

The counter 104 is configured as shown in FIG.
For example, it is initialized by a reset pulse that is generated when "00" is first detected as an ID, which is supplied from the system controller 52a shown in FIG. Qi,j, dynamic range DRm,n, and minimum value MINm,n are counted during the input period, and while counting up, the terminal 10
The gate circuit 103 is controlled to supply the ADRC circuit 90 with the clock supplied through the ADRC circuit 1. Also, for example, the lower system counts the number of tracks in which the necessary quantized data Qi,j, dynamic range DRm,n, and minimum value MINm,n are recorded, and while counting up, The gate circuit 103 is controlled to supply the ADRC circuit 90 with a clock synchronized with the supplied track.

On the other hand, as shown in FIG. 10, the quantized data Qi,j, dynamic range DRm,n and The minimum value MINm,n is converted into parallel data by the S/P converter 92. Then, via the changeover switch 93,
Quantized data Qi,j and dynamic range DRm
, n are supplied to the adaptive decoder 94, and the minimum value MIN
m, n are supplied to an adder 95.

The adaptive decoder 94 has a gate circuit 103
, and converts each quantized data Qi,j in block Bm,n into a dynamic range DRm,n
It is adaptively decoded based on the information and supplied to the adder 95. The adder 95 adds the minimum value MINm,
n is added and the pixel data a1,1, (a1,2 +
a1,3)/2, a1,3, . . . That is, the pixel data bi,j required by the lower system is reproduced. Then, the reproduced pixel data bi,j
is connected via the terminal 96 to the video RAM 3 shown in FIG.
2a.

In this way, in the lower system, the control circuit 100 performs interpolation processing by controlling the ADRC circuit 90 to operate during the period for reproducing pixel data required by the lower system based on the ID. The pixel data bi,j necessary for the lower system can be easily reproduced without requiring a circuit for performing reverse processing.

As is clear from the above explanation, the lower system only needs to select and reproduce pixel data based on the ID, and from the pixel data ai,j of the 6fSC video signal to the 4fSC video There is no need to form pixel data bp,q of the signal. That is, in the lower system, a magnetic tape on which still images are recorded can be easily reproduced using the sampling clock SCK1 having a frequency of 6fSC in the upper system. In other words, magnetic tape compatibility between the lower system and the upper system can be ensured without increasing the circuit scale of the lower system.

[0084] In the above explanation, the ID is added to the digital video signal of a still image and recorded in the PCM audio area, but for example, the so-called guard band (or loading
Index), a so-called cute track, or a so-called audio track. Furthermore, when recording still image video signals in the host system, subsampling and ADRC encoding may be used in combination. In addition, in the first specific example, pixel data ai
, j. For example, when a carry occurs, this increased 1 bit may also be recorded at the same time to prevent rounding errors due to the carry.

Furthermore, the present invention is not limited to the above-mentioned embodiments; for example, a so-called deep recording method in which the recording area is divided in the thickness direction of a magnetic tape is adopted, and an analog video signal and a digital signal are It goes without saying that the present invention can be applied to a video tape recorder or the like that can record in each of these areas and reproduce the recorded analog video signal and digital.

[0086]

Effects of the Invention As is clear from the above explanation, in the present invention, the video signal is sampled by the first sampling clock to form the first image data, and the video signal is sampled by the first sampling clock. The second image data of the second sampling clock is formed by interpolating the first image data, and the third image data is reproduced by using the formed second image data. forming image data of from the first image data;
By recording the second image data and third image data on the recording medium, the recording medium on which the video signal is recorded by the upper system that uses a high frequency sampling clock can be played back by the lower system that uses the low frequency sampling clock. When doing so, the video signal can be easily reproduced without increasing the circuit scale of the lower system. In other words, compatibility between the recording media of the lower system and the upper system, such as magnetic tape, can be ensured without increasing the circuit scale of the lower system.

[Brief explanation of the drawing]

FIG. 1 is a block circuit diagram showing the circuit configuration of a camera-integrated 8 mm video tape recorder using a sampling clock having a frequency of 6 fSC to which the present invention is applied.

FIG. 2 is a diagram showing a spatial arrangement of pixel data of a 6fSC video signal.

FIG. 3 is a diagram showing a spatial arrangement of pixel data of a 4fSC video signal.

FIG. 4 is a diagram showing a main part of the spatial arrangement of pixel data for explaining the principle of interpolating pixel data of a 6fSC video signal to form pixel data of a 4fSC video signal.

FIG. 5 is a diagram showing a main part of the spatial arrangement of pixel data for explaining the principle of interpolating pixel data of a 6fSC video signal to form pixel data of a 4fSC video signal.

FIG. 6 is a diagram showing essential parts of the spatial arrangement of pixel data for explaining the principle of subsampling pixel data of a 6fSC video signal and then performing interpolation processing to form pixel data of a 4fSC video signal. .

FIG. 7 is a block circuit diagram showing the circuit configuration of a data processing circuit that performs interpolation processing, etc., provided in the still image video processing circuit constituting the camera-integrated 8mm video tape recorder.

FIG. 8 is a time chart for explaining the interpolation processing operation of the data processing circuit.

FIG. 9 is a diagram illustrating the spatial arrangement of pixel data and an enlarged portion of the same for explaining adaptive dynamic range encoding.

FIG. 10 is a time chart for explaining the rearrangement operation of the data processing circuit.

FIG. 11 is a block circuit diagram showing a circuit configuration of a data processing circuit that performs adaptive dynamic range decoding, etc., provided in a still image video processing circuit constituting the camera-integrated 8 mm video tape recorder.

FIG. 12 is a block circuit diagram showing the circuit configuration of a camera-integrated 8mm video tape recorder using a 4fSC sampling clock.

FIG. 13 is a block circuit diagram showing the circuit configuration of a data processing circuit that performs adaptive dynamic range decoding, etc., provided in a still image video processing circuit that constitutes a camera-integrated 8mm video tape recorder that uses the 4fSC sampling clock. It is.

FIG. 14 is a diagram showing a tape format of magnetic tape used in an 8 mm video tape recorder.

FIG. 15 is a diagram showing a spatial arrangement of pixel data for explaining the principle of forming a 4fSC video signal from a 6fSC video signal.

[Explanation of symbols]

1...Magnetic tape 31...Still image video process circuit 32...Video RAM 33...PCM process circuit 41...MUX 45...Rotating head 52...System controller

Claims (1)

[Claims] 1. A video signal is sampled by a first sampling clock to form first image data, and second image data is generated by a second sampling clock having a frequency lower than that of the first sampling clock. is formed by interpolating the first image data, and the second image data thus formed is used to form the first image data.
video signal recording, characterized in that third image data for reproducing the image data of is formed from the first image data, and the second image data and the third image data are recorded on a recording medium. Method.