JPH04252632A - Cell exchanging method and cell exchanging system of this method - Google Patents

Abstract

PURPOSE:To considerably reduce unbalance and closing of paths in a routing network. CONSTITUTION:At the time of cell exchange between incoming lines IP0 to IPn and outgoing lines OP0 to OPn, a presequentalizing part 100 adds a prescribed sequential code to plural cells of at least one incoming line in the input order, and a dietributing network 200 distributes these cells to different paths in time division, and a routing network 300 routes each of distributed cells to a corresponding outgoing line in accordance with its routing tag information, and a postsequentializing part 400 sequentializes cells after routing in accordance with the sequential code. Thus, the degree of congestion of cells in the routing network 300 is uniformized, and cells transposed in the routing network 300 are sequentialized again in the original cell input order.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cell switching method and a cell switching system using the method, and more particularly to a cell switching method for switching cells between a plurality of input and output lines and a cell switching system using the method.

Today, wideband ISDNs use asynchronous transfer mode (ATM) to support multimedia such as voice, images, and high-speed data communications.
A high-speed communication system using fixed-length packets (cells) called Transfer Mode is being considered, but there is a need for a cell switching system that can route such cells at high speed without internal blockage.

0003

20 is a diagram explaining the routing operation of a conventional routing network. In the figure, 1 is a cross-point switch section, IP00 to IPmn are its incoming lines, and 0P
00 to 0Pmn are also outgoing lines, S11 to Sk3 are crosspoint switches each having a buffer at each crosspoint, a to c are cells, and 2 controls the routing of the crosspoint switch unit 1 according to the routing tag H of each cell. This is a switch control section.

Conventionally, when a call occurs, for example, the incoming IP address is
0 to the same routing tag H (for example, outgoing line 0P00
When a series of high-speed cells a to c having destinations ) are input, the switch control unit 2 sets a specific path ■ for them,
The path (2) was fixed for cells a to c.

FIG. 21 is a timing chart of the conventional routing operation.
When input, the cells a to c are written into the buffer of the cross point switch S11 at high speed, for example, at a rate of time t per cell by the write clock signal on the input line side. However, the crosspoint switch unit 1 has limitations such as its internal transfer clock being slow or the routing process of the switch control unit 2 taking time, so for example, the average transfer time per cell is T. be. Moreover, since the path ■ is fixed for cells a to c, cells a to c of cross point switch S11 end up
Pass ■ takes 3T and cross point switch S
It will be transferred to 13. Therefore, if the outgoing line OP0
Even if cell reading from 0 is performed at high speed at a rate of time t per cell, there is a limit on the transfer speed (capacity) due to the routing network as shown in the figure, so as the amount of cell communication increases, internal blockages often occur. I was awake.

Moreover, when the amount of cell communication increases further, the buffer overflows and cells are sometimes discarded. Also,
When looking at such a routing network as a whole, a situation may occur in which only path (1) becomes congested and other paths are vacant, so the usage efficiency of such a routing network has been significantly reduced.

Furthermore, FIGS. 22 and 23 show the conventional Banyan (
This is a diagram explaining the routing operation of the Banyan) network.
In the figure, IP0 to IP7 are incoming lines, 0P0 to 0P7
is an outgoing line, and A11 to A43 are (2×2) type self-routing switches.

[0008] This self-routing switch checks bits 0/1 of the routing tag H, and if it is "0",
If it is "1", it is a switch that connects the incoming line to the outgoing line on the upper (0) side, and if it is "1", it connects the incoming line to the outgoing line on the lower (1) side. The most significant bit (MSB) of tag H is checked, and the second stage switches A12 to A42 respectively check the next bit, and the third
The switches A13 to A43 of the stage each have the least significant bit (LS
B).

Therefore, each self-routing switch A1
1 to A43 are unblocked unless their two incoming lines are connected to the same outgoing line, but become blocked if their two incoming lines are connected to the same outgoing line. This blocking/non-blocking is determined by the routing tags H of the two cells input to the two input lines, respectively.

FIG. 22 shows an example of a special cell input mode. When routing tags H as shown in the figure are simultaneously input to incoming lines IP0 to IP7, the path becomes unblocked at each stage. All cells are fast and each outgoing line 0P0
Transferred to ~0P7.

However, even if there is no blockage, if the amount of cell communication per incoming line increases significantly, internal blockage may occur for the same reason as described for the conventional crosspoint switch section 1, or cells may be discarded due to buffer overflow. I can't escape it.

On the other hand, FIG. 21 shows an example of a special case where the mode of cell input is different. When routing tags H as shown in the figure are simultaneously input to incoming lines IP0 to IP7, internal Since blockages occur, cell transfer delays due to this type of self-routing network are more serious.

[0013] Normally, blockage occurs in one of the partial paths in the intermediate state described above, but when looking at the entire self-routing network, only one path is blocked and other paths are blocked. Since a situation in which a path is vacant may occur frequently, the efficiency of use of such a self-routing network has been significantly reduced.

[0014]

[Problem to be Solved by the Invention] As mentioned above, in conventional routing networks, the path is fixed when a call is generated.
Unbalanced cell congestion occurred within the routing network, and the usage efficiency of the routing network was significantly reduced.

Furthermore, in conventional self-routing networks, cells with the same routing tag information input from one incoming line occupy a certain path, so within the routing network there are frequent internal connections between cells input from other incoming lines. A blockage occurs;
The usage efficiency of the routing network was significantly reduced.

An object of the present invention is to provide a cell switching method and a cell switching system using the method, which can significantly reduce path imbalance and blockage in such a routing network.

[0017]

[Means for Solving the Problems] The above problems are solved by the configuration shown in FIG. That is, the cell switching system of the present invention is a cell switching system in which cells are exchanged between a plurality of incoming and outgoing lines, and includes a distributed network 200 that distributes a plurality of cells on at least one incoming line to different paths in a time division manner, and a routing network 300 that routes each subsequent cell to a corresponding outgoing line according to its routing tag information.

Further, in a cell switching system of the present invention, in which cells are exchanged between a plurality of incoming and outgoing lines, a predetermined sequential code is added to a plurality of cells on at least one incoming line in the order of their input. Ordering unit 10
0, a distribution network 200 that distributes each cell after the addition to different paths in a time division manner, a routing network 300 that routes each cell after the distribution to a corresponding outgoing line according to its routing tag information, and a post-ordering unit 400 that reorders each cell after routing according to the sequential code.

[0019]

[Operation] In the cell switching system of the present invention, when exchanging cells between a plurality of incoming lines IP0 to IPn and outgoing lines OP0 to OPn, the distributed network 200 switches in advance at least one incoming line (for example, IP0). For example, multiple cells are connected to different paths (for example, input lines IP0 to I
The routing network 300 routes each cell after the distribution to the corresponding outgoing line of the routing network 300 according to its routing tag information. This attempts to equalize the congestion of cells within the routing network 300.

Furthermore, in the cell switching system of the present invention, a plurality of incoming lines IP0 to IPn and outgoing lines OP0 to OP
When exchanging cells with n, pre-sequencing unit 1
00 is a predetermined sequential code (
For example, 0, 1, 2,) is added, and the distributed network 20
0 distributes each cell after the addition to different paths in time division (for example, paths corresponding to incoming lines IP0 to IPn),
On the other hand, the routing network 300 routes each cell after the distribution to the corresponding outgoing line according to its routing tag information, and then the post-ordering unit 400 routes each cell after the routing using the sequential code (0 ,1,
2,), thereby making the congestion of cells within the routing network 300 uniform, and even if the order of cells within the routing network 300 varies, the original cell input reordered in order.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 2 is a block diagram of a cell switching system according to a first embodiment, and the feature of this embodiment is that a conventional routing network 300 consisting of a cross-point switch section 1 and a switch control section 2 can be used.

In the figure, the same reference numerals as in FIG. 20 indicate the same or equivalent parts, 100 is a pre-ordering unit that adds a predetermined sequential code to each of the plurality of cells of input lines IP0 to IPn in the order of input, and 200 is a pre-sequencing unit. a distributed network that disperses each cell after the addition to different outgoing lines (paths) in a time-division manner; 3;
00 is a routing network that routes each cell after the distribution to a corresponding outgoing line according to its routing tag H;
400 is a post-ordering unit that reorders each cell after the routing according to the sequential code.

Further, in the distributed network 200, reference numeral 3 denotes a switch section that can connect the input and output lines in a non-blocking manner, and 4 is a distributed control section that controls the connection of the switch section 3 in a barrel shift mode.

The switch unit 3 is composed of (n+1) selector circuits that select a different one of all incoming lines IP0 to IPn according to a switch signal S, and connect each one to the outgoing lines OP0 to OPn. Furthermore, the distributed control unit 4 can be configured with a programmable counter that counts according to a predetermined counting sequence every time one cell is transferred.

FIG. 3 is a diagram for explaining the operation of the distributed network of the first embodiment. The figure shows a case where a series of high-speed cells a to c are input to the incoming line IP0 due to call generation. (A) in FIG. 3 shows a state in which the input and output lines are matched by the switch signal S0 of the distribution control unit 4, and in this state, cell a is connected to the output line OP0.
is output to. FIG. 3B shows a state in which the input and output lines are barrel-shifted by one step by the switch signal S1, and in this state, the cell b is output to the output line OP1. (C in Figure 3)
) indicates a state in which the barrel has been further shifted by one step by the switch signal S2, and in this state, the cell c is output to the output line OP2.

FIG. 4 is a diagram explaining the routing operation of the routing network of the first embodiment.
00 barrel-shifts and distributes the cells a to n, the cells a to n are input to the crosspoint switch S11 of the routing network 300 separately into incoming lines IP00 to IP0n as shown in the figure.

By the way, these cells a to n have different incoming lines, but their routing tags are all the same (for example, outgoing line OP00), so the switch control unit 2 assigns cells from each incoming line to the common outgoing line OP00. It is possible to determine that the cells are concentrated and to assign paths ■ to ■ to each cell.

FIG. 5 is a timing chart of the routing operation of the first embodiment. In the figure, cells a to n inputted to the incoming line IP0 of the distributed network 200 are distributed at the timing shown in the figure, and are distributed to the incoming lines IP00 to IP0 of the routing network 300.
n, and each cell is written into the corresponding buffer of the cross-point switch S11 at a rate of time t per cell by a write clock signal on the incoming line side. In this example, the average transfer time per cell in the crosspoint switch section 1 is T, which is slow, but since the cells a to n are transferred to the crosspoint switch S13 via the parallel paths ■ to ■, all The time required to transfer cells a to n is much shorter than in the past.

Therefore, according to the first embodiment, even if the cell communication volume of the incoming line IP0 of the distributed network 200 increases extremely,
Since each cell is input to the routing network 300 in a distributed manner, concerns about not only internal blockage but also cell discard due to buffer overflow are greatly reduced.

Furthermore, when looking at the entire routing network 300, it is possible to avoid the conventional situation in which only the path ■ is congested and the other paths ■ and ■ are vacant, and the usage efficiency of the routing network 300 is improved. Significant improvement compared to conventional methods.

By the way, each cell that is distributed and input to the routing network 300 should arrive at the outgoing line in the same order as the input, but in reality, various delays occur depending on the relationship with other cells in the routing network, so the output line is We cannot guarantee the order in which they will arrive on the line. Therefore, in the first embodiment, the pre-sequencing unit 10
0, a serial number is added to the input cell, and the post-sequencing unit 40
0 corrects the order of cells that arrive late.

FIG. 6 is a diagram showing a part of the pre-sequencing section of the first embodiment, and this figure shows a portion of the pre-sequencing section 100 corresponding to the input line IP0. In the figure, 11 is the incoming IP
12 is a shift register that reads and stores the first memory cell of the buffer 11, 12a is a portion of the shift register 12 that stores the cell body a, and 12b is a buffer that temporarily stores cells from 0 to 0. Serial number SN for each outgoing line of the routing network 300 added to the cell body a
i, 12c is a part that stores the input line number IP0 (fixed) of the pre-sequencing unit 100 which is also added to the cell body a, and 13 is the logical destination information (VPI: Virtual Pass) in the cell body a. Identif
14 is a decoder that decodes the outgoing line number OPi of the ROM 13 and outputs the corresponding counter activation signals E0 to En, 15; ~17 is any counter activation signal E0~En
A counter that counts up at a rate of 1 count per cell when is true, 18 is the outgoing line number OPi of the ROM 13
Accordingly, any count value of counters 15 to 17 (
Serial number for each outgoing line of the routing network 300) SNi
This is a selector that selects and outputs.

Note that each energized counter counts up by one after writing the serial number SNi to the shift register 12b. Further, each energized counter returns to 0 after counting, for example, p cells, and repeats this counting cycle.

As described above, the serial number (0) and the incoming line number (IP0) of the pre-sequencing unit 100 are added to the first cell a, and the cell is output to the outgoing line OP0 of the pre-sequencing unit 100. The next cell b also has the same VPI, so the serial number (1) and incoming line number (IP0) are added.
Furthermore, since the next cell n also has the same VPI, a serial number (2) and an incoming line number (IP0) are added, and these are output to the outgoing line OP0 of the pre-sequencing section 100, respectively.

FIG. 7 is a block diagram showing an example of a buffer in the pre-sequencing section, and the buffer 11 has a function of detecting the state of cell congestion on the incoming line of the pre-sequencing section 100. In the figure, 21 is the input line I of the pre-sequencing unit 100.
Memory (MEM) for temporarily storing Pi cells, 22
23 is a write counter (WCTR) that generates the write address WA of the memory 21, a read counter (RCTR) that also generates the read address RA, and 24 is the write address W.
25 is an AN
D gate, 26 is an adder that adds a predetermined number of cells (α) to the upper bit B, 27 compares the upper bit A and the value (B+α) of the output of the adder 26, and calculates (A=B+
This is a comparator (CMP) that outputs true when α).

FIG. 8 is an operation timing chart of the buffer of the pre-sequencing section. In the figure, cells a to f of the input line IPi of the pre-sequencing section 100 receive the write request signal WREQi / (however, / indicates negative logic) and the write clock signal fWi, so that the count A of the write counter 22 increases by 1 each time writing of one cell is completed. On the other hand, cells a to f of the memory 21 are read out in accordance with the read clock signal fRi for which service permission has been obtained from the outgoing line Oi, and as a result, the count B of the read counter 23 increases by 1 every time reading of one cell is completed. Count up.

Thus, count B will track count A, but if there is an internal blockage in the routing network 300, only cell a will be read and the remaining cells b~
A state occurs in which f remains in the memory 21 and the count B of the read counter 23 is "1" and on standby.

In this state, the output of the comparator 24 (A
=B) is true (HIGH level) until timing t2, but the write request signal WREQi / is true (LOW level) between t1 and t2, so the AND gate 25 ends up being true (HIGH level) at timing t1. Until the timing, a signal BEi is output in which the buffer 11 is empty. Also, the output of the comparator 27 (A=B+α) is t7
becomes true at the timing of , thereby outputting a signal BFi indicating that the buffer 11 is busy.

FIG. 9 is a diagram showing a part of the post-sequencing section of the first embodiment, and this figure shows the part connected to the outgoing line OP0 of the routing network 300. In the figure, 31 is a shift register that temporarily stores the cell of the input line IP0 of the post-sequencing unit 40, 31a is a portion of the shift register 31 that stores the cell body a, and 31b is a portion that is added to the cell body a. Serial number SN for each outgoing line of the routing network 300
31c is a part that stores the input line number IPi of the pre-sequencing unit 100, which is also added to the cell body a, and 32 is a cell write part for notifying the completion of writing of cell a to the memory 33, which will be described later. This is a shift register that can forcibly set a flag (F) at the timing of writing into the cell.

Further, 33 is a memory (MEM) for temporarily storing cells, 34 is a selector for selecting write data WD to the memory 33, and 35 is a write address W of the memory 33.
The selector 36 that selects A is also the read address RA.
37 is the input line I of the post-sequencing unit 400.
This is a write counter that increments the lower bit of the write address WA for each byte of the write cell in accordance with the write clock signal fW0 from the P0 side. For example, if one cell body is 255 bytes, this write counter 37 generates a lower address of the memory 33 from 0 to 255, which is the result of adding 1 byte of the cell write flag (F).

Further, 38 is a microprocessor (MPU) that controls the readout of the memory 33, 39 is a ROM that stores the memory readout control program shown in FIGS. 11 and 12 executed by the MPU 38, and 40 is a A programmable counter (PGC) for reading cell blocks (a series of cells) in each designated area of the memory 33
), 41 is an AND gate.

Here, one of the write addresses WA in the memory 33 is the incoming line number IPi in the pre-ordering section 100 of the cell added to the body of the received cell, and the routing network 3.
Cell serial number SNi added to each outgoing line of 00
and the output of the write counter 37. For example, the write address WA of the cell body a is determined by the incoming line number (IP0) in the pre-sequencing unit 100, the cell serial number (0) added to each outgoing line of the routing network 300, and the output of the write counter 37. (0 to 255) are arranged and synthesized in order from top to bottom.

The other write address WA of the memory 33 is from the MPU 38, and while the memory 33 is not being accessed, the MPU 38 switches the selectors 34 and 35 to its own side and writes the cells already in the memory 33. The user resets the cell write flag (F) that has finished reading, or switches the selector 36 to its own side and checks the cell write flag (F) in the memory 33.

FIG. 10 is a diagram showing the storage mode of the memory of the post-sequencing section, and the data writing area of the memory 33 is roughly divided as shown in the figure by input line numbers IP0 to IPn of the pre-sequencing section 100. Each of the further divided areas has a serial number SN added to each outgoing line of the routing network 300.
It is subdivided by i. The beginning of each sub-divided area is the cell write flag (F) storage area 3.
3a, and the remainder is a storage area 33b of the cell body.

That is, this memory 33 is connected to the routing network 3.
All the cells that arrived at the outgoing line OP0 of 00 are stored, and the cells a to f among them are the incoming line IP of the pre-sequencing unit 100.
0, the outgoing line O of the routing network 300
is rerouted to P0 and is also rerouted to cell g
Cells ~i are distributed from the input line IP1 of the pre-sequencing unit 100 and then rerouted to the output line OP0 of the routing network 300, and cells j to m are distributed from the input line IPn of the pre-sequencing unit 100. After that, it is rerouted to the outgoing line OP0 of the routing network 300.

Thus, each cell a to m has a preordering section 1.
In each distributed processing of 00, consecutive serial numbers SNi are attached to each outgoing line of the routing network 300 (here, to the outgoing line OP0 of the routing network 300), so these are assigned to the incoming lines of the pre-sequencing unit 100. Each area is roughly divided by number, and the outgoing line O of the routing network 300 is
If the addresses pointed to by the serial numbers SNi added to P0 are used to write in random order in the order of arrival, cells can be reordered and written into addresses in the order of serial numbers, regardless of the order in which the cells arrive.

Note that in FIG. 10, since cells c and k have not yet arrived, the storage area 33a of the cell write flag is "0".
However, the storage area 33a in which cell writing has already been completed has become "F".

On the other hand, the MPU 38 sequentially searches the storage areas 33a of the memory 33, and when it finds an area where the cell write flag "F" continues for a predetermined number of times, the programmable counter 40 indicates that the cell block is Set the start address and end address of As a result, the programmable counter 40 is activated in conjunction with the setting of the terminal address, for example, the address PGC(X).
A series of cell block bodies g~ surrounded by and PGC(Y)
i is read out to the output line OP0 of the post-sequencing unit 400. Note that during this read period, the energizing signal EN from the programmable counter 40 is true. Then, when the programmable counter 40 finishes reading the cell block, the MPU 38 sets a read flag "0" in the storage area 33a.
It is possible to write a cell to be routed later into the cell block.

FIG. 11 is a flowchart of the memory read control of the post-sequencing section, which is entered into this process when the cell exchange system is powered on. In the figure, in step S1, an incoming line counter IPC for indexing each incoming line of the pre-sequencing unit 100 and a busy/busy counter of the programmable counter 40 are used.
The busy flag BSYF indicating unbusy is reset. In step S2, the incoming line counter IP in the memory 33 is
The cell write flag storage area 33a of the area indexed by C is searched. In step S3, it is determined whether the cell block in question can be output to the output line OP0 by checking whether the cell write flag "F" continues for a predetermined number or more, and if the cell block cannot be output, the process proceeds to step S7. Add 1 to the incoming line counter IPC. Also, if output is possible, step S4
Check the busy flag BSYF with
), the programmable counter 40 is in operation, so it waits until it is no longer busy. Eventually, when it's no longer busy,
In step S5, the area of the cell block to be read is set in the programmable counter 40, and the programmable counter 40 is started, and in step S6, the busy flag BSYF is set.

FIG. 12 is a flowchart of interrupt control of the post-sequencing section. When the programmable counter 40 finishes reading the designated cell block, the interrupt signal INT is input to this process. In the figure, in step S11, the cell write flag "F" of the cell block in the memory 33 for which reading has been completed is set to "0". In step S12, the busy flag BSYF is reset and the process returns to the interrupt interruption process of FIG.

FIG. 13 is a block diagram of a cell switching system according to a second embodiment. The feature of this embodiment is that the first stage of a routing network 300 consisting of a conventional cross-point switch section 1 and a switch control section 2 is replaced by a distributed control section 4'. The reason is that it is configured to be controlled by

In the figure, 500 is a distributed routing network that performs routing after distributing cells at the first stage; 4';
2 is a distributed control section that performs distributed control of the first stage of the cross-point switch section 1, and 2' is a routing control section that similarly performs routing control of the remaining stages.

FIG. 14 is a diagram for explaining the operation of the distributed routing network of the second embodiment. The figure shows a case where a series of high-speed cells a to n are input to the incoming line IP00 due to call generation. On the other hand, the distributed control unit 4' first writes cell a into the buffer of path ■ using switch signal S0, then writes cell b into the buffer of path ■ using switch signal S1, and so on, and then cell n. The switch signal Sn
writes to the buffer of path ■. Thus, entry line I
A series of cells a to n of P00 are cross point switches S
It was distributed over 11 multiple outgoing lines (paths).

By the way, since these cells a to n all have the same routing tag (for example, outgoing line OP00), the switch control unit 2'
Each of the 11 outgoing cells is a common outgoing OP of the routing network.
It is possible to determine that the cells are concentrated on 00 and assign paths 1 to 2 to each cell.

FIG. 15 is a block diagram of a cell switching system according to a third embodiment, and the feature of this embodiment is that the routing network 30
0 is provided with a self-routing network (ATM switch) 6.

In the figure, 5 is a distribution control unit that distributes incoming cells in a manner suitable for the path structure of the self-routing network 300, and 6 is a plurality of distributed control units that self-determine cell paths according to the routing tag H of the cell. It is a self-routing network in which self-routing switches are linked in multiple stages.

FIG. 16 is a diagram for explaining the operation of the distributed network of the third embodiment. The figure shows a case where a series of high-speed cells a to c are input to the incoming line IP0 due to call generation. (A in Figure 16)
) indicates a state in which the input and output lines are matched by the switch signal S0 of the distributed control unit 5, and in this state, the first cell a is output to the output line OP0. (B) in FIG. 16 shows the incoming lines IP0 and IP2 and the outgoing line OP0 due to the switch signal S3.
, OP2 are crossed, and in this state, the next cell b is distributed and output to the outgoing line OP2. In Figure 16 (
C) is connected to input lines IP0 and IP4 by switch signal S4.
This shows a state where the output lines OP0 and OP4 cross, and in this state, the next cell c is distributed and output to the output line OP4.

Note that this distributed control is not limited to the above; for example, the cells a to d of the incoming line IP0 are connected to the outgoing lines OP0, O
Cross distribution may be performed in the order of P4, OP2, and OP6. FIG. 17 is a diagram for explaining the operation of the self-routing network of the third embodiment. The self-routing network is an example of a Banyan network 6, and in the figure, AS11 to A
S43 is a self-routing switch that self-determines the path of a cell according to the routing tag H of the cell, B1,
B2 is a buffer.

In this example, in advance, the distributed control unit 5 switches the cells a to d of the incoming line IP0 of the switch unit 3 to the outgoing lines OP0,
Since the distribution is performed in the order of OP2, OP4, and OP6, in the Banyan network 6, the cell a of the incoming IP0 is first
follows the routing tag (000) and passes through the path ■ to the outgoing line OP0, then cell b of the incoming line IP2 follows the same routing tag (000) and passes through the path ■ to the outgoing line OP0, and then the incoming line IP4's Cell c follows the same routing tag (000) and passes through path ■ to outgoing line O
P0, and then cell d of incoming IP6 follows the same routing tag (000) and passes through path ■ to outgoing line OP0.
leading to.

By the way, paths ■ and paths ■ are blocked at the self-routing switch AS13, but the cells in the buffers B1 and B2 of the switch AS13 are connected to the outgoing line OP0.
Since it can be read by a high-speed clock signal from the side, the influence of the blockage is small. Furthermore, although paths (2) and (2) are blocked in the self-routing switch AS12, the input phases (timings) of cells a and c are far apart, so the effect of this blockage is small. Further, the relationship between path ■ and path ■ is also similar.

FIG. 18 is a diagram for explaining the operation of a self-routing network according to another embodiment, and the self-routing network is a Banyan network 6' according to another example. In this example, the cells a to d of the incoming line IP0 of the switch unit 3 are distributed in advance in the order of the outgoing lines OP0, OP4, OP2, and OP6 by the distribution control unit 5, so that in the Banyan network 6', the incoming line IP
0 cell a passes through path ■ according to its routing tag (000) to reach outgoing line OP0, and then connects to incoming line IP4.
Cell b follows the same routing tag (000) and passes the path ■ to the outgoing line OP0, then cell c of the incoming IP2 follows the same routing tag (000) and passes the path ■ to the outgoing line OP0, and then Incoming line IP6 cell d
follows the same routing tag (000) and passes through the path ■ to the outgoing line OP0. Therefore, the same effect as in the case of FIG. 17 can be obtained.

In this way, for this type of self-routing network, the distribution control unit 5 can have a simple configuration by predefining a distribution method suitable for the path structure (link structure, etc.) of the self-routing network. can perform optimal distributed control.

[0063] In this case, the distribution control unit 5 may distribute the cells on the incoming line that are particularly crowded, or distribute the cells on the incoming line of interest to other paths that are already crowded with cells. We must also consider things that will prevent this from happening.

FIG. 19 is a control flowchart of the distributed control unit of the third embodiment. When the cell switching system is powered on, this process is entered. In the figure, in step S21, an incoming line counter IPC for indexing each incoming line of the pre-sequencing unit 100 and a data register DR for storing information on distribution destinations, which will be described later, are reset, and in step S22, each incoming line of the switch unit 3 is reset in advance. A table counter TC for indexing a distribution table that defines how cells are distributed is set to "1". Step S23
Now, the buffer full signal BF detected by the pre-ordering section 100 is
It is checked whether the incoming line buffer 11 indexed by the incoming line counter IPC among 0 to BFn is full. If it is not full, the incoming line is not crowded with cells, so there is no need to distribute the cells, and the flow proceeds to step S24, in which the incoming line counter IPC is incremented by 1 and the process returns to step S22. If it is full, the process advances to step S25, where information on the distribution destination indexed by the incoming line counter IPC and table counter TC (incoming line number of the pre-sequencing unit 100) is read from the distribution table and set in the data register DR. . In step S26, the buffer full signals BF0 to BFn are
It is checked whether the buffer 11 of the incoming line to be indexed by the data register DR is full or not, and if it is not full, the cells may be distributed to the outgoing line, so in step S27, the incoming and outgoing lines to be indexed by the incoming line counter IPC and the data register are checked. One cell is exchanged (distributed) by crossing the incoming and outgoing lines indexed by DR. Further, when the memory is full, the process of step S27 is skipped. In step S28, the table counter TC is incremented by 1 and the process returns to step S23.

In the above, the distribution table is a table in which, for example, address 0 is written with the own outgoing line number, address 1 is written with the outgoing line number of the first candidate, address 2 is written with the outgoing line number of the second candidate, etc. That's fine. Then, the table counter TC is set to "1" in step S22, but this is done so that when an incoming line with crowded cells is found in step S23, the own line is not initially read out as a distribution destination from the distribution table. This is for the purpose of However, when the contents of the table counter TC return to "0" from its maximum value after the contents of the table counter TC have gone through all the other distribution destinations by the process of step S28, the own outgoing line number is changed to the distribution destination. It is read as .

Note that in step S26, the buffer is full B.
Detected whether F or not, but instead buffer empty B
It is also possible to check whether it is E or not. Further, the distributed control unit 5 of the third embodiment may be replaced with the distributed control unit 4 of the first embodiment, or conversely, the distributed control unit 4 of the first embodiment may be replaced with the distributed control unit 5 of the third embodiment. May be replaced.

Furthermore, in the above embodiment, the self-routing networks 6, 6' are composed of (2×2) type self-routing switches AS11 to AS43, but generally (n×m)
It may be configured with a type of self-routing switch.

[0068]

According to the present invention, the distribution network 200 distributes a plurality of cells on at least one incoming line to different paths in a time-division manner, and the routing network 300 distributes each cell after distribution according to its routing tag information. Since the route is routed to the corresponding outgoing line of the routing network 300, the congestion of cells within the routing network 300 is made uniform, the usage efficiency of the routing network 300 is improved, and there is no blockage within the network.

Further, according to the present invention, the pre-sequencing unit 100 adds a predetermined sequential code to a plurality of cells on at least one incoming line in the input order, and the distribution network 200 time-divides each added cell. The routing network 300 routes each cell after distribution to a corresponding outgoing line according to its routing tag information, and the post-ordering unit 400 routes each cell after routing according to the sequential code. Since reordering, routing network 3
The congestion of cells within 00 is equalized, and even if cells change back and forth within the routing network 300, they are reordered in the original cell input order.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the basic configuration of the present invention.

FIG. 2 is a block diagram of the cell switching system of the first embodiment.

FIG. 3 is a diagram illustrating the operation of the distributed network of the first embodiment.

FIG. 4 is a diagram illustrating the routing operation of the routing network of the first embodiment.

FIG. 5 is a timing chart of the routing operation in the first embodiment.

FIG. 6 is a diagram illustrating a part of the pre-ordering unit of the first embodiment.

FIG. 7 is a block diagram illustrating an example of a buffer of a pre-ordering unit.

FIG. 8 is an operation timing chart of a buffer in a pre-ordering section.

FIG. 9 is a diagram showing a part of the post-sequencing section of the first embodiment.

FIG. 10 is a diagram showing a storage format of a memory of a post-sequencing unit.

FIG. 11 is a flowchart of memory read control of a post-sequencing unit.

FIG. 12 is a flowchart of interrupt control of the post-sequencing unit.

FIG. 13 is a block diagram of a cell switching system according to a second embodiment.

FIG. 14 is a diagram illustrating the operation of the distributed routing network of the second embodiment.

FIG. 15 is a block diagram of a cell switching system according to a third embodiment.

FIG. 16 is a diagram illustrating the operation of a distributed network according to a third embodiment.

FIG. 17 is a diagram illustrating the operation of the self-routing network of the third embodiment.

FIG. 18 is a diagram illustrating the operation of a self-routing network according to another embodiment.

FIG. 19 is a control flowchart of the distributed control unit of the third embodiment.

FIG. 20 is a diagram illustrating the routing operation of a conventional routing network.

FIG. 21 is a timing chart of a conventional routing operation.

FIG. 22 is a diagram illustrating the routing operation of the conventional Banyan network.

FIG. 23 is a diagram illustrating the routing operation of the conventional Banyan network.

[Explanation of symbols]

100 Pre-ordering part 200 Distributed network 300 Routing network 400 Post ordering section

Claims (10)

[Claims] 1. A cell exchange method for exchanging cells between a plurality of incoming and outgoing lines, comprising: (200) distributing a plurality of cells of at least one incoming line to different paths in a time-sharing manner;
A cell switching method characterized by comprising a step (300) of routing each of the distributed cells to a corresponding outgoing line according to its routing tag information. 2. A cell exchange method for exchanging cells between a plurality of incoming and outgoing lines, comprising the steps of: (100) adding a predetermined sequential code to a plurality of cells of at least one incoming line in the order of their input; a step (200) of distributing each subsequent cell to different paths in a time-sharing manner; a step (300) of routing each cell after the dispersion to a corresponding outgoing line according to its routing tag information; a step (400) of reordering each cell according to the sequential code. 3. In a cell switching system that exchanges cells between a plurality of incoming and outgoing lines, a distributed network (200
), and a routing network (300) that routes each of the distributed cells to a corresponding outgoing line according to its routing tag information. 4. The distributed network (200) includes a switch unit (3) that can connect input and output lines in a non-blocking manner, and a distributed control unit (3) that controls connection of the switch unit (3) in a barrel shift mode. 4) The cell switching system according to claim 3, characterized by comprising: 5. The distributed network (200) includes a switch section (3) that can connect input and output lines in a non-blocking manner, and a switch section (3) that controls connection so that arbitrary input and output lines cross. 4. The cell switching system according to claim 3, further comprising a distributed control section (5) that performs the following operations. 6. The routing network (300) includes a crosspoint switch unit (1) in which a plurality of crosspoint switches each having a buffer at each crosspoint are linked in multiple stages, and a crosspoint switch unit (1) that connects the crosspoint switch unit (1) to a cell. 4. The cell switching system according to claim 3, further comprising a switch control section (2) for controlling routing to a corresponding outgoing line according to routing tag information of the cell switching system. 7. The routing network (300) is a self-routing network (6) in which a plurality of self-routing switches that self-determine the path of a cell according to the routing tag information of the cell are linked in multiple stages. The cell switching system according to claim 3, characterized in that: 8. A plurality of crosspoint switches having buffers at each crosspoint are provided with a crosspoint switch unit (1) linked in multiple stages, and the first stage of the crosspoint switch unit (1) is a distributed network (200). , the remaining stages thereof being configured to be a routing network (300). 9. A cell switching system that exchanges cells between a plurality of incoming and outgoing lines, comprising: a pre-sequencing unit (100) that adds a predetermined sequential code to a plurality of cells of at least one incoming line in the order of their input; , a distribution network (200) that distributes each cell after the addition to different paths in a time-division manner, and a routing network (200) that routes each cell after the distribution to a corresponding outgoing line according to its routing tag information.
300), and a post-ordering unit (400) that reorders each cell after the routing according to the sequential code.
) A cell exchange system characterized by comprising: 10. The distributed network (200) includes a detection unit (27) that detects the congestion level of cells on each incoming line, and the distributed network (200)
10. The cell switching system according to claim 9, wherein the mode of distribution is changed based on the detection output of step 27).