JPH0423172A - Production system for clock adjustment data - Google Patents

Abstract

PURPOSE:To quickly produce the highly accurate data by specifying a route to adjust the clocks at a circuit part where the extracted clocks are distributed and calculating the clock delay value of the specified route. CONSTITUTION:A circuit part where the clocks are distributed is extracted out of a subject logic circuit, and a route is specified in the circuit part to adjust the clocks. Then the specified route and its clock delay value are outputted. That is, a file 26 of the data showing the logic circuit is previously stored in a storage 24. Then a route to perform the adjustment of clocks and the clock delay time of the route are obtained by a host computer 22 by reference to the contents of the file 26 and based on the terminal operation. The data on the route and the delay time obtained by the computer 22 are outputted to the storage 24 and stored in a file 28 of the output destination in a form of a list. As a result, a clock adjustment subject route is specified in a short period of time and the clock delay value of the route is obtained with high accuracy.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Use Division Prior Art Problems to be Solved by the Invention Means for Solving the Problems Effects of the Invention [Summary] Necessary for clock adjustment of logic circuits The purpose of this study is to provide a method for creating data that is subject to clock adjustment in a short period of time, and also to determine the amount of clock delay for that route with high accuracy. a means for extracting a circuit portion to be adjusted from a target logic circuit; a means for specifying a route on which clock adjustment should be performed in the extracted circuit portion; a means for calculating a clock delay amount of the specified route; and means for outputting the calculated route and the calculated clock delay amount.

[Industrial Application Field] The present invention relates to a method for creating data necessary for adjusting a logic circuit.

In large computers, it is necessary to improve the processing speed and to guarantee this processing speed. Therefore, it is necessary to adjust the clock of the internal logic circuit according to the design.

[Prior Art] The path on which clock adjustment should be performed in a logic circuit is specified by the designer of the circuit, and the delay time of the specified path is also calculated. Time is input from a terminal, and these input data are used as data for clock adjustment [Problem to be solved by the invention] However, as computers become larger, clocks are subject to clock adjustment. As the number of routes has increased dramatically, it is difficult for logic circuit designers to identify all the routes that are incorrect, and it takes a huge amount of time to create them.

Furthermore, since the delay time of the clock adjustment path is calculated by the designer of the logic circuit, it is difficult to obtain the clock delay time with sufficient accuracy.

The present invention has been made in view of the above-mentioned conventional circumstances,
The purpose is to provide a method that allows a route to be subject to clock adjustment to be specified in a short time, and also allows the clock delay amount of that route to be determined with high precision.

[Means for Solving the Problems] In order to achieve the above object, the present invention adopts the method shown in FIG. 1.

The circuit portion to which the clock is distributed is extracted from the target logic circuit by means 10 in the figure.

Furthermore, means 12 specifies a path in which clock adjustment should be performed in the circuit portion extracted by means 10.

Further, the clock delay amount of the route specified by the means 12 is calculated by the means 14.

Then, the route specified by the means 12 and the clock delay amount calculated by the means 14 are outputted from the means 16.

[Operation] In the present invention, when a circuit portion to which a clock is distributed is extracted from a target logic circuit, a path in which clock adjustment should be performed is specified in this circuit portion.The specified path and its clock delay amount are is output.

[Embodiments] Hereinafter, preferred embodiments of the system according to the present invention will be described based on the drawings.

FIG. 2 illustrates the configuration of a system to which the present invention is applied, and one of the terminals 20-1, 20-2, . . . 20-n is operated by a logic circuit designer or the like.

These terminals 20-1, 20-2...20-n are connected to the host computer 22, and the host computer 22
A storage device 124 is connected to.

A file 26 of data indicating the target logic circuit is stored in advance in the storage device 24, and the route for which clock adjustment is to be performed and the clock delay time of that route are determined by the host computer 22 according to the terminal operation using the contents of the file 26. is required.

The data on the route and delay time determined by the host computer 22 is stored in the storage device 24 in the form of a list in the output light file 28.

In FIG. 3, the operation of this embodiment is explained using a flowchart. First, the file 26 in the storage device 24 is read into the host computer 22 (step 300), and the circuit portion to which the clock is distributed (clock distribution circuit) is read. The data shown is extracted from the data in the read file 26 (step 302).

Then, when both end points of the route for which clock adjustment is to be performed are specified by terminal operation (step 304), the route is specified on the clock distribution circuit (step 306).

For example, when the clock distribution circuit shown in Figure 4 is extracted, when points A and B are specified as route end points, the fan-in table showing point p linked to point B on the output side is first created. Search tag In addition, Fan Yinbin's m point and j point.

Point h+fa Point a, point b, and point a are searched in order.

Conclusion On the clock distribution circuit, a path from point B to point A is specified as shown in FIG.

Next, the clock delay time on this route is calculated (step 308).

Then, it is determined whether clock adjustment routes and clock delay times have been calculated for all specified route end points (step 31O), and all clock adjustment routes are identified and their clock delay times are calculated. is calculated (YES in step 310), data in a list representation in which each clock adjustment path and clock delay time correspond is output from the host computer 22 to the file 28 as adjustment data (step 312). ).

The clock delay time can be obtained, for example, by integrating from point a to point b in FIG.

As explained above, according to this embodiment, the route on which clock adjustment should be performed is automatically specified, so even if the target logic circuit is large-scale, the route specification can be corrected (reliably in a short period of time). You can do it with

Furthermore, since the clock delay time of the specified route is automatically calculated, high accuracy and lock delay time can be obtained in a short time.

By efficiently creating high-precision data for lock WR maintenance, it becomes possible to design a reliable, high-speed, large-scale computer in a shorter period of time.

[Effects of the Invention] As explained above, according to the present invention, the path on which clock adjustment is to be performed and the calculation of the amount of clock delay on that path are automatically performed. Highly accurate data can be created quickly even when

Therefore, it becomes possible to efficiently design a highly reliable logic circuit.

[Brief explanation of drawings]

FIG. 1 is an explanation of the principle of the invention. FIG. 2 is an explanation of the configuration of the embodiment. FIG. 3 is a flowchart explaining the operation of the embodiment. FIG. 4 is an explanation of the extracted clock distribution circuit. Explanation 1 of Specific Effect of Adjustment Path FIG. 6 is an explanation A of the specified clock adjustment path. 20-1゜20-2- ・・20-n...Terminal 22...Host computer 24...Storage device 26゜28...File Figure 1 Figure 2 Figure 3 Figure 6

Claims (1)

[Scope of Claims] Means (10) for extracting a circuit portion to which a clock is distributed from a target logic circuit; Means (12) for specifying a path on which clock adjustment should be performed in the extracted circuit portion; Means (14) for calculating the clock delay amount of the route
); and means (16) for outputting the specified route and the calculated clock delay amount.