JPH0195365A - Analyzing processing system for critical path - Google Patents

Abstract

PURPOSE:To reduce a necessary memory capacity, to trace a critical path, to check a clock skew at a high speed and to improve a data processing efficiency by providing a critical ready table, an even table, etc. CONSTITUTION:An event table 2 stores a next step pin number 21 to be calculated next, proceeds a delaying time value calculation, also stores a starting pin number 22 and a calculated integrating delaying time value 11 is stored into a critical ready table 1 together with a front step pin number 12. The table 2 is prepared for respective gates, and the area of the table of a gate step processed by the preparation of two gate steps can be used as the table of a new gate step. Consequently, when calculation is successively communicated and arrives at a final pin, the table 2 is preserved as a starting pin table, and by the information of the clock to the starting pin stored separately and the clock to a final pin, a clock skew for the FF checking can be obtained. Thus, the memory capacity is reduced and a data processing efficiency can be improved.

Description

[Detailed Description of the Invention] [Summary] Regarding a delay time analysis processing method in large-scale digital circuits, each flip-flop is or a critical delay table creation means for creating a critical delay table that stores the integrated delay time value and the terminal pin number of the previous stage flip-flop or gate circuit for each terminal pin of the gate circuit, and the next stage flip-flop whose delay time is to be calculated next. Or, it is equipped with an event table creation means for creating an event table that stores the terminal pin number of the gate circuit and the starting pin number of the critical path traced back to the starting point, and from the starting point to the final point of delay time calculation. For each stage of the gate, a critical delay table and an event table are created while mutually referring to the other table, and delay time calculation processing is executed.

[Industrial application field]

The present invention relates to CAD (computer-aided design), and particularly to a method for analyzing delay time in large-scale digital circuits.

When designing a large-scale digital circuit, the correctness of the logic is confirmed by logic simulation, and the delay time between flip-flops is calculated to verify whether it is within a predetermined tolerance range. Since delay time calculation processing for large-scale digital circuits requires a large amount of computer processing time, an efficient calculation method is required.

[Conventional technology]

In delay time calculation processing for large-scale digital circuits, calculating all possible paths requires a huge amount of computer processing time, so A method is used to calculate the delay time (hereinafter referred to as delay) of the path with the smallest delay time (hereinafter referred to as critical path).

FIG. 5 is a diagram for explaining a conventional delay time calculation processing method.

Figure <8) is an example of a digital circuit that is subject to delay time calculation processing. Figures (A, B in al.

C, H, and I indicate flip-flop circuits (hereinafter abbreviated as FF), and D, E, F, and G indicate intermediate gate circuits.

Also, a, b, c, m, and n indicate the clock pins of FF, and d+ e+ f+ g+ h+ ', j+
k,' indicate input pins of FF or gate.

In the delay time calculation process, starting from the clock pins a, b, and c of FFs A, B, and C, a delay calculation using a critical path (hereinafter referred to as critical delay) is started, and the data of FF-H and I are calculated. Calculation processing is performed until input pin k or l is reached.

In this example, the critical path is the path with the largest delay.

The calculation process calculates the integrated delay value by integrating the delay values one after another for each gate stage from the starting point OFF to the final OFF, and for gate stages with multiple inputs, the integrated delay value is calculated from the integrated delay value up to each input pin. The path passing through the pin showing the largest value is defined as a critical path, and the cumulative critical delay value of the next stage pin is obtained by adding the delay to the next stage pin using this cumulative delay value. In this way, the cumulative critical delay value up to the input pin of the final stage FF is calculated. The calculation process for the digital circuit shown in FIG. 5(a) is performed in accordance with the procedure described below, as shown in FIG.

(2) Calculate the delay ta from the clock input terminal CLKI to pin a of FF-A from the path length based on the circuit configuration data.

(2) Similarly, calculate the delay tb from the clock input terminal CLK2 to the pin b of FF-B.

(2) Similarly, calculate the delay tc from the clock input terminal CLK3 to the pin C of FF-C.

■Calculate the delay from pin a to pin d by adding the delay in FF-A and the delay due to the path length from the output pin of FF-A to the input pin d of gate D, and add ta to this value. is calculated as the delay td of pin d.

(2) Similarly, tb is added to the delay in FF-B and the delay due to the path length from the output pin of FF-B to the input pin e of gate D to calculate the delay te of pin e.

(2) Similarly, calculate the delay tf of the input pin f of the gate E.

(2) Similarly, calculate the delay tf of the input pin g of the gate E.

■Compare the delay td and te of input pins d and e of gate D. If jd<te, the path passing through pin e is set as a critical path.

(2) Similarly, delay tf and tg of input pins f and g of gate E are compared, and if tf<tg, the path passing through pin g is determined as a critical path.

[Phase] Add the delay tg due to the critical path to the delay at gate E and the delay due to the path length to the input pin h of gate F, and the integrated value of the delay passing through the critical path at the input pin h of gate F: Critical integrated delay Calculate th.

■Similarly, by adding the delay te due to the critical path to the delay at gate D and the delay due to the path length to the input bin i of gate G,
The critical integrated delay ti is calculated.

Similarly, the critical integrated delay tj of the input pin j of the gate G is calculated.

◎Delay ti and tj of input pins i and :j of gate G
Compare. If ti<tj, the path passing through pin j is set as a critical path.

■The critical delay t is added to the delay at gate D and the delay due to the path length to the input pin k of gate H.
e is added to calculate the critical integrated delay tk at the input pin k of the gate H.

[Phase] Add critical delay tj to the delay at gate G and the delay due to the path length to input pin l of gate I to calculate critical integrated delay 12 at input bin l of gate (2).

As a result of the above calculation, the critical cumulative delay at the input pins k and l of the final stage FFs H and I is obtained, and it is possible to check whether the delay conforms to the design criteria.

The digital circuit designer who performed this delay calculation may not only want to know the critical delay value, but also the route taken. Also, F
To perform a delay check (hereinafter referred to as FF check) at the F pin, the clock skew between the FFs on the start and end sides of the critical path is also relevant.

For example, if the critical path leading to the data input pin k of FF-H is from b to e-4 as shown by the broken line, the delay check in FF-H is between the data input pin and the clock pin m. The skew is determined by the relationship between clocks CLKI and CLK2. That is, it is checked whether Tcb + Td + Tske-≦Tcs+r is satisfied.

Here, Tcb: Delay from LSI terminal to pin b.

TCM: Delay from LSI terminal to pin m.

Td: Critical delay value up to pin k.

T skew: Skew value between CLKI and CLK2.

τ: Tukku period.

For example, if the critical path leading to data input pin l of FF-1 is C-4g-4h → j → l as shown by the broken line, the FF check is performed between data input pin l and clock pin n. They use the same clock CLK3 and there is no clock skew.

Conventionally, the following method has been used to trace the critical path at high speed and quickly check clock skew.

(1) By storing the start pin number of the critical path along with the critical cumulative delay value for all passing pins and transmitting it to the end pin, information on the start clock pin during FF check can be quickly obtained. do.

(2) For each pin on the critical path, store the pin number of the preceding stage along with the critical integrated delay value. This makes it possible to trace the critical path without calculating the delay again.

(3) By combining (1) and (2), each pin on the critical path stores both the previous pin number and the starting pin number in addition to the critical cumulative delay value.

[Problem that the invention seeks to solve]

Conventional methods of obtaining clock pin information (1) to (3) above
According to the report, there were the following problems:

(1) After calculating the critical delay, it is necessary to calculate the delay again in order to trace the critical path.

(2) The critical path can be easily found by tracing back from the end pin, but it is also necessary to always trace back when finding the start pin during check.

(3) In large-scale circuits, the number of pins in the entire circuit ranges from tens of thousands to millions, and storing both the preceding pin number and the starting pin number poses a problem in terms of storage capacity.

The present invention aims to provide a critical path analysis processing method that eliminates such conventional problems.

[Means for solving problems]

FIG. 1 shows a principle block diagram of the critical path analysis processing method of the present invention.

In the figure, 1 is a critical delay table, in which each pin has an integrated delay time value of 11 and a previous pin number of 12.
Store.

Reference numeral 2 denotes an event table, which stores the next stage pin number 21 for which the delay time value is to be calculated and the starting pin number 22 for tracing back the critical path to the calculation start point.

Reference numeral 3 denotes a critical delay table creation means, which creates a critical delay table for each flip-flop or gate pin in each stage while referring to the event table 2.

Reference numeral 4 denotes an event table creation means, which creates an event table 2 for each stage while referring to the critical delay table 1.

[For production]

An event table 2 is provided for each FF stage, and the event table 2 stores the next stage pin number 21 to be calculated next.
Proceed with the delay time value calculation. This event table 2
, the starting pin number 2 along with the next pin number 21 to be calculated.
2 will also be memorized.

Calculation of the cumulative delay time value for each pin is performed in the order specified by event table 2, and the calculated cumulative delay time value 1
1 is stored in the critical delay table 1 together with the previous stage pin number 12. Event table 2 is created for each gate stage, and only needs to be prepared for two gate stages.
The processed gate stage table area can be used as a new gate stage table area.

When the calculations are transmitted one after another and the final pin is reached, event table 2 is saved as the starting pin table. The clock skew for the FF check can be determined from the separately stored information on the clock to the start pin and the clock to the final pin.

As described above, the start pin information needs to be provided for each pin (and only the bins of two FF stages are required, so the required storage capacity is significantly reduced.

For example, if the number of pins is 500,000 pins, the number of gate stages is 20, and each start pin requires 8 bytes, the storage capacity required for start pin information is as follows: 500,000 x 8
Bytes = 4 million bytes, and if you want to store it in the event table, the event table 2 for 1 game stage is
The expected amount is 500,000 pins/20 stages = 25,000, so it is approximately 250,000 x 2 x 8 bytes = 400,000 bytes.

〔Example〕

The present invention will be explained in more detail below with reference to embodiments shown in FIGS. 2 to 4.

FIG. 2 is a diagram showing the memory usage status on the main memory in the processing device according to the embodiment of the present invention.

In the figure, -10 is the event table area, and 2
It is thick enough to store an event table for one game stage.

Area 0 is a critical delay table area, and requires a size to store critical tables corresponding to the number of pins of the circuit to be analyzed.

Reference numeral 30 is a critical delay table creation program area, which stores integrated delay calculation routines and others.

Reference numeral 40 denotes an event table creation program area, which stores a next-stage pin detection routine, a delay comparison routine, and a start pin detection routine.

A circuit configuration data area 50 stores various data indicating the configuration of the designed digital circuit.

An initial data area 60 stores initial conditions such as a start pin number, a final pin number, and a critical definition (maximum or minimum delay).

FIG. 3 is a flowchart showing processing according to an embodiment of the present invention.

FIG. 4 is a diagram showing an example of processing according to an embodiment of the present invention.

In FIG. 4, A to I, a-1 and CLKI to CL
K3 indicates an FF or a gate, a pin, and a clock terminal, respectively, as in FIG.

Table (2)-1 shows the event table for the first gate stage, and table (2)-2 shows the event table for the second gate stage. Table (1)-1 shows the critical delay table for each pin of the FF belonging to the first gate stage, and Table (1)-2 shows the critical delay table for each pin of the gate belonging to the second gate stage. . Table (3) is an event table for the final gate stage, indicating that it has become the starting pin table.

Below, follow each step of the flowchart in Figure 4.
The flow of processing according to this embodiment will be explained with reference to FIGS. 2 and 4.

(2) The event table creation program reads the start pin information in the initial condition data stored in the data area, creates table (2)-0 by referring to the circuit configuration data, and stores it in the event table area. In this, a, b, and c are written as the next stage pin information and the starting pin information. When the creation of table (2)-0 is completed, control is passed to the critical delay table creation program.

■The critical delay table creation program calculates the integrated critical delay value ta + tb + tc of pins a and bc according to table (2)-0, creates table (1)-1 by also writing the previous pin number, and calculates the critical delay value. Store in table area. The integrated critical delay values ta, tb, tc are applied to clock terminals CLKI, CLK2 . CLK3 to pin a, b,
The delay value is up to c, and the front pin numbers are a and b.
, c. Once the table (ILI) has been created, control is passed to the event table creation program.

■The event table creation program uses the circuit configuration data to create a table (2) in which next-stage pin d and its starting pin a to be calculated, next-stage pin f and its starting pin a1, as well as e, bSg, and C are listed. 1 and store it in the event table area.

■The critical delay table creation program starts from pin a to pin d to pin a according to table (2)-1.
Calculate the delay values from pin f1 from pin b to pin e1 from pin C to pin g, and add the values td, te, tf, and tg of ta+tb+tc from table (1)-1, respectively.
Table (1) − as the integrated critical delay value
2 is created and stored in the critical delay table area.

■The event table creation program reads the circuit configuration data and determines the next pin to be calculated.

Let it be h. Next, read the critical direction from the initial data area and recognize that it is on the larger side of the delay,
The accumulated critical delay values of pins d and e are shown in the table (
1) Read and compare from -2, and since td<te, the path passing through pin e is set as the critical path to pin, and the starting pin is b, and similarly, tf<tg, so pin g
The path passing through is defined as a critical path to pin h, and the starting pin is C. Next pins are t, h and starting pins b, b,
Create table (2)-2 as c and store it in the location where table (2)-0 in the event table area was previously stored.

■The critical delay table creation program calculates the delay of pin h according to table (2)-2 and creates table (1)-3. Since the path passing through pin g is critical, calculate the delay value from pin g to pin h, add tg to this value, set it as the integrated critical delay value th, add the previous pin number g, and write it in the table (
1) Create -3 and store it in the critical delay table area.

■The event table creation program is table (1)
Create a table (2)-3 regarding pin j from the result of -3 and store it in the location where table (2)-1 was stored in the event table area.

■The critical delay table creation program calculates the delay for pin i and pin j, and creates a table (
1) Create -4 and store it in the critical delay table area.

■The event table creation program creates an event table (2)-4 for pin l. for that purpose,
Read Table (1)-4 and compare the cumulative critical delay values of pin i and pin j.Since ti<tj, it is found that the critical path to pin l is a path passing through pin j, and the starting pin Write C as the number. The created table (2)-4 is stored in the event table area where table (2)-2 was located.

[Phase] The critical delay table creation program calculates the delay for pin k and creates table (1) -
Make 5. In other words, from Table (2)-2, we know that the critical path is b -4e→ Calculate the delay from pin e to pin k, add te to calculate tk, and set the previous pin number e. Add. Next, the delay is calculated for pin l and table (1)-5 is created. In other words, since the critical path is the path passing through pin j,
The delay from pin j to pin 1 is calculated, t3 is added 17 to this to obtain an integrated delay value tJ, and the previous stage pin number j is added. Table (1)-5 shows the integrated critical delay values tk and t of the final stage pin and l.
It is l. The created table is stored in the critical delay table area.

■The event table creation program is table (2)
-2 and table (2) -4, the final pin, and the starting pin information of pin l are extracted and stored in the event table area as table (3).

The starting pin required for clock skew check can be found from table (3).

〔Effect of the invention〕

As explained above, according to the present invention, in delay analysis of large-scale digital circuits, it is possible to trace critical paths and check crosstalk skew at high speed with a small amount of required storage capacity, thereby improving data processing efficiency. The contribution effect is significant.

[Brief explanation of the drawing]

Figure 1 is a block diagram of the principle of the present invention; Figure 2 is a diagram showing memory usage in an embodiment of the present invention; Figure 1 is a flowchart showing processing according to an embodiment of the invention; FIG. 5 is a diagram showing an example of processing according to an embodiment. FIG. 5 is a diagram showing an example of processing according to a conventional example. In the drawing, 1 is a critical delay table, and 4 is an event table creation means. 10 is the critical delay table area, 11 is the cumulative delay time value, 12 is the previous stage pin number, 20 is the event table area, 21 is the next stage pin number, 22 is the start pin number, 3
0 indicates a critical delay table creation program area, 40 an event table creation program area, 50 a circuit configuration data area, and 60 an initial data area. 1st stage 2nd stage Event table 2 Event table 2 pin ■ Bin ■ Bin ■
Bin ■Principle of the present invention Block diagram Figure 1 Main memory

Claims (1)

[Claims] An analytical processing method for delay time in a large-scale digital circuit, comprising: an integrated delay time value (11) for each terminal pin of each flip-flop or gate circuit; and a terminal pin number of the preceding flip-flop or gate circuit. A critical delay table creation means (3) creates a critical delay table (1) storing (12), and a terminal pin number (2
1) and an event table creation means (4) for creating an event table (2) that stores the starting pin number (22) traced back to the starting point of the critical path. A critical delay table (1) and an event table (2) are created for each stage of a gate or a gate, each referring to the other's table, and delay time calculation processing is executed. Path analysis processing method.