JPH04222026A - Program controller - Google Patents

Abstract

PURPOSE:To easily change the contents of a program at a real time by receiving program data from another device and applying an instruction code constituting the program data to a program control means. CONSTITUTION:A CPU 1 to be the program control means for forming a control command in accordance with a program is connected to a program data receiving part 3 through a CPU interface part 2 and fetches a program instruction code. The receiving part 3 receives program data from a master device (program sending device) 5 through a communication channel 4 and sends the received data to the interface part 2. The CPU 1 is connected to a data memory 7 and an I/O controller 8 through a data bus 6 and executes the storage of respective data and the control of the I/O unit 9.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a program control device that processes program instructions that are changed in real time.

0002

2. Description of the Related Art As shown in FIG. 4, a conventional program control device is equipped with a large-capacity memory, and program data is stored in advance in a program stored memory 17, and a CPU 1 uses the data in the memory as an instruction code. Fetching and processing. Types of memory include ROM and RAM. When the memory is ROM, program data is written in advance into a non-volatile memory and installed at the device assembly stage, so it is used in systems that use programs in a fixed manner. Furthermore, if the memory is a RAM, program data is written into the memory all at once from a file unit or a host device through a communication line when the power is turned on. The program is used permanently during power-on operation. The control program is thus capable of changing the program by changing the program data file. In other words, in the conventional example, it has a storage section that stores a program,
It is controlled by the stored data code.

0003

As described above, in the conventional program control circuit, since the program is stored in advance in the storage section, it is difficult to change the program in real time during operation such as process control.

SUMMARY OF THE INVENTION The present invention aims to eliminate these drawbacks, and aims to provide a program control device that can easily change program contents in real time.

[0005]

[Means for Solving the Problems] The present invention provides a program control device equipped with a program control means for generating control commands according to a program, which receives program data coming from another device, and receives instruction codes constituting the program data. The present invention is characterized by comprising a program data receiving section that sequentially provides the program control means with the program data.

Preferably, the program data receiving section includes a communication control section that detects an error in the incoming program data and, when an error is detected, requests the sender of the program data to retransmit the program data.

Furthermore, it is preferable that the communication control section includes a CPU interface section for supplying a NOP code to the program control means in place of the program data in which an error has been detected.

[0008]

[Operation] Stores the normally received program data in a buffer and waits for it to be fetched from the program control means. When an abnormality in the program data is detected, a NOP code is given to the program control means. During this time, the sender is requested to resend the program data. This makes it easy to change program content in real time.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of this embodiment. As shown in FIG. 1, this embodiment includes a CPU 1 which is a program control means that generates control commands according to a program, and further includes a CPU 1 which is a program control means that generates control commands according to a program. The program data receiving section 3 includes a program data receiving section 3 that sequentially supplies the instruction codes constituting the program data to the program control means, and this program data receiving section 3 detects an error in the incoming program data, and when an error is detected, the program data communication control unit 10 that requests retransmission from the source of the
The communication control unit 10 further includes a CPU interface unit 2 for providing the program control means with a NOP code in place of the program data in which an error has been detected.

Next, the operation of this embodiment will be explained. C.P.
U1 is connected to the program data receiving section 3 via the CPU interface section 2, and fetches the instruction code of the program. The program data receiving section 3 is connected to the communication line 4
It receives program data from the higher-level device 5 (program sending device) through the CPU interface section 2, and sends it to the CPU interface section 2. The CPU 1 is connected to a data memory 7 and an IO controller 8 via a data bus 6, and stores data and controls the IO unit 9, respectively.

FIG. 2 is a block diagram of the program data interface section. The program data receiving section 3 includes a communication control section 10, a communication receiver 11, and a communication driver 1.
Consists of 2. Data is received via the communication line 4 and checked by the communication control unit 10 for errors. When normal data is received, the write signal 13 is activated, and the data is output to the received data 14 and sent to the CPU interface unit 2. If there is an error in the data, a negative response is sent through the communication driver 12 to request retransmission of the data. Any type of communication procedure may be used as long as the reliability of this communication is high. The CPU interface section 2 buffers the received data from the communication control section 10, and outputs it to the latch circuit when the program code fetch signal 15 becomes active. If there is no received data, a NOP code is output. The CPU 1 can receive and process the program instruction code 16 by outputting the program code fetch signal 15.

FIG. 3 shows a schematic flow of instruction code processing in this control circuit. The program data receiving unit 3 receives instruction codes A, B, C, and D, but a reception error occurs with instruction code D, and recovery processing (retransmission request processing) is performed. When the recovery is completed, instruction codes D and E- are received. Accordingly, CPU1 performs fetch processing,
They each receive instruction codes A, B, and C and execute processing. NOP while executing recovery process for instruction code D
Receive code. As shown in FIG. 3, the CPU 1 executes instructions in accordance with the received program data (instruction codes A, B, C, D, E-). By doing so, it is possible to change the processing in real time.

[0013] In the above explanation, it is assumed that the communication line 4 is wired as an example, but the same effect can be obtained with wireless communication.

[0014]

Effects of the Invention As explained above, the present invention has a communication control section instead of a storage section for storing program data, handles received data as program data, and has a function of arbitrarily changing communication data. By providing it in a host device, program control can be changed in real time, and it is effective in systems where program instructions can be changed during operation and processing can be changed in real time, such as process control. It also has the effect of eliminating memory for storing large-capacity programs.

[0015]

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the overall configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing details of a CPU interface section and a program data receiving section shown in FIG. 1.

FIG. 3 is a flow diagram showing an outline of program instruction code processing.

FIG. 4 is a block diagram showing the configuration of a conventional example.

[Explanation of symbols]

1 CPU 2 CPU interface section 3 Program data receiving section 4 Communication line 5 Host device 6 Data bus 7 Data memory 8 IO controller 9 IO unit 10 Communication control section 11 Communication receiver 12 Communication driver 13 Write signal 14 Received data 15 Program code fetch signal 16 Program instruction code 17 Program stored memory

Claims (3)

[Claims] Claim 1: A program control device comprising program control means for generating control commands according to a program, which receives program data coming from another device,
A program control device comprising a program data receiving section that sequentially supplies instruction codes constituting the program data to the program control means. 2. The program control according to claim 1, wherein the program data receiving section includes a communication control section that detects an error in the incoming program data and requests retransmission from the source of the program data when an error is detected. Device. 3. The program control device according to claim 1, wherein said communication control section includes a CPU interface section that provides a NOP code to said program control means in place of program data in which an error has been detected.