JPH04207872A - Video signal switching device - Google Patents

Abstract

PURPOSE:To obviate the generation of a disturbance in a screen by imparting the signals of a specific pattern to the screen boundary part of an asynchronous video signal and executing a phase adjustment so as to attain specified intervals when the signals are not at the specified intervals. CONSTITUTION:The video signals inputted to input signal terminals 1 of respective channels are digitalized by an A/D converter 12 of the present system. An intrinsic pattern is then inserted into the part of, for example, the vertical flyback time of the video signals by an intrinsic pattern converting section 13. One of thereof is selected on a signal reception side and a light signal receiver 5 converts this light signal to an electric signal and outputs the signal to a synchronous phase correcting circuit 15. The synchronous phase is corrected in such a manner that the periods of the synchronizing signals attain the specified interval through the synchronous phase correcting circuit 15 and thereafter the prescribed intrinsic pattern is removed by an intrinsic pattern removing circuit 16. This part is returned to the ordinary synchronizing signal. The signal is then converted to an analog signal by a D/A converter 17 and is outputted after decoded to the video signal.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a video signal switching device for arbitrarily switching and outputting a desired channel among video signals of a plurality of channels.

(Prior art) For example, television cameras are installed at various locations in studios, convention halls, event halls, theaters, etc., and the television video signals captured by these television cameras are transmitted to a broadcasting room or broadcasting station. There are systems that perform adjustments, editing, recording, and broadcasting.

In addition to such multiple relay, in remote monitoring devices, video signals obtained from television cameras installed at various locations are sent to a central location where they are monitored or recorded on a VTR or the like.

In this case, there are a plurality of television cameras, and the video signals from each camera are digitally transmitted as asynchronous video signals via transmission paths such as optical cables. Then, these video signals are taken in by selecting any desired channel (the above-mentioned transmission path for any desired television camera) via a channel changeover switch called a switcher.

However, since the video signals of each channel are asynchronous, switching the channel to be captured using a switcher means switching video signals with different frame phases, so the moment the switch is made, a phase jump occurs and the screen on the TV monitor changes. Disturbed. This is very unsightly. For this reason, conventionally, the asynchronous video signal before switching is synchronized with a frame synchronizer, and then switching is performed.

FIG. 5 shows an example of the configuration of a conventional system of this type. The video signal input to the input signal terminal 1 is digitally converted by an A/D converter 2, converted into an optical signal by an optical transmitter 3, and then transmitted via an optical fiber transmission line 4. The signal is received by a first receiver 5 provided at the other end and converted back into an electrical signal, and further converted into an analog signal by a D/A converter 6 to become the original video signal. There are a plurality of television cameras, and the video signals from each television camera are sent to the receiving side through the above-mentioned systems provided in correspondence with the respective television cameras.

Since these video signals are asynchronous, they are synchronized by a frame synchronizer 7 for synchronizing the video signals, and then supplied to a switcher 9. The switch 9 has a plurality of input channels, and when the input channel is designated with the controller 8, the controller 8 controls the switch 9 to pass the video signal of the designated channel. As a result, the video signal of the designated channel from the switch 9, that is, the video signal from the designated television camera, is outputted from the signal output terminal 10.

The frame synchronizers 7 provided for each channel operate in synchronization with the synchronization signal output from the synchronization signal generator 11. Therefore, mutually asynchronous video signals of each channel are processed by the frame synchronizers 7. By passing it through, it will be synchronized and output.

Figure 6 is a diagram showing the state of this internal signal, (a),
As shown in (b), the original video signals A, which are asynchronous to each other,
B is synchronized by a frame synchronizer for each system, thereby producing a synchronized video signal A' as shown in (c) and (d).

B' and these are given to the switcher and switched to become the output video signal X as shown in (e). The output video signal X is initially selected and output as the synchronized video signal A' by the switcher, and the switching command C
At timing t due to H, the switcher outputs the synchronized video signal B.
This shows that the synchronized video signal B' has been switched to the synchronized video signal B' from time t. S
YN is a synchronization signal period, which is a frame boundary indicating the frame phase. Since the synchronized video signals A' and B- are maintained in a frame synchronization relationship with each other, the switcher uses the frame boundary SYN of the video signal. By monitoring and controlling the switching to be performed at the beginning of this frame boundary portion 12, frame synchronization can be achieved, and clean switching can be performed without causing screen disturbance.

FIG. 6(f) shows an example of a signal at the time of switching when synchronization is not performed with a frame synchronizer. In this case, as shown in (f), the video signals A and B are asynchronous and can only be switched in frame synchronization.

Therefore, when switching from video signal A to B, a switching command is given at an arbitrary timing, so that the switcher switches to video signal B in the middle of video signal A, and video signal B also switches to video signal B in the middle of the frame. If there is, not only will the image be displayed from the middle, but also the vertical synchronization of the video signal will be disrupted, which will cause the screen to become out of synchronization and other problems.

(Problem to be Solved by the Invention) As described above, it is possible to individually receive asynchronous video signals for a plurality of channels, input them to a switch, and select and output one of them at the switch. Is there a system that allows a monitor television to display the video of a desired channel? In this case, the video signals of each channel are not in a synchronized relationship, so the moment the channel is switched, the screen becomes out of synchronization due to a phase jump. Therefore, since the screen on the television monitor will be distorted from now on, it will be necessary to perform synchronization adjustment. In order to prevent this, in conventional systems, a frame synchronizer is provided for each channel to align the frame synchronization relationships of each channel to achieve synchronization. Therefore, the above device requires frame synchronizers for the number of channels, which increases the size and cost of the system.

SUMMARY OF THE INVENTION An object of the present invention is to provide a video signal switching device that individually receives asynchronous video signals of a plurality of channels and selects and extracts a video signal of a desired channel among them. To provide a video signal switching device which can realize frame synchronization with a common circuit and can perform video switching in a compact and low-cost manner without requiring a frame synchronizer.

[Configuration of the Invention] (Means for Solving the Problems) In order to achieve the above object, the present invention is configured as follows. In other words, in a system that arbitrarily switches and outputs mutually asynchronous video signals for multiple channels, each input asynchronous video signal of each channel is digitized, and an identification mark is placed on the screen border of the video signal for identification. a first processing means for adding information; a switching means for selecting and outputting a desired channel from among the digital video signals of the respective channels to which identification information has been added; The received digital video signal is monitored, and when the identification information deviates from a specified period, the received digital video signal is and a second processing means that removes the identification information from the digital video signal obtained through the adjustment means, converts it into analog, and outputs it.

Second, in a system that arbitrarily switches and outputs mutually synchronized video signals for multiple channels, each input video signal of each channel is digitized, and its identification is written on the screen border of the video signal. a first processing means for adding identification information for the digital video signal; and a first processing means for selecting and outputting a designated desired channel from among the digital video signals of the respective channels to which the identification information has been added; switching means for switching to the video signal of the designated channel in synchronization with the identification information of the video signal;
A second processing means is provided for removing the identification information from the digital video signal obtained through the switching means, converting the same into analog, and outputting the same.

(Function) In such a configuration, the first configuration is intended for a system that arbitrarily switches a plurality of channels of mutually asynchronous video signals, and in this case, the first processing means processes each input signal. Each asynchronous video signal of the channel is digitized and identification information for identification is added to the screen border of the video signal and output, and the switching means converts the digital video signal of each channel to which the identification information has been added. Among them, the one corresponding to the specified desired channel is selected and output. In response to this, the adjustment means monitors the identification information, and when the identification information deviates from a prescribed period, adjusts the phase of the video signal in response to the deviation in order to keep the period of the screen boundary portion constant. and output it.

The second processing means extracts identification information from this video signal, converts it into analog, and outputs it.

As described above, in the first invention, a signal with a specific pattern is applied to the screen boundary of the asynchronous video signal, and when the signal is not spaced at a constant interval, the phase is adjusted so that the interval is constant. This is to ensure that there is no screen disturbance during switching, and the phase adjustment method involves, for example, detecting the position of the screen boundary in the asynchronous video signal and checking the length of the screen. is temporarily stored in a buffer and then read out, and readout is performed by adjusting the screen length to a specified length according to the checked screen length, or by holding a buffer for multiple frames, This is achieved by temporarily storing the asynchronous video signal that has been switched and output by the switching means in a buffer, and reading out the asynchronous video signal so that the frame length is equal to the specified length. By performing the correction, synchronization is maintained when switching between asynchronous video signals.

Therefore, according to this example, the synchronous phase correction is performed on the asynchronous video signal taken out through the switching means, so it can be shared, and the problem of the conventional problem of requiring frame synchronizers for the number of channels is solved. This makes it possible to realize a small, low-cost system. In addition, since asynchronous switching is possible, an optical switch can be used as a switching means, making it possible to achieve downsizing and low power consumption.

In addition, in the second embodiment, when selecting and extracting the video signal of a specified desired channel from among the synchronized video signals of a plurality of channels, identification information is added to each video signal at the screen separation. Then, when the switching side detects this identification information, it switches to the specified desired channel. This makes it possible to switch channels at screen breaks, and prevents screen disturbances when switching channels.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. In the figure, 1 is an input signal terminal for inputting a video signal, 12 is an A/D converter that converts the video signal input to this input signal terminal 1 into a digital signal, and 13 is an identification for notifying screen divisions. It is a unique pattern conversion unit that adds a predetermined pattern that is information, and it
For example, in the vertical retrace section from the second field to the first field, the boundary can be known from the vertical synchronization signal). Since the period is taken continuously, when such a condition is satisfied, the data of that part is converted into a predetermined unique pattern (unique code). It should be noted that the specific code may be provided in multiple devices in the above-mentioned portion, or may be provided in one device. As a result, in this device, the input video signal is digitized by the A/D converter 12, and a unique code is inserted.

In the case of a video signal, using an example of 10-bit quantization, the quantization level is 1. For example, the blanking level is "OFOH".
, OIRE, white level is “320 H-, 1
00IRE, synchronization level is "010H', -40I"
R.E.

A relationship such as "004H to 3FBH" was found for the video signal full scale, and in the case of 10-bit quantization,
Normally, only “004~3FB)I” is used for the video signal, so “000H~003H”5 “3FC)I~3”
FPH" word can be used as a unique code. In addition, there is a method of adding flag bits in addition to video signal bits, and a transmission path code is CM I (CodedMark).
Inversion) code and mB I C (tn b
jnary 1complement 1nserti
on ) code, etc., CRV (Code Ru1e
It is also possible to use Vioration).

Note that H indicates hexadecimal notation.

Reference numeral 3 denotes an optical transmitter, which receives the digital signal from the A/D converter 13, converts it into an optical signal, and outputs it. In addition, 4 is a transmission line using an optical fiber,
The optical signal converted by the optical transmitter 3 is transmitted. In this system, multiple systems such as 1.13 and 3.4 systems are prepared. Reference numeral 14 denotes an optical switch, which accommodates the other ends of the transmission lines 4 of each of these plurality of systems (channels), and selects any one channel by operating the operator 8 to switch the channels. signal can be extracted.

Reference numeral 5 denotes an optical receiver, which converts the signal (optical signal) output from the optical switch 14 into an electrical signal. Reference numeral 15 denotes a synchronous phase correction circuit, which takes in the output of the optical receiver 5, corrects the synchronous phase so that the period of the synchronous signal is constant, and outputs it. When the unique code is not detected for a predetermined period of time, the circuit outputs the signal with the minimum delay amount, and when the unique code is received, the delay amount is maximized and output, thereby correcting the synchronization phase. Reference numeral 16 denotes a unique pattern removal circuit, which removes the unique code from the output of the synchronization phase correction circuit 15 and outputs the signal back to the normal synchronization signal. Reference numeral 17 denotes a D/A converter that returns the output that has passed through the unique pattern removal circuit 16 to an analog video signal.

The operation of this device having such a configuration will be explained.

The video signal input to the input signal terminal 1 of each channel is digitized by the A/D converter 12 of its own system, and then the unique pattern converter 13 converts the vertical blanking period portion of the video signal into a unique pattern ( digital pattern) is inserted. And after this process is completed,
The signal is input to the optical transmitter 3 of the own system, converted into an optical signal, and then transmitted through the transmission line 4 using an optical fiber. On the receiving side, the other end of the transmission line 4 of each system is accommodated in an optical switch 14, and by switching the optical switch 14, one of these is selected, and the optical signal of the selected system (channel) is transmitted. is input to the optical receiver 5. The optical receiver 5 converts this optical signal into an electrical signal and outputs it to the synchronous phase correction circuit 15. If the channel of the 8-power signal from the optical receiver 5 is switched midway through the optical switch 14, there is no synchronization relationship with the video signal between each channel, so when converted to an analog image, the field length is as shown in Figure 6(f). becomes abnormal. If this continues, problems will occur such as the screen on the television monitor (receiver) being distorted.

Therefore, after the synchronization phase is corrected through the synchronization phase correction circuit 15 so that the period of the synchronization signal is constant, the specific pattern removal circuit 16 removes the predetermined specific pattern and converts this part into a normal synchronization signal. D/A after returning
The converter L7 performs analog conversion to restore the video signal and output it.

FIG. 6(g) is an example of this output waveform. For example, in synchronization phase correction, the received data is stored once and the synchronization phase is corrected by adjusting the timing at which it is read out, so it is read out later than the time it is captured, and the frame length is changed at the time it is captured. By checking the frame length of the captured data, the excess or deficiency of the frame length of the captured data relative to the standard frame length can be temporally adjusted by adjusting the read timing, making it possible to match the synchronization phase. for example,
If the field length becomes long when switching from asynchronous video signal A to asynchronous video signal B at the timing shown in FIG. Since the next unique code is not detected even after a period of time corresponding to the specified field length has elapsed from the time when the pattern (pattern) was detected, it is determined that there is an abnormality at this stage. By this amount, the amount of delay on the read side is adjusted to be shortened. If a unique pattern is detected before the specified field length period is reached, the field length is shorter than specified, so
The amount of delay on the read side is increased to compensate for the shortage. By performing such adjustment in the synchronization phase correction circuit 15, the field length can be adjusted and the synchronization phase can be corrected so that the period of the synchronization signal becomes a constant interval. Note that depending on the correction method, the screen switching position can also be set at the field boundary.

Figure 2 shows a synchronous phase correction circuit 1 using a variable length delay.
5, a unique pattern detector 18 which takes the output signal from the optical receiver 5 as an input signal, detects a unique pattern in this input signal and generates a detection output, and from the unique pattern detector 18. It is reset in response to the detection output of
A timer 19 measures time from an initial value and outputs the previous time value as time information for the unique pattern detection cycle each time it is reset, and the timer 19 reads the input signal from the optical receiver 5, usually after a predetermined delay. The variable length delay 20 receives clock information from the timer 19 and changes the delay time to a value corresponding to the clock information.

In such a configuration, the input signal is input to the unique pattern detector 18 and the variable length delay 20, and the variable length delay 20 delays it by a predetermined delay time and outputs the signal to the D/A converter I7. output to the side.

On the other hand, when the unique pattern detector 18 detects a unique code from the input signal, it generates a detection output.

This detection output is given to the timer 19, and the timer 19 is thereby reset and starts counting from the initial value, or at the time when the detection output is received, the timer 19 converts the time value up to that point into a variable-length delay-20. give to Then, the variable length delay 20 resets the delay time to a delay time corresponding to this time value, delays the input signal from the optical receiver 5 by the delay time, and outputs the delayed signal. Assuming that the variable length delay 20 is output with a delay of at least one screen in the standard state, the optimal delay amount is obtained after checking the screen frame length from the sequentially input video signals, By delaying with this amount of delay, it is possible to correct the synchronization for each screen, and by switching the asynchronous video signal, it is possible to prevent screen disturbances due to synchronization or mismatch.

This variable length delay 20 uses a frame memory to store at least one frame's worth of input signals (data), and if readout is adjusted, the input signal can be delayed by a desired amount. It is also possible to use a method of controlling the readout position using a shift register for one frame, and thereby it is possible to prevent video data from being cut off at the time of delay change without using a frame memory.

FIG. 3 shows another configuration example of the synchronous phase correction circuit 15,
Reference numerals 21a and 21b are frame memories, respectively, for storing digital signals (video signals) from the optical receiver 5, and 23 are these frame memories 21a, 21b.
This is a selection switch for alternately extracting the read data of 21b one frame at a time.

Further, I8 is a unique pattern detection circuit, which detects a unique pattern from the digital signal (video signal) from the optical receiver 5 and outputs a detection signal, and 22 is a control unit, which includes a frame memory 21a, It performs read/write mode switching and address control of the frame memories 21a and 21b, selection switching control of the switch 23 for output selection of the frame memories 21a and 21b, and the like. When the detection signal output from the unique pattern detection circuit 18 is detected at a normal cycle, that is, when the control section 22 is out of synchronization, the control section 22 controls the frame memory 2 every time it receives the detection signal.
1a and 21b are selected alternately, and the input data is written to the selected one from the beginning, and the frame memory on the side where writing has been completed is set in accordance with the vertical synchronization timing of the TV scan, and at the same time as the speed of the TV scan. Control is performed such as reading from the beginning according to the timing. Further, the control section 22 controls the selection and switching of the output selection switch 23 so as to pass the read output data of the frame memory on the side that is being read. Furthermore, the control unit 22 controls reading of this frame memory so that reading is performed on the frame memory for which writing has been completed, or if a detection signal of the unique pattern is not obtained even after a specified time has elapsed, The frame memory in the read mode is controlled to be repeatedly read out successively, and when a unique pattern detection signal is received during this read, the mode of the frame memories 21a and 21b is not switched this time, and the frame memory in the read mode is read out. Then, the frame memory of the write mode is controlled to clear its contents and start writing from the beginning. Then, the control section 22
The reading start timing is performed at the vertical synchronization timing of the TV scan, and the writing of input data is synchronized with the vertical synchronization timing of the asynchronous video signal, so the two are not in a synchronous relationship, so as a frame memory, dual port memory etc. can be written and read at the same time. It has a function that uses accessible memory and controls the writing to start from the beginning position of the other frame memory that has already been read when writing to one frame memory is completed. It is set.

In such a configuration, writing and reading are normally performed alternately in the two frame memories 21a and 21b. In writing, the starting position of the screen is known from the detection signal output from the unique pattern detection circuit 18, and input data is stored in order from the starting address position of the frame memory. In addition, at the stage when data for one screen has been written, the written data is read out for one frame in sequence at a timing set to match the vertical synchronization timing of television scanning, and is used for output selection. The signal is output to the lower stage side via the switch 23. The input data is asynchronous video signal data, and the frame is not synchronized with the reading side.

Therefore, while one frame memory is being read, data for one frame of the asynchronous video signal may be written to the frame memory that is being written. However, in this case, the control unit 22 starts writing the next frame of the asynchronous video signal from the beginning of the one frame memory that is being read. In this way, when the frame length of the input asynchronous video signal is normal, the data of the input asynchronous video signal is written into the frame memory alternately for each frame, and the writing is completed. By performing a reading comparison from the frame memory of the frames, it is possible to obtain synchronized video signal data with a constant frame length.

Normally, writing and reading are performed alternately in the two frame memories 21a and 21b, or if a unique pattern cannot be detected even after a specified period of time has elapsed, no detection signal can be obtained, so the two frame memories 21a and 21b are Memory 21a, 2
Since 1b is only switched between write and read mode, the contents of the frame memory in the read mode are repeatedly read out. Also, 1
If a unique pattern is detected before a specified time, which is the standard time required to read one frame's worth of data, the frame memory that is being written is cleared, and the writing is controlled to start from the beginning of the frame. In this case, when the reading of the other frame memory is completed, writing to this memory has not yet been completed, so the control is performed so that the contents of the same frame memory are read twice and then the normal operating state is entered.

In short, the embodiments shown in FIGS. 1 to 3 are systems that arbitrarily switch and output asynchronous video signals for multiple channels, and the asynchronous video signals are provided with identification codes at frame boundaries. , detects the frame boundary position in the switched and output asynchronous video signal and checks the frame length, and also temporarily stores the output asynchronous video signal in a buffer and reads it out. The synchronization phase is corrected by adjusting and outputting the frame length to a specified length (1/30 sec) according to the checked frame length, and synchronization is maintained when switching asynchronous video signals. Alternatively, the asynchronous video signal that has been switched and outputted by the switching means is temporarily stored in a buffer when the frame length is a specified length, and the video signal that has been output after being switched by the switching means is temporarily stored in a buffer. It reads out the asynchronous video signal and outputs it, thereby correcting the synchronous phase and
This is to maintain synchronization when switching asynchronous video signals.

Therefore, according to this embodiment, the synchronized phase correction is performed on the asynchronous video signal taken out via the switching means, so it can be shared, and five frame synchronizers are required for four channels as in the conventional case. This problem can be solved and a small, low-cost video signal transmission system can be realized. Furthermore, since asynchronous switching is possible, an optical switch can be used as a switching means, which has the advantage of being compact and reducing power consumption. The above buffers include variable length delay, shift register, frame memory, and F.
IFO (Fast In Fast Out) type elastic memory etc. can also be used.

The above is an example of synchronized phase correction using a buffer, or if the video signal is synchronized, the channel is switched without using a buffer and at the timing of frame switching. . Such channel switching is performed by a switcher. In other words, a switcher is a switching device that switches and outputs video signals for multiple channels that are supplied. For example, when considering an application where video signals of multiple channels are edited and recorded or displayed, it is necessary to switch between channels when switching channels. It is necessary to ensure that there is no disturbance in the image. To do this, for example,
It is necessary to switch during the synchronization signal period in the video signal, and in such a case, the switching timing detection technique using the unique pattern as described above can be used.

This example will be explained below.

FIG. 4 shows an embodiment according to the present invention, 31a to 31n
32a to 32n are A/D converters, respectively, and 32a to 32n are A/D converters, each of which outputs a corresponding one of the video signal generators 31a to 31n. This converts video signals into digital data. Each of the A/D converters 32a to 32n has a switching timing signal addition function. These A/D converters 36a to 36n
The timing at which the video signal can be switched, for example,
It has a function of inserting a specific pattern into a synchronization signal period such as a vertical retrace period. Of course, this feature is the first
As in the embodiment shown in the figure, a unique pattern converting section that detects a signal period indicating a pattern of the synchronizing signal period and inserts a specific pattern into this portion may be provided separately. 33 is a switcher, and the A/
The outputs of the D converters 32a to 32n are individually inputted, and one of the outputs of these A/D converters 32a to 32n is selected and switched to be output. The switch 33 has an input section 33a that detects the unique pattern from the input video signal data of each channel to detect synchronization timing, and generates a switching timing signal at the time of detection, and switches the switching. The device 33 has a function of switching to the instruction channel of the switching operation device 35 in synchronization with this switching timing signal.

34 is a synchronizing signal generator, 36 is a D/A converter, 37
are video equipment such as VTRs and monitors.

The synchronization signal generator 34 outputs a signal corresponding to the vertical synchronization timing of the video signal, and this signal is given to each video signal generator 31a to 31n so that the vertical synchronization timing matches this signal. control and output a video signal. Further, the switching operation device 35 is used to perform an operation for switching channels on the switching device 33, and by operating this, the switching device 33 switches each channel input from the A/D converter. One of the video signals is selected and output. Further, the D/A converter 36 has an input section 36a, which converts input data into an analog signal, and the input section 36a converts the unique pattern in the data to its original level.

In this way, the D converter converter 36 has the function of converting the data outputted through the switch 33 into an analog signal, and the function of converting the unique pattern in the data to its original level. Therefore, as in the example shown in FIG. 1, a configuration may be adopted in which the function of converting the unique pattern to the original level is provided separately and this function is placed before the D/A converter 36. That is, the unique pattern removal circuit 16 is placed before the DIA converter.

In such a configuration, the synchronization signal generator 34 generates a signal corresponding to the vertical synchronization timing of the video signal and supplies this to the output video signal generators 31a to 31n, so the output video signal generators 31a to 31n A video signal is output in synchronization with this signal. Output video signal generators 31a-3
Each of the 1n output video signals is converted into a digital signal by the corresponding D/A converter 36a to 36n, and inputted to the switch 33 as a respective digital video signal.

Each of the D/A converters 36a to 36n is provided with a function of inserting a specific pattern into a switchable timing of the video signal, for example, a synchronization signal period such as a vertical retrace period. Therefore, a unique pattern is inserted into the synchronization signal period of the digitally converted video signal so that it can be identified.

As an example of the second unique pattern signal, as mentioned above, in the case of 10-bit quantization, “000H to 0033H
",", "3FCH to 3FFH" can be used. Also, in 8-bit quantization, if all "OOH to FFH" are used, it is sufficient to use 9-bit data and set a flag at the timing position.

The digital video signal of each channel to which the unique pattern has been added in this way is sent to the switch 33 at its input section 33a.
Input via . The input section 33a detects this unique pattern, detects the timing, and applies it to the switch 33 as the switching timing. Now, if the switching operation device 35 is operated to instruct switching from the currently selected channel to another channel, the switching device 33 responds to the switching timing of the input section 33a to switch from the currently selected channel to the channel currently selected. It switches to the designated channel, outputs the input data from that channel, and sends it to the D/A converter 36 side.

The input section 36a of the D/A converter 36 converts the data of the unique pattern in this data back into the signal level data of the original synchronizing signal period, converts it into analog, and outputs the final video signal. This final video signal output is then given to a video device 37 or the like for recording or display.

In this way, when multiple channels of mutually synchronized video signals are digitized and sent individually, and the receiving side selects and extracts the video signal of the desired channel using a switcher, it is possible to In order to be able to switch channels at intervals of By providing the function of switching to a designated channel and controlling the switching, the switcher itself can determine the switching timing from the video signal itself, making it possible to switch channels without disturbing the screen.

It should be noted that the present invention is not limited to the embodiments described above and shown in the drawings, but can be implemented with appropriate modifications within the scope of the gist. It can also be applied to television broadcasting), surveillance monitor systems, industrial television systems, etc.

[Effects of the Invention] As explained above, according to the present invention, in a video signal switching device that receives video signals of a plurality of channels and selects a desired one of them as an output video signal, channel switching is performed. You can sometimes switch between screens to avoid screen clutter.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIGS. 2 and 3 are block diagrams showing a configuration example of a synchronous phase correction circuit according to the present invention, and FIG. 4 is a block diagram showing an example of application of the present invention. FIG. 5 is a block diagram showing an example of a conventional video signal switching system, and FIG. 6 is a diagram for explaining the operation of FIGS. 1 and 5. DESCRIPTION OF SYMBOLS 1... Signal input terminal, 3... Optical transmitter, 4... Transmission line, 5... Optical receiver, 8, 35... Switching operation device, 1
o...Signal output terminal, 12...A/D converter,
13... Unique pattern converter, 14... Optical switch, 15... Synchronous phase correction circuit, 17... D/A converter, 18... Unique pattern detector, 19... Timer, 20 ...Variable length delay-121a, 21b
...Frame memory, 22...Control unit, 23...Switch, 32a-32n...A/D converter with unique pattern insertion circuit, 33...Switcher, 36...With unique pattern removal circuit D/A converter. Applicant's agent Patent attorney Takehiko Suzue Figure 2 Figure 3 YN Figure 6

Claims (2)

[Claims] (1) In a system that arbitrarily switches and outputs mutually asynchronous video signals for multiple channels, each input asynchronous video signal of each channel is digitized, and a mark is placed on the screen border of the video signal for identification. a first processing means for adding identification information; a switching means for selecting and outputting a desired channel from among the digital video signals of the respective channels to which identification information has been added; and outputting via the switching means. The received digital video signal is monitored, and when the identification information deviates from a specified period, the received digital video signal is An adjustment means for adjusting the phase of the signal, and a second processing means for removing the identification information from the digital video signal obtained through the adjustment means, converting it into analog, and outputting it. A video signal switching device characterized by: (2) In a system that arbitrarily switches and outputs mutually synchronized video signals for multiple channels, each input video signal of each channel is digitized, and an identification mark is placed on the screen border of the video signal for identification. a first processing means for adding information; and a means for selecting and outputting a designated desired channel from among the digital video signals of each channel to which identification information has been added; a switching means for switching to the video signal of the designated channel in synchronization with the identification information; and a second process for removing the identification information from the digital video signal obtained through the switching means, converting it into analog, and outputting it. 1. A video signal switching device comprising: means.