JPH04205678A - Image information processor - Google Patents

Abstract

PURPOSE:To allow the change of always the assigned plane alone by moving the access bit position memory data to the top by a barrel shifter even if image data does not begin from the top of the access data of a bit map memory. CONSTITUTION:This device is constituted of a CPU 1, a direct memory access controller 2, a memory section 5, a raster arithmetic processor 6, a magnification and reduction circuit 7, a compression and expansion circuit 8, an optical disk device 9, a scanner 10, a printer 11, and bus controllers 12 to 15. The memory data is rotated to match the position of the mask data even if the data of one picture element extends across the word boundary which is the max. number of the bits to execute data processing and, therefore, the masking processing to the assigned bit is executed even if the constitution of the data changes dynamically. Always the assigned plane alone is changed in this way.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention performs logical operation processing and arithmetic operation processing on image information stored on a bitmap memory to create a new image. The present invention relates to an image information processing device that creates information.

(Prior Art) Conventionally, this type of image information processing device has been equipped with a mask register that matches the memory configuration of the bitmap memory, and has been equipped with a mask register that matches the memory configuration of the bitmap memory, and has a mask register that stores the calculated data as a result of the calculation and the bitmap memory to which the calculated data is written. Mask processing was performed by using the data in the mask register as a selection signal with the test nation data.

However, since the mask register was set to match the memory configuration of the bitmap memory, the pixel configuration must be such that the pixel data can fit within a data boundary that can be accessed at once depending on the memory configuration of the bitmap memory. was there.

That is, as shown in FIG. 8(a), in an image information processing device capable of processing 8-bit data, if one pixel is composed of 4 bits, the pixel data will fit within the 8-bit boundary. By preparing 8-bit mask data, it is possible to change only the specified plane, but if one pixel is composed of 3 bits as shown in Figure 8(b), the pixel data There are cases where an 8-bit data boundary is crossed, and if the mask data is used as is in accordance with the memory data, there is a problem that only the specified plane cannot be changed.

(Problems to be Solved by the Invention) Conventionally, as described above, pixel data had to be stored within a data boundary that could be accessed at once by matching the mask register to the memory configuration of the bitmap memory. Furthermore, when the pixel data does not fit within a data boundary that can be accessed at once, there is a problem in that if the mask data is used as is in conjunction with the memory data, only the designated plane cannot be changed.

Therefore, the present invention allows you to use a specified plane without adjusting the mask register to the memory configuration of the bitmap memory, and even if the pixel configuration does not allow pixel data to fit within the data boundary that can be accessed at any time. An object of the present invention is to provide an image information processing device that can only change the image information processing device.

[Configuration of the Invention (Means for Solving the Problems) The image information processing device of the present invention includes a storage means for storing input image information, and an operation for performing calculations on the image information stored in the storage means. means, a storage means for storing mask data for performing a masking process such that only the specified image information is subjected to arithmetic processing and no other image information is changed; and the arithmetic results of the arithmetic means and the storage means. and selecting means for selecting the image information stored in the storage means and for not changing the image information in the storage means for bits designated by the mask data.

(Function) According to the image information processing device of the present invention, even if the pixel data does not start from the beginning of the access data of the bitmap memory by the above means, the access bit position of the memory data can be moved to the beginning by the barrel shifter. Therefore, mask processing becomes possible, and even if the access bit position changes dynamically, only the specified plane can be changed.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 schematically shows the configuration of an image information processing apparatus according to the present invention. In other words, the system system 5 consists of a CPU that controls the entire system, a direct memory access controller 2 that performs memory transfer, a display memory 3 that is a frame memory for display, and a main memory 4 that stores program data and image data. A memory unit 5, a display 3 that displays the contents of the display memory 3, a rask arithmetic processor 6 that can access bits and perform various operations on image data, and a scaling circuit that scales up and down the image data. 7, a compression/expansion circuit 8 that compresses and expands image data, an optical disk device 9 that stores compressed image data, a scanner 10 that reads document images, a printer 11 that outputs image data, and a bus controller that controls between buses ( B/C) 12.1B, 14, 1.5.

In such a configuration, image data read by the scanner 10 is stored in the display memory 3 or main memory 4 of the memory unit 5 via the bus controller 14 and the rask calculation processor 6. The image data stored in the memory section 5 can be edited using the functions of the rask calculation processor 6. Furthermore, in order to perform high-quality scaling, the image data is read out from the memory section 5, passed through the rask arithmetic processor 6, enlarged/reduced by the enlarging/reducing circuit 7, and then read out again via the rask arithmetic processor 6. This is possible by writing into the memory section 5. Printing out the image data stored in the memory section 5 is executed by the rask calculation processor 6 reading the image data from the memory section 5 and outputting it to the printer 11 via the bus controller 14.

Next, the rask arithmetic processor 6 that performs image processing will be explained in detail with reference to FIG.

The Rask calculation processor 6 has an image interface (I/F) 20 that performs interface control with an image bus to which a scaling circuit 7 and a compression/expansion circuit 8 are connected.
．． A drawing sequencer 21 that performs sequence control of pattern drawing, copying, data exchange, etc., an address generator 22 that generates addresses for accessing memory, and image data accessed by an arbitrary bit address by the address generator 22. , an arithmetic processing unit 23 that can perform various arithmetic processes, etc., and a memory interface (I/F) that interfaces with the memory unit 5.
) 24, and a controller 25 for controlling the entire raster arithmetic processor 6.

In such a configuration, the image interface 2
The image data input from 0 is sent to address generator 2.
The address generated by 2 is written to the storage location of the memory unit 5 indicated by the address through the arithmetic processing unit 23 and the memory interface 24.

Since the image data at this time can be written to any bit address, read-modify-write processing is performed on the memory section 5. That is, the data at the word address indicated by the address generator 22 is once read out from the memory section 5, taken into the arithmetic processing section 23, subjected to arithmetic processing and masking processing with the data input from the image interface 20, and then read back into the memory section 5. Write. By operating in this manner, data processing can be performed from any bit address position.

Next, the arithmetic processing section 23 will be explained in detail using FIG. 3. The arithmetic processing unit 23 includes a logic arithmetic unit 30 . an arithmetic operation unit 31 that performs arithmetic operation processing;
A selector 32 selects the results of the logical operation section 30 and the arithmetic operation section 31, a latch section 33 that latches data from the memory section 5, and rotates the memory data latched in the latch section 33 according to the offset address of the address generator 22. , a barrel shifter 34 that moves the accessed bit to the 0th bit position, and a masking process that selects either the memory data after rotation from the barrel shifter 34 or the data of the arithmetic processing result, and generates a control signal for performing masking processing. A selector 36 selects between the memory data rotated by the barrel shifter 34 and the operation result selected by the selector 32 based on the mask data from the mask processing unit 35, and the data subjected to the masking process selected by the selector 36. , a barrel shifter 37 that rotates according to the offset address from the address generator 22 and returns the data to a position on the memory, a pattern RAM 38 that stores pattern data, a temporary arithmetic processing section 23 that reads data read from the memory section 5 and performs arithmetic processing on the data. a register 39 stored internally; a selector 4 for selecting between image data input from the image interface 20 and data stored in the register 39;
0, buffers 41, 42, 43, and 44.

In such a configuration, the logical operation unit 30 uses source data, that is, data input from the image interface 20 or data latched in the internal register 39, destination data, that is, data in the memory unit 5, A ternary operation is possible with the pattern data stored in the pattern RAM 38.

Furthermore, the arithmetic operation section 31 is capable of performing binary operations on two of the data described above. Here, assuming that the memory data is 8 bits as shown in the upper part of FIG. 7, the offset address (lower address of the bit address) from the address generator 22 causes the barrel shifter 37 to Rotation is performed so that the data of the access address is aligned with the Oth bit, and is input to the logic operation section 30 and the arithmetic operation section 31.

Next, the mask processing section 35 will be explained in detail using FIG. 4. In this embodiment, in order to simplify the explanation, data processing by the arithmetic processing section 23 is assumed to be 8 bits at maximum. Therefore, the maximum amount of data that can be accessed in memory at one time is 8 bits. That is, the mask data register 50 has 8
This is a bit data register and can be set by the CPU. Mask processing is performed when the mask data is "1", and the calculation result is used for "0". Here, it is assumed that a maximum of 8 bits of mask data from the bit address position indicated by the address generator 22 is set in the mask data register 50. The access mask generation unit 52 is a block that generates a mask that performs masking processing on bits other than the bits that are actually accessed from the −11=offset address and access width.

FIG. 5 explains the mask data generated by the access mask generation unit 52. In the case of FIG. 5(a), the offset address is "2" and the access width is "2".
3", when the address switching signal is rLJ, the 4th bit from the 0th bit becomes "0" and no mask processing is performed.
Data processing becomes possible. Here, the address switching signal is a signal indicating the next 8 bits on the memory. Therefore, when the address switching signal is rHJ, the access width is "3" and is 4 bits, so the next 8 bits are not accessed and all are rJ.

Next, in the case of FIG. 5(b), that is, the access width is "7".
”, in the case of 8-bit access, the access mask generation unit 5
In the mask data generated in step 2, when the address switching signal is rLJ, the 6th bit from the θ-th bit is “0”.
When the address switching signal is rHJ, the 6th and 7th bits become "0" and data processing becomes possible.

Then, the final mask data is stored in the mask data register 5.
Mask data stored in 0 and access mask generation unit 5
Using the data taken by the OR circuit 53 from the mask data generated in step 2, the selector 36 selects the data after the arithmetic processing for the "0" bit I. In this case, masking processing is performed by selecting data latched by the latch unit 33 and rotated by the barrel shifter 34.

Here, the purpose of the mask data set in the mask data register 50 is, for example, as shown in FIG. 8(a).
When handling a color image, the memory configuration is a packed pixel configuration, the pixel is 4 bits, and 1 plane is 1 bit, when the memory is accessed, the 8 bits accessed to memory will contain data for 2 pixels. If the access width is set to 8 bits, all 8 bits become new data. However, if it is desired to change only a certain specified plane, by using mask data, it becomes possible to rewrite only the plane specified by the mask data. Furthermore, in the conventional example, when one pixel has three bits as shown in FIG. 8(b), one pixel may span two words (here, one word = 8 bits). At this time, since the mask data is directly applied to the 8 bits of one word, the specified plane (O bit 1 of one pixel) cannot be subjected to masking processing.

However, according to the present invention, a barrel shifter is provided after the memory data is latched, the memory data is rotated to make it an offset address, and masking processing is performed using mask data using this data and the calculation result, as shown in FIG. As such, masking processing can be performed accurately on the designated plane. That is, when processing image data using 3 bits per pixel in a memory configured to allow 8 bits per access, processing is possible in units of 2 pixels. At this time, a mask is set in the mask data register so that the 0th plane in one pixel is set to "0" and the 0th plane is rewritten. 6th
In the case of (A) in the figure, since the offset address is "0", the memory data is not rotated but masked. Here, since it is a 6-bit access,
The access width is "5", which is a 6-bit access, and the access mask generation section 52 generates "0" for the first 6 bits. Therefore, in the final mask data, the 0th and 3rd bits become "0", the bits in this part become "1", and are written to the memory section 5. Next, in the case of (B) in FIG. 6, since the offset address is 6, the data read from the memory section 5 is rotated by 6 bits by the barrel shifter 34.

Here, since only the 8 bits shown in FIG. 6(a) can be accessed to the memory, processing is first performed on the 6th bit and 7th bit "1" shown in FIG. 6(a), and then, Using the address switching signal rHJ, processing is performed on the next 8 bits, 8 bits shown in FIG. 6(b). At this time,
Using the mask data generated by the access mask generation section 52, processing is performed on 4 bits from the 0th bit of the memory. By repeating the above steps, even if one pixel data spans two memory addresses, it is possible to perform mask processing on a designated plane.

As explained above, according to the above embodiment, even if one pixel data straddles a word boundary, which is the maximum number of bits for data processing, the memory data is rotated to match the position of the mask data. , it is possible to perform masking processing on specified bits even if the data structure changes dynamically. Therefore, it is effective for data processing when handling color images and the like. Furthermore, the number of bits in one pixel can be changed to 1 bit, 2 bits, 4 bits,
Since there is no need to use 8 bits, 16 bits, and 32 bits to a power of 2, R
, GSB, 8 bits each, making it possible to configure the memory with 24 bits per pixel, so the memory capacity can be reduced.

[Effects of the Invention] As described in detail above, according to the present invention, the mask register does not need to match the memory structure of the bitmap memory, and the pixel data can be stored within the data boundary that can be accessed at every time. Even if it is not configured,
An image information processing device that can change only a designated plane can be provided.

[Brief explanation of the drawing]

1 to 7 are for explaining one embodiment of the present invention. FIG. 1 is a block diagram schematically showing the overall configuration of an image information processing device, and FIG. 2 is a rask calculation processor. 3 is a block diagram showing the configuration of the arithmetic processing section in the rask arithmetic processor, FIG. 4 is a block diagram showing the structure of the mask processing section in the rask arithmetic processor, and FIG. 5 is an access FIG. 6 is a diagram for explaining the mask data generated by the mask generation unit, and explains the relationship between the mask data and data processing in the memory.
7 is a diagram for explaining the rotation of memory data, and FIG. 8 is a diagram for explaining conventional mask processing. DESCRIPTION OF SYMBOLS 1...CPU, 2...Direct memory access controller, 3...Display memory, 4...Main memory, 5...Memory section, 6...Rusk calculation processor, 7. Enlarging/reducing circuit, 8... Compression/expansion circuit, 9...
Optical disk device, 10...Scanner, 11...Printer, 12゜13.14.15...Bus controller, 20...Image interface, 21...Drawing sequencer, 22...Address generator , 23...
Arithmetic processing unit, 24...Memory interface, 25
...Controller, 30...Logic operation section, 31...
・Arithmetic operation section, 32゜35.40...Selector, 33
．． 37...Barrel shifter, 34...Latch portion, 36
...Mask processing unit, 38...Pattern RAM, 39
...Register, 4], 42°43.44...Buffer, 50...Mask data remask, 51...Barrel shifter, 52...Access mask generation unit, 53...
・OR circuit. OCp Dimension I + J Actual ' ＼ : 1 t.'

Claims (2)

[Claims] (1) A storage means for storing input image information, an arithmetic means for performing predetermined operations on the image information stored in this storage means, and an operation means for performing arithmetic processing only on specified bits and for other operations. a storage means for storing mask data that performs mask processing so that image information is not changed for bits; a calculation result in the calculation means and image information stored in the storage means; An image information processing apparatus comprising: a selection means for not changing the image information in the storage means for bits designated by data. (2) The mask data stored in the storage means starts from the beginning of the pixel, and includes a barrel shifter that rotates the data on the memory so that the access bit position becomes the beginning, and after passing through the barrel shifter, 2. The image information processing apparatus according to claim 1, wherein the selection means selects the data and the calculation result using the mask data.